170 lines
5.0 KiB
C
170 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT_EMI_BW_LIMITER__
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#define __MT_EMI_BW_LIMITER__
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/*
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* Define EMI hardware registers.
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*/
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#define EMI_CONA (EMI_BASE_ADDR + 0x0000)
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#define EMI_CONB (EMI_BASE_ADDR + 0x0008)
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#define EMI_CONC (EMI_BASE_ADDR + 0x0010)
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#define EMI_COND (EMI_BASE_ADDR + 0x0018)
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#define EMI_CONE (EMI_BASE_ADDR + 0x0020)
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#define EMI_CONF (EMI_BASE_ADDR + 0x0028)
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#define EMI_CONG (EMI_BASE_ADDR + 0x0030)
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#define EMI_CONH (EMI_BASE_ADDR + 0x0038)
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#define EMI_TESTB (EMI_BASE_ADDR + 0x00E8)
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#define EMI_TESTD (EMI_BASE_ADDR + 0x00F8)
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#define EMI_ARBA (EMI_BASE_ADDR + 0x0100)
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#define EMI_ARBB (EMI_BASE_ADDR + 0x0108)
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#define EMI_ARBC (EMI_BASE_ADDR + 0x0110)
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#define EMI_ARBD (EMI_BASE_ADDR + 0x0118)
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#define EMI_ARBE (EMI_BASE_ADDR + 0x0120)
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#define EMI_ARBF (EMI_BASE_ADDR + 0x0128)
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#define EMI_ARBG (EMI_BASE_ADDR + 0x0130)
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#define EMI_ARBG_2ND (EMI_BASE_ADDR + 0x0134)
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#define EMI_ARBH (EMI_BASE_ADDR + 0x0138)
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#define EMI_ARBI (EMI_BASE_ADDR + 0x0140)
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#define EMI_ARBI_2ND (EMI_BASE_ADDR + 0x0144)
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#define EMI_ARBJ (EMI_BASE_ADDR + 0x0148)
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#define EMI_ARBJ_2ND (EMI_BASE_ADDR + 0x014C)
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#define EMI_ARBK (EMI_BASE_ADDR + 0x0150)
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#define EMI_ARBK_2ND (EMI_BASE_ADDR + 0x0154)
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#define EMI_SLCT (EMI_BASE_ADDR + 0x0158)
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#define LOW_POWER_CORRELATION
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#ifdef LOW_POWER_CORRELATION
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enum TRANS_TYPE {
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R = 0,
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W,
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RW
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};
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extern phys_addr_t dram_rank0_addr;
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extern unsigned int bw_mon_in_ms(enum TRANS_TYPE trans_type, unsigned int ms);
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extern unsigned int get_dram_data_rate(void);
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#define CLK_CFG_0 (CKGEN_BASE_ADDR + 0x100)
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#define CLK_CFG_5 (CKGEN_BASE_ADDR + 0x150)
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#define CLK_CFG_0_CLR (CKGEN_BASE_ADDR + 0x108)
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#define CLK_CFG_UPDATE (CKGEN_BASE_ADDR + 0x900)
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#define EMI_BMEN (EMI_BASE_ADDR + 0x0400)
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#define EMI_BCNT (EMI_BASE_ADDR + 0x0408)
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#define EMI_WSCT (EMI_BASE_ADDR + 0x0428)
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#define EMI_MSEL (EMI_BASE_ADDR + 0x0440)
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#define EMI_MSEL2 (EMI_BASE_ADDR + 0x0468)
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#define EMI_BMEN2 (EMI_BASE_ADDR + 0x04E8)
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#define EMI_BMRW0 (EMI_BASE_ADDR + 0x04F8)
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#define EMI_IOCL (EMI_BASE_ADDR + 0x00D0)
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#define EMI_IOCL_2ND (EMI_BASE_ADDR + 0x00D4)
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#define EMI_IOCM (EMI_BASE_ADDR + 0x00D8)
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#define EMI_IOCM_2ND (EMI_BASE_ADDR + 0x00DC)
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#define DISP_FAKE_ENG_RD_ADDR (MMSYS_BASE_ADDR + 0x210)
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#define DISP_FAKE_ENG_WR_ADDR (MMSYS_BASE_ADDR + 0x214)
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#define DISP_FAKE_ENG_CON0 (MMSYS_BASE_ADDR + 0x208)
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#define DISP_FAKE_ENG_CON1 (MMSYS_BASE_ADDR + 0x20C)
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#define DISP_FAKE_ENG_EN (MMSYS_BASE_ADDR + 0x200)
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#define DISP_FAKE_ENG_STATE (MMSYS_BASE_ADDR + 0x218)
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#define DISP_FAKE_ENG2_RD_ADDR (MMSYS_BASE_ADDR + 0x230)
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#define DISP_FAKE_ENG2_WR_ADDR (MMSYS_BASE_ADDR + 0x234)
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#define DISP_FAKE_ENG2_CON0 (MMSYS_BASE_ADDR + 0x228)
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#define DISP_FAKE_ENG2_CON1 (MMSYS_BASE_ADDR + 0x22C)
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#define DISP_FAKE_ENG2_EN (MMSYS_BASE_ADDR + 0x220)
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#define DISP_FAKE_ENG2_STATE (MMSYS_BASE_ADDR + 0x238)
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#define MMSYS_CG_CLR0 (MMSYS_BASE_ADDR + 0x108)
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#define MMSYS_CG_CLR1 (MMSYS_BASE_ADDR + 0x118)
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#define MMSYS_CG_CLR2 (MMSYS_BASE_ADDR + 0x148)
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#define MMSYS_CG_CON0 (MMSYS_BASE_ADDR + 0x100)
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#define MMSYS_CG_CON1 (MMSYS_BASE_ADDR + 0x110)
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#define SMI0_MON_ENA (SMI_COMMON_BASE + 0x1A0)
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#define SMI0_MON_CLR (SMI_COMMON_BASE + 0x1A4)
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#define SMI0_BUS_SEL (SMI_COMMON_BASE + 0x220)
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#define SMI_LARB0_MON_EN (SMI_LARB0_BASE + 0x400)
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#define SMI_LARB0_MON_CLR (SMI_LARB0_BASE + 0x404)
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#define SMI_LARB0_OSTDL_PORT (SMI_LARB0_BASE + 0x200)
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#define SMI_LARB1_MON_EN (SMI_LARB1_BASE + 0x400)
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#define SMI_LARB1_MON_CLR (SMI_LARB1_BASE + 0x404)
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#define SMI_LARB1_OSTDL_PORT (SMI_LARB1_BASE + 0x200)
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#endif /* LOW_POWER_CORRELATION */
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#define DRAMC_CONF1 (0x004)
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#define DRAMC_LPDDR2 (0x1e0)
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#define DRAMC_PADCTL4 (0x0e4)
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#define DRAMC_ACTIM1 (0x1e8)
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#define DRAMC_DQSCAL0 (0x1c0)
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#define DRAMC_READ(offset) ( \
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readl(IOMEM(DRAMC0_BASE + (offset)))| \
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readl(IOMEM(DDRPHY_BASE + (offset)))| \
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readl(IOMEM(DRAMC_NAO_BASE + (offset))))
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#define DRAMC_WRITE(offset, data) do { \
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writel((unsigned int) (data), \
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(DRAMC0_BASE + (offset))); \
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writel((unsigned int) (data), \
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(DDRPHY_BASE + (offset))); \
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mt65xx_reg_sync_writel((unsigned int) (data), \
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(DRAMC_NAO_BASE + (offset))); \
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} while (0)
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/*
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* Define constants.
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*/
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/* define supported DRAM types */
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enum {
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LPDDR2_1066 = 0,
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LPDDR4_3200,
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mDDR,
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};
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/* define concurrency scenario ID */
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enum {
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#define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe, \
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arbf, arbg, arbh) con_sce,
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#include "con_sce_lpddr4_3200.h"
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#undef X_CON_SCE
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NR_CON_SCE
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};
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/* define control operation */
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enum {
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ENABLE_CON_SCE = 0,
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DISABLE_CON_SCE = 1
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};
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#define EN_CON_SCE_STR "ON"
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#define DIS_CON_SCE_STR "OFF"
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/*
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* Define data structures.
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*/
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/* define control table entry */
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struct emi_bwl_ctrl {
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unsigned int ref_cnt;
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};
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/*
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* Define function prototype.
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*/
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extern int mtk_mem_bw_ctrl(int sce, int op);
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extern int get_ddr_type(void);
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extern unsigned int ucDram_Register_Read(unsigned long u4reg_addr);
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extern void __iomem *EMI_BASE_ADDR;
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#endif /* !__MT_EMI_BWL_H__ */
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