415 lines
13 KiB
C
415 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MTK_SECURE_API_H_
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#define _MTK_SECURE_API_H_
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#include <linux/kernel.h>
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#include <linux/arm-smccc.h>
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/* Error Code */
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#define SIP_SVC_E_SUCCESS 0
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#define SIP_SVC_E_NOT_SUPPORTED -1
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#define SIP_SVC_E_INVALID_PARAMS -2
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#define SIP_SVC_E_INVALID_Range -3
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#define SIP_SVC_E_PERMISSION_DENY -4
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#ifdef CONFIG_ARM64
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#define MTK_SIP_SMC_AARCH_BIT 0x40000000
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#else
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#define MTK_SIP_SMC_AARCH_BIT 0x00000000
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#endif
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/* 0x82000200 - 0x820003FF & 0xC2000300 - 0xC20003FF */
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/* Debug feature and ATF related */
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#define MTK_SIP_KERNEL_WDT \
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(0x82000200 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_GIC_DUMP \
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(0x82000201 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_TIME_SYNC \
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(0x82000202 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AEE_DUMP \
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(0x82000203 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_ATF_DEBUG \
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(0x82000204 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_DFD \
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(0x82000205 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_CCCI_GET_INFO \
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(0x82000206 | MTK_SIP_SMC_AARCH_BIT)
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/* v1.3 compatible */
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#define MTK_SIP_KERNEL_DISABLE_DFD \
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(0x8200020A | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_SCP_RESET \
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(0x8200020B | MTK_SIP_SMC_AARCH_BIT)
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/* CPU operations */
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#define MTK_SIP_POWER_DOWN_CLUSTER \
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(0x82000210 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_POWER_UP_CLUSTER \
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(0x82000211 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_POWER_DOWN_CORE \
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(0x82000212 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_POWER_UP_CORE \
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(0x82000213 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_POWER_FLOW_DEBUG \
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(0x82000214 | MTK_SIP_SMC_AARCH_BIT)
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/* Backward compatible */
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#define MTK_SIP_KERNEL_MSG \
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MTK_SIP_POWER_FLOW_DEBUG
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/* SPM related SMC call */
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#define MTK_SIP_KERNEL_SPM_SUSPEND_ARGS \
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(0x82000220 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_SPM_FIRMWARE_STATUS \
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(0x82000221 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_SPM_IRQ0_HANDLER \
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(0x82000222 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_SPM_AP_MDSRC_REQ \
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(0x82000223 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_SPM_PWR_CTRL_ARGS \
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(0x82000224 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_SPM_LEGACY_SLEEP \
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(0x82000225 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_SPM_VCOREFS_ARGS \
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(0x82000226 | MTK_SIP_SMC_AARCH_BIT)
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/* SPM deepidle related SMC call */
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#define MTK_SIP_KERNEL_SPM_DPIDLE_ARGS \
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(0x82000227 | MTK_SIP_SMC_AARCH_BIT)
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/* SPM SODI related SMC call */
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#define MTK_SIP_KERNEL_SPM_SODI_ARGS \
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(0x82000228 | MTK_SIP_SMC_AARCH_BIT)
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/* SPM sleep deepidle related SMC call */
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#define MTK_SIP_KERNEL_SPM_SLEEP_DPIDLE_ARGS \
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(0x82000229 | MTK_SIP_SMC_AARCH_BIT)
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/* SPM ARGS */
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#define MTK_SIP_KERNEL_SPM_ARGS \
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(0x8200022A | MTK_SIP_SMC_AARCH_BIT)
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/* SPM get pwr_ctrl args */
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#define MTK_SIP_KERNEL_SPM_GET_PWR_CTRL_ARGS \
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(0x8200022B | MTK_SIP_SMC_AARCH_BIT)
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/* SPM dummy read */
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#define MTK_SIP_KERNEL_SPM_DUMMY_READ \
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(0x8200022C | MTK_SIP_SMC_AARCH_BIT)
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/* SPM Check security CG (for deepidle/SODI) */
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#define MTK_SIP_KERNEL_CHECK_SECURE_CG \
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(0x8200022D | MTK_SIP_SMC_AARCH_BIT)
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/* SPM LP related SMC call */
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#define MTK_SIP_KERNEL_SPM_LP_ARGS \
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(0x8200022E | MTK_SIP_SMC_AARCH_BIT)
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/* SPM DCS S1 control */
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#define MTK_SIP_KERNEL_SPM_DCS_S1 \
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(0x8200022F | MTK_SIP_SMC_AARCH_BIT)
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/* Low power Misc. 1 SMC call,
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* 0x82000230 - 0x8200023F & 0xC2000230 - 0xC200023F
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*/
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/* DCM SMC call */
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#define MTK_SIP_KERNEL_DCM \
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(0x82000230 | MTK_SIP_SMC_AARCH_BIT)
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/* MCDI related SMC call */
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#define MTK_SIP_KERNEL_MCDI_ARGS \
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(0x82000231 | MTK_SIP_SMC_AARCH_BIT)
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/* SCP DVFS related SMC call */
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#define MTK_SIP_KERNEL_SCP_DVFS_CTRL \
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(0x82000232 | MTK_SIP_SMC_AARCH_BIT)
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/* v1.3 compatible */
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#define MTK_SIP_KERNEL_MCUPM_FW_LOAD_STATUS \
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(0x82000234 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_PMU_EVA \
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(0x82000235 | MTK_SIP_SMC_AARCH_BIT)
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/* AMMS related SMC call */
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#define MTK_SIP_KERNEL_AMMS_GET_FREE_ADDR \
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(0x82000250 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AMMS_GET_FREE_LENGTH \
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(0x82000251 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AMMS_GET_PENDING \
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(0x82000252 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AMMS_ACK_PENDING \
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(0x82000253 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AMMS_MD_POS_ADDR \
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(0x82000254 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AMMS_MD_POS_LENGTH \
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(0x82000255 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AMMS_GET_MD_POS_ADDR \
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(0x82000256 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AMMS_GET_MD_POS_LENGTH \
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(0x82000257 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AMMS_GET_SEQ_ID \
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(0x82000258 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_AMMS_POS_STRESS_TOUCH\
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(0x82000259 | MTK_SIP_SMC_AARCH_BIT)
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/* Security related SMC call */
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/* EMI MPU */
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#define MTK_SIP_KERNEL_EMIMPU_WRITE (0x82000260 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_EMIMPU_READ (0x82000261 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_EMIMPU_SET \
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(0x82000262 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_EMIMPU_CLEAR \
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(0x82000263 | MTK_SIP_SMC_AARCH_BIT)
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/* DEVMPU */
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#define MTK_SIP_KERNEL_DEVMPU_VIO_GET \
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(0x82000264 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_DEVMPU_PERM_GET \
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(0x82000265 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_DEVMPU_VIO_CLR \
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(0x82000268 | MTK_SIP_SMC_AARCH_BIT)
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/* TRNG */
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#define MTK_SIP_KERNEL_GET_RND \
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(0x8200026A | MTK_SIP_SMC_AARCH_BIT)
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/* DEVAPC/SRAMROM */
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#define MTK_SIP_KERNEL_DAPC_PERM_GET \
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(0x8200026B | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_CLR_SRAMROM_VIO \
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(0x8200026C | MTK_SIP_SMC_AARCH_BIT)
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/* v1.4 compatible */
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#define MTK_SIP_KERNEL_DAPC_DUMP \
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(0x8200026D | MTK_SIP_SMC_AARCH_BIT)
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/* v1.3 compatible */
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#define MTK_SIP_KERNEL_DAPC_INIT \
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(0x8200026E | MTK_SIP_SMC_AARCH_BIT)
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/* Storage Encryption related SMC call */
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/* HW FDE related SMC call */
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#define MTK_SIP_KERNEL_HW_FDE_UFS_CTL \
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(0x82000270 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_HW_FDE_AES_INIT \
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(0x82000271 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_HW_FDE_KEY \
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(0x82000272 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_HW_FDE_MSDC_CTL \
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(0x82000273 | MTK_SIP_SMC_AARCH_BIT)
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/* HIE related SMC call */
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#define MTK_SIP_KERNEL_CRYPTO_HIE_CFG_REQUEST \
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(0x82000274 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_CRYPTO_HIE_INIT \
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(0x82000275 | MTK_SIP_SMC_AARCH_BIT)
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/* UFS generic SMC call */
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#define MTK_SIP_KERNEL_UFS_CTL \
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(0x82000276 | MTK_SIP_SMC_AARCH_BIT)
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/* v1.3 compatible */
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/* LPDMA SMC calls */
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#define MTK_SIP_KERNEL_LPDMA_WRITE \
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(0x82000277 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_LPDMA_READ \
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(0x82000278 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_LPDMA_GET \
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(0x82000279 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_DRAM_DCS_CHB \
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(0x8200027A | MTK_SIP_SMC_AARCH_BIT)
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/* Platform related SMC call */
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#define MTK_SIP_KERNEL_CACHE_FLUSH_FIQ \
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(0x82000280 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_CACHE_FLUSH_INIT \
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(0x82000281 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_CACHE_FLUSH_BY_SF \
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(0x82000283 | MTK_SIP_SMC_AARCH_BIT)
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/* v1.3 compatible */
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#define MTK_SIP_KERNEL_L2_SHARING \
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(0x82000286 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_MCUSYS_WRITE \
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(0x82000287 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_MCUSYS_ACCESS_COUNT \
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(0x82000288 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_MCSI_A_WRITE \
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(0x82000289 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_MCSI_A_READ \
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(0x8200028A | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_KERNEL_MCSI_NS_ACCESS \
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(0x8200028B | MTK_SIP_SMC_AARCH_BIT)
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/* Pheripheral related SMC call */
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#define MTK_SIP_KERNEL_I2C_SEC_WRITE \
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(0x820002A0 | MTK_SIP_SMC_AARCH_BIT)
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/* v1.4 Compatible */
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/* M4U related SMC call */
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#define MTK_M4U_DEBUG_DUMP \
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(0x820002B0 | MTK_SIP_SMC_AARCH_BIT)
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/* APU related SMC call */
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#define MTK_APU_VCORE_CG_CTL \
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(0x820002B1 | MTK_SIP_SMC_AARCH_BIT)
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/* GIC related SMC call */
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#define MTK_SIP_GIC_CONTROL \
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(0x82000501 | MTK_SIP_SMC_AARCH_BIT)
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/* Debug related SMC call */
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#define MTK_SIP_CCCI_CONTROL \
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(0x82000505 | MTK_SIP_SMC_AARCH_BIT)
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/* MTK LPM */
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#define MTK_SIP_MTK_LPM_CONTROL \
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(0x82000507 | MTK_SIP_SMC_AARCH_BIT)
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/* TEEs related SMC call */
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#define MTK_SIP_KERNEL_TEE_CONTROL \
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(0x82000516 | MTK_SIP_SMC_AARCH_BIT)
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/* AUDIO related SMC call */
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#define MTK_SIP_AUDIO_CONTROL \
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(0x82000517 | MTK_SIP_SMC_AARCH_BIT)
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/* cmdq related SMC call */
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#define MTK_SIP_CMDQ_CONTROL \
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(0x82000518 | MTK_SIP_SMC_AARCH_BIT)
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/* APUSYS MNoC related SMC call */
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#define MTK_SIP_APUSYS_MNOC_CONTROL \
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(0x82000519 | MTK_SIP_SMC_AARCH_BIT)
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#define MTK_SIP_MMSRAM_CONTROL \
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(0x8200051D | MTK_SIP_SMC_AARCH_BIT)
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/* APUSYS control related SMC call */
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#define MTK_SIP_APUSYS_CONTROL \
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(0x8200051E | MTK_SIP_SMC_AARCH_BIT)
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/* CACHE control related SMC call */
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#define MTK_SIP_CACHE_CONTROL \
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(0x8200051F | MTK_SIP_SMC_AARCH_BIT)
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/* TMEM */
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#define MTK_SIP_TMEM_CONTROL \
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(0x82000524 | MTK_SIP_SMC_AARCH_BIT)
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/* APUPWR control related SMC call */
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#define MTK_SIP_APUPWR_CONTROL \
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(0x82000526 | MTK_SIP_SMC_AARCH_BIT)
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#define mtk_idle_smc_impl(p1, p2, p3, p4, p5, res) \
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arm_smccc_smc(p1, p2, p3, p4,\
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p5, 0, 0, 0, &res)
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#ifndef mt_secure_call
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#define mt_secure_call(x1, x2, x3, x4, x5) ({\
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struct arm_smccc_res res;\
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mtk_idle_smc_impl(x1, x2, x3, x4, x5, res);\
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res.a0; })
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#endif
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#define mt_secure_call_ret1(_fun_id, _arg0, _arg1, _arg2, _arg3) \
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mt_secure_call_all(_fun_id, _arg0, _arg1, _arg2, _arg3, 0, 0, 0)
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#define mt_secure_call_ret2(_fun_id, _arg0, _arg1, _arg2, _arg3, _r1) \
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mt_secure_call_all(_fun_id, _arg0, _arg1, _arg2, _arg3, _r1, 0, 0)
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#define mt_secure_call_ret3(_fun_id, _arg0, _arg1, _arg2, _arg3, _r1, _r2) \
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mt_secure_call_all(_fun_id, _arg0, _arg1, _arg2, _arg3, _r1, _r2, 0)
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#define mt_secure_call_ret4(_fun_id, _arg0,\
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_arg1, _arg2, _arg3, _r1, _r2, _r3) \
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mt_secure_call_all(_fun_id, _arg0, _arg1, _arg2, _arg3, _r1, _r2, _r3)
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#define emi_mpu_smc_write(offset, val) \
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mt_secure_call(MTK_SIP_KERNEL_EMIMPU_WRITE, offset, val, 0, 0)
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#define emi_mpu_smc_read(offset) \
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mt_secure_call(MTK_SIP_KERNEL_EMIMPU_READ, offset, 0, 0, 0)
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#ifdef CONFIG_ARM64
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#define emi_mpu_smc_set(start, end, region_permission) \
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mt_secure_call(MTK_SIP_KERNEL_EMIMPU_SET, start, end, region_permission, 0)
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#else
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#define emi_mpu_smc_set(start, end, apc8, apc0) \
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mt_secure_call_all(MTK_SIP_KERNEL_EMIMPU_SET,\
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start, end, apc8, apc0, 0, 0, 0)
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#endif
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#define emi_mpu_smc_clear(region) \
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mt_secure_call(MTK_SIP_KERNEL_EMIMPU_CLEAR, region, 0, 0, 0)
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#define emi_mpu_smc_protect(start, end, apc) \
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mt_secure_call(MTK_SIP_KERNEL_EMIMPU_SET, start, end, apc, 0)
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/* v1.3 API Compatible */
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#define dram_smc_dcs(OnOff) \
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mt_secure_call(MTK_SIP_KERNEL_DRAM_DCS_CHB, OnOff, 0, 0, 0)
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#define lpdma_smc_write(offset, val) \
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mt_secure_call(MTK_SIP_KERNEL_LPDMA_WRITE, offset, val, 0, 0)
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#define lpdma_smc_read(offset) \
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mt_secure_call(MTK_SIP_KERNEL_LPDMA_READ, offset, 0, 0, 0)
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#define lpdma_smc_get_mode() \
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mt_secure_call(MTK_SIP_KERNEL_LPDMA_GET, 0, 0, 0, 0)
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#define mcsi_a_smc_read_phy(addr) \
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mt_secure_call(MTK_SIP_KERNEL_MCSI_A_READ, addr, 0, 0, 0)
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#define mcsi_a_smc_write_phy(addr, val) \
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mt_secure_call(MTK_SIP_KERNEL_MCSI_A_WRITE, addr, val, 0, 0)
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#define dcm_smc_msg(init_type) \
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mt_secure_call(MTK_SIP_KERNEL_DCM, init_type, 0, 0, 0)
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#define dcm_smc_read_cnt(type) \
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mt_secure_call(MTK_SIP_KERNEL_DCM, type, 1, 0, 0)
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#define CONFIG_MCUSYS_WRITE_PROTECT
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#if defined(CONFIG_MCUSYS_WRITE_PROTECT) && \
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(defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI))
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#define kernel_smc_msg(x1, x2, x3) \
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mt_secure_call(MTK_SIP_KERNEL_MSG, x1, x2, x3, 0)
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#ifndef mcsi_reg_read
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#define mcsi_reg_read(offset) \
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mt_secure_call(MTK_SIP_KERNEL_MCSI_NS_ACCESS, 0, offset, 0, 0)
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#define mcsi_reg_write(val, offset) \
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mt_secure_call(MTK_SIP_KERNEL_MCSI_NS_ACCESS, 1, offset, val, 0)
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#endif
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#define mcsi_reg_set_bitmask(val, offset) \
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mt_secure_call(MTK_SIP_KERNEL_MCSI_NS_ACCESS, 2, offset, val, 0)
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#define mcsi_reg_clear_bitmask(val, offset) \
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mt_secure_call(MTK_SIP_KERNEL_MCSI_NS_ACCESS, 3, offset, val, 0)
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#ifdef CONFIG_ARM64 /* Kernel 64 */
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#define mcusys_smc_write(virt_addr, val) \
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mt_reg_sync_writel(val, virt_addr)
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#define mcusys_smc_write_phy(addr, val) \
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mt_secure_call(MTK_SIP_KERNEL_MCUSYS_WRITE, addr, val, 0, 0)
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#define mcusys_access_count() \
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mt_secure_call(MTK_SIP_KERNEL_MCUSYS_ACCESS_COUNT, 0, 0, 0, 0)
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#else /* Kernel 32 */
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#define SMC_IO_VIRT_TO_PHY(addr) (addr-0xF0000000+0x10000000)
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#define mcusys_smc_write(virt_addr, val) \
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mt_secure_call(MTK_SIP_KERNEL_MCUSYS_WRITE, \
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SMC_IO_VIRT_TO_PHY(virt_addr), val, 0, 0)
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#define mcusys_smc_write_phy(addr, val) \
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mt_secure_call(MTK_SIP_KERNEL_MCUSYS_WRITE, addr, val, 0, 0)
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#define mcusys_access_count() \
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mt_secure_call(MTK_SIP_KERNEL_MCUSYS_ACCESS_COUNT, 0, 0, 0, 0)
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#endif
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#else
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#define mcusys_smc_write(virt_addr, val) \
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mt_reg_sync_writel(val, virt_addr)
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#define mcusys_access_count() (0)
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#define kernel_smc_msg(x1, x2, x3)
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#endif
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#endif /* _MTK_SECURE_API_H_ */
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