184 lines
8.4 KiB
C
184 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __JPEG_DRV_REG_H__
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#define __JPEG_DRV_REG_H__
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/* #include <mach/mt_reg_base.h> */
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/* #include <mach/sync_write.h> */
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#include <mt-plat/sync_write.h>
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#include <linux/io.h>
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#include "jpeg_drv.h"
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#define JPEG_ENC_BASE jpeg_dev_get_encoder_base_VA()
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#define JPEG_DEC_BASE jpeg_dev_get_decoder_base_VA()
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#define JPEG_HYBRID_DEC_BASE(i) jpeg_dev_get_hybrid_decoder_base_VA(i)
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#define IMG_REG_WRITE(v, a) writel(v, (void __iomem *)a)
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#define IMG_REG_READ(a) readl((void __iomem *)a)
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#define JPEG_ENC_REG_COUNT 0x31C
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/********************************************************************/
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/* define JPEG Encoder Registers register field*/
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/********************************************************************/
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#define JPEG_DRV_ENC_INT_STATUS_DONE 0x01
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#define JPEG_DRV_ENC_INT_STATUS_STALL 0x02
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#define JPEG_DRV_ENC_INT_STATUS_VCODEC_IRQ 0x10
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#define JPEG_DRV_ENC_INT_STATUS_MASK_ALLIRQ 0x13
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#define JPEG_DRV_DEC_INT_STATUS_DEC_ERR 0x04
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/********************************************************************/
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/* The following registers are for JPEG Encoder Registers on MT6589 */
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/********************************************************************/
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#define REG_ADDR_JPEG_ENC_RSTB (JPEG_ENC_BASE + 0x100)
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#define REG_ADDR_JPEG_ENC_CTRL (JPEG_ENC_BASE + 0x104)
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#define REG_ADDR_JPEG_ENC_QUALITY (JPEG_ENC_BASE + 0x108)
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#define REG_ADDR_JPEG_ENC_BLK_NUM (JPEG_ENC_BASE + 0x10C)
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#define REG_ADDR_JPEG_ENC_BLK_CNT (JPEG_ENC_BASE + 0x110)
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#define REG_ADDR_JPEG_ENC_INTERRUPT_STATUS (JPEG_ENC_BASE + 0x11C)
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#define REG_ADDR_JPEG_ENC_DST_ADDR0 (JPEG_ENC_BASE + 0x120)
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#define REG_ADDR_JPEG_ENC_DMA_ADDR0 (JPEG_ENC_BASE + 0x124)
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#define REG_ADDR_JPEG_ENC_STALL_ADDR0 (JPEG_ENC_BASE + 0x128)
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#define REG_ADDR_JPEG_ENC_OFFSET_ADDR (JPEG_ENC_BASE + 0x138)
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#define REG_ADDR_JPEG_ENC_CURR_DMA_ADDR (JPEG_ENC_BASE + 0x13C)
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#define REG_ADDR_JPEG_ENC_RST_MCU_NUM (JPEG_ENC_BASE + 0x150)
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#define REG_ADDR_JPEG_ENC_IMG_SIZE (JPEG_ENC_BASE + 0x154)
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#define REG_ADDR_JPEG_ENC_GULTRA_TRESH (JPEG_ENC_BASE + 0x158)
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#define REG_ADDR_JPEG_ENC_DEBUG_INFO0 (JPEG_ENC_BASE + 0x160)
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#define REG_ADDR_JPEG_ENC_DEBUG_INFO1 (JPEG_ENC_BASE + 0x164)
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#define REG_ADDR_JPEG_ENC_TOTAL_CYCLE (JPEG_ENC_BASE + 0x168)
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#define REG_ADDR_JPEG_ENC_BYTE_OFFSET_MASK (JPEG_ENC_BASE + 0x16C)
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#define REG_ADDR_JPEG_ENC_SRC_LUMA_ADDR (JPEG_ENC_BASE + 0x170)
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#define REG_ADDR_JPEG_ENC_SRC_CHROMA_ADDR (JPEG_ENC_BASE + 0x174)
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#define REG_ADDR_JPEG_ENC_STRIDE (JPEG_ENC_BASE + 0x178)
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#define REG_ADDR_JPEG_ENC_IMG_STRIDE (JPEG_ENC_BASE + 0x17C)
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#define REG_ADDR_JPEG_ENC_MEM_CYCLE (JPEG_ENC_BASE + 0x208)
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#define REG_ADDR_JPEG_ENC_SMI_DEBUG0 (JPEG_ENC_BASE + 0x304)
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#define REG_ADDR_JPEG_ENC_SMI_DEBUG1 (JPEG_ENC_BASE + 0x308)
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#define REG_ADDR_JPEG_ENC_SMI_DEBUG2 (JPEG_ENC_BASE + 0x30C)
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#define REG_ADDR_JPEG_ENC_SMI_DEBUG3 (JPEG_ENC_BASE + 0x310)
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#define REG_ADDR_JPEG_ENC_CODEC_SEL (JPEG_ENC_BASE + 0x314)
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#define REG_ADDR_JPEG_ENC_ULTRA_THRES (JPEG_ENC_BASE + 0x318)
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#define REG_ADDR_JPEG_ENC_PASS2_RSTB (JPEG_ENC_BASE + 0x800)
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/********************************************************************/
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/* define JPEG Decoder Registers register field*/
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/********************************************************************/
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/* REG_JPGDEC_RESET ( JPEG_DEC_BASE + 0x0090 ) */
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#define BIT_SOFT_RST_SHIFT 0
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#define BIT_HARD_RST_SHIFT 4
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/* REG_JPGDEC_BRZ_FACTOR ( JPEG_DEC_BASE + 0x00F8 ) */
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#define BIT_BRZ_YH_SHIFT 0
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#define BIT_BRZ_YV_SHIFT 4
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#define BIT_BRZ_CH_SHIFT 8
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#define BIT_BRZ_CV_SHIFT 12
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/* REG_JPGDEC_DU_SAMPLE ( JPEG_DEC_BASE + 0x00FC ) */
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/* REG_JPGDEC_DEST_ADDR0_Y ( JPEG_DEC_BASE + 0x0140 ) */
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/* REG_JPGDEC_DEST_ADDR0_U ( JPEG_DEC_BASE + 0x0144 ) */
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/* REG_JPGDEC_DEST_ADDR0_V ( JPEG_DEC_BASE + 0x0148 ) */
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/* REG_JPGDEC_DEST_ADDR1_Y ( JPEG_DEC_BASE + 0x014C ) */
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/* REG_JPGDEC_DEST_ADDR1_U ( JPEG_DEC_BASE + 0x0150 ) */
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/* REG_JPGDEC_DEST_ADDR1_V ( JPEG_DEC_BASE + 0x0154 ) */
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/* REG_JPGDEC_STRIDE_Y ( JPEG_DEC_BASE + 0x0158 ) */
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/* REG_JPGDEC_STRIDE_UV ( JPEG_DEC_BASE + 0x015C ) */
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/* REG_JPGDEC_IMG_STRIDE_Y ( JPEG_DEC_BASE + 0x0160 ) */
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/* REG_JPGDEC_IMG_STRIDE_UV ( JPEG_DEC_BASE + 0x0164 ) */
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/* REG_JPGDEC_WDMA_CTRL ( JPEG_DEC_BASE + 0x016C ) */
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/* REG_JPGDEC_PAUSE_MCU_NUM ( JPEG_DEC_BASE + 0x0170 ) */
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/* REG_JPGDEC_OPERATION_MODE ( JPEG_DEC_BASE + 0x017C ) */
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/* REG_JPGDEC_DEBUG0 ( JPEG_DEC_BASE + 0x0180 ) */
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/* REG_JPGDEC_FILE_ADDR ( JPEG_DEC_BASE + 0x0200 ) */
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/* REG_JPGDEC_COMP_ID ( JPEG_DEC_BASE + 0x020C ) */
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/* REG_JPGDEC_TOTAL_MCU_NUM ( JPEG_DEC_BASE + 0x0210 ) */
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/* REG_JPGDEC_COMP0_DATA_UNIT_NUM ( JPEG_DEC_BASE + 0x0224 ) */
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/* REG_JPGDEC_DU_CTRL ( JPEG_DEC_BASE + 0x023C ) */
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#define BIT_DU_CTRL_COMP_Y 4
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#define BIT_DU_CTRL_COMP_U 5
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#define BIT_DU_CTRL_COMP_V 6
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#define BIT_DU_CTRL_NOUSE 7
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/* REG_JPGDEC_TRIG ( JPEG_DEC_BASE + 0x0240 ) */
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/* REG_JPGDEC_FILE_BRP ( JPEG_DEC_BASE + 0x0248 ) */
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/* REG_JPGDEC_FILE_TOTAL_SIZE ( JPEG_DEC_BASE + 0x024C ) */
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/* REG_JPGDEC_QT_ID ( JPEG_DEC_BASE + 0x0270 ) */
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/* REG_JPGDEC_INTERRUPT_STATUS ( JPEG_DEC_BASE + 0x0274 ) */
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#define BIT_INQST_MASK_TYPE 0x80000000
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#define BIT_INQST_MASK_ERROR_BS 0x20
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#define BIT_INQST_MASK_PAUSE 0x10
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#define BIT_INQST_MASK_OVERFLOW 0x04
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#define BIT_INQST_MASK_UNDERFLOW 0x02
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#define BIT_INQST_MASK_EOF 0x01
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#define BIT_INQST_MASK_END 0x27
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#define BIT_INQST_MASK_ALLIRQ 0x37
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#define BIT_DEC_IRQ_EN_DEBUG_BRP_FLAG 0x80
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/* REG_JPGDEC_STATUS ( JPEG_DEC_BASE + 0x0278 ) */
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#define BIT_DEC_ST_STATE_MASK 0x07000000
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#define BIT_DEC_ST_STATE_IDLE 0x00000000
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#define BIT_DEC_ST_STATE_DMA 0x01000000
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#define BIT_DEC_ST_STATE_HEADER 0x02000000
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#define BIT_DEC_ST_STATE_VLD 0x03000000
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#define BIT_DEC_ST_STATE_RST 0x04000000
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#define BIT_DEC_ST_STATE_PROG 0x05000000
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#define BIT_DEC_ST_STATE_IDCT 0x06000000
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#define REG_JPGDEC_HYBRID_090(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0090)
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#define REG_JPGDEC_HYBRID_0FC(X) (JPEG_HYBRID_DEC_BASE(X) + 0x00FC)
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#define REG_JPGDEC_HYBRID_14C(X) (JPEG_HYBRID_DEC_BASE(X) + 0x014C)
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#define REG_JPGDEC_HYBRID_150(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0150)
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#define REG_JPGDEC_HYBRID_154(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0154)
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#define REG_JPGDEC_HYBRID_17C(X) (JPEG_HYBRID_DEC_BASE(X) + 0x017C)
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#define REG_JPGDEC_HYBRID_200(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0200)
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#define REG_JPGDEC_HYBRID_20C(X) (JPEG_HYBRID_DEC_BASE(X) + 0x020C)
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#define REG_JPGDEC_HYBRID_210(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0210)
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#define REG_JPGDEC_HYBRID_224(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0224)
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#define REG_JPGDEC_HYBRID_23C(X) (JPEG_HYBRID_DEC_BASE(X) + 0x023C)
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#define REG_JPGDEC_HYBRID_240(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0240)
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#define REG_JPGDEC_HYBRID_24C(X) (JPEG_HYBRID_DEC_BASE(X) + 0x024C)
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#define REG_JPGDEC_HYBRID_270(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0270)
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#define REG_JPGDEC_HYBRID_274(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0274)
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#define REG_JPGDEC_HYBRID_31C(X) (JPEG_HYBRID_DEC_BASE(X) + 0x031C)
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#define REG_JPGDEC_HYBRID_330(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0330)
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#define REG_JPGDEC_HYBRID_334(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0334)
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#define REG_JPGDEC_HYBRID_338(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0338)
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#define REG_JPGDEC_HYBRID_33C(X) (JPEG_HYBRID_DEC_BASE(X) + 0x033C)
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#define REG_JPGDEC_HYBRID_340(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0340)
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#define REG_JPGDEC_HYBRID_344(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0344)
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#define REG_JPGDEC_HYBRID_348(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0348)
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#define REG_JPGDEC_HYBRID_36C(X) (JPEG_HYBRID_DEC_BASE(X) + 0x036C)
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#define REG_JPGDEC_HYBRID_370(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0370)
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#define REG_JPGDEC_HYBRID_374(X) (JPEG_HYBRID_DEC_BASE(X) + 0x0374)
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#endif /* / __MT6589_JPEG_REG_H__ */
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