52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT6877_COND_H__
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#define __MT6877_COND_H__
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/* Definition about SPM_COND_CHECK_BLOCKED
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* bit [00 ~ 15]: cg blocking index
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* bit [16 ~ 29]: pll blocking index
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* bit [30] : pll blocking information
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* bit [31] : idle condition check fail
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*/
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#define SPM_COND_BLOCKED_CG_IDX (0)
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#define SPM_COND_BLOCKED_PLL_IDX (16)
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#define SPM_COND_BLOCKED_PLL (1<<30L)
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#define SPM_COND_CHECK_FAIL (1<<31L)
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enum PLAT_SPM_COND {
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PLAT_SPM_COND_MTCMOS_1 = 0,
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PLAT_SPM_COND_MTCMOS_2,
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PLAT_SPM_COND_CG_INFRA_0,
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PLAT_SPM_COND_CG_INFRA_1,
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PLAT_SPM_COND_CG_INFRA_2,
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PLAT_SPM_COND_CG_INFRA_3,
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PLAT_SPM_COND_CG_INFRA_4,
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PLAT_SPM_COND_CG_INFRA_5,
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PLAT_SPM_COND_CG_MMSYS_0,
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PLAT_SPM_COND_CG_MMSYS_1,
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PLAT_SPM_COND_CG_MMSYS_2,
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PLAT_SPM_COND_CG_MMSYS_3,
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PLAT_SPM_COND_CG_MMSYS_4,
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PLAT_SPM_COND_CG_MMSYS_5,
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PLAT_SPM_COND_CG_MMSYS_6,
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PLAT_SPM_COND_CG_MMSYS_7,
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PLAT_SPM_COND_MAX,
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};
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enum PLAT_SPM_PLL_COND {
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PLAT_SPM_COND_UNIVPLL = 0,
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PLAT_SPM_COND_PLL_MFGPLL1,
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PLAT_SPM_COND_PLL_MFGPLL4,
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PLAT_SPM_COND_MSDCPLL,
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PLAT_SPM_COND_TVPLL,
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PLAT_SPM_COND_MMPLL,
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PLAT_SPM_COND_PLL_MAX,
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};
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#endif
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