128 lines
3.8 KiB
C
128 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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*/
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#ifndef _MDLA_HW_REG_H_
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#define _MDLA_HW_REG_H_
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#define APU2_IRQ_ID (321+32)
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#define MDLA_IRQ_SWCMD_TILECNT_INT (1 << 1)
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#define MDLA_IRQ_TILECNT_DONE (1 << 1)
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#define MDLA_IRQ_SWCMD_DONE (1 << 2)
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#define MDLA_IRQ_PMU_INTE (1 << 9)
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#define MDLA_IRQ_MASK (0x1FFFFF)
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#define MDLA_AXI_CTRL_MASK ((1 << 7) | (1 << 16))
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/* Infra TOPAXI */
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#define INFRA_TOPAXI_PROTECTEN_MCU_SET (0x2C4)
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#define INFRA_TOPAXI_PROTECTEN_MCU_CLR (0x2C8)
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#define INFRA_TOPAXI_PROTECTEN_MCU_STA0 (0x2E0)
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#define INFRA_TOPAXI_PROTECTEN_MCU_STA1 (0x2E4)
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#define VPU_CORE2_PROT_STEP1_0_MASK \
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((0x1 << 8) | (0x1 << 9) | (0x1 << 10))
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#define VPU_CORE2_PROT_STEP1_0_ACK_MASK \
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((0x1 << 8) | (0x1 << 9) | (0x1 << 10))
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/* APU CONN */
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#define APU_CONN_SW_RST (0x00C)
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#define APU_CORE2_RSTB (1 << 15)
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/* MDLA config */
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#define MDLA_CG_CON (0x000)
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#define MDLA_CG_SET (0x004)
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#define MDLA_CG_CLR (0x008)
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#define MDLA_SW_RST (0x00C)
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#define MDLA_MBIST_MODE0 (0x010)
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#define MDLA_MBIST_MODE1 (0x014)
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#define MDLA_MBIST_CTL (0x018)
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#define MDLA_RP_OK0 (0x01C)
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#define MDLA_RP_OK1 (0x020)
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#define MDLA_RP_OK2 (0x024)
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#define MDLA_RP_OK3 (0x028)
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#define MDLA_RP_FAIL0 (0x02C)
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#define MDLA_RP_FAIL1 (0x030)
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#define MDLA_RP_FAIL2 (0x034)
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#define MDLA_RP_FAIL3 (0x038)
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#define MDLA_MBIST_FAIL0 (0x03C)
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#define MDLA_MBIST_FAIL1 (0x040)
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#define MDLA_MBIST_FAIL2 (0x044)
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#define MDLA_MBIST_FAIL3 (0x048)
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#define MDLA_MBIST_FAIL4 (0x04C)
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#define MDLA_MBIST_FAIL5 (0x050)
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#define MDLA_MBIST_DONE0 (0x054)
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#define MDLA_MBIST_DONE1 (0x058)
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#define MDLA_MBIST_DEFAULT_DELSEL (0x05C)
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#define MDLA_SRAM_DELSEL0 (0x060)
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#define MDLA_SRAM_DELSEL1 (0x064)
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#define MDLA_RP_RST (0x068)
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#define MDLA_RP_CON (0x06C)
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#define MDLA_RP_PRE_FUSE (0x070)
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#define MDLA_SPARE_0 (0x074)
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#define MDLA_SPARE_1 (0x078)
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#define MDLA_SPARE_2 (0x07C)
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#define MDLA_SPARE_3 (0x080)
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#define MDLA_SPARE_4 (0x084)
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#define MDLA_SPARE_5 (0x088)
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#define MDLA_SPARE_6 (0x08C)
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#define MDLA_SPARE_7 (0x090)
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#define MDLA_AXI_CTRL (0x120)
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#define MDLA_AXI1_CTRL (0x124)
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/* MDLA command */
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#define MREG_TOP_G_REV (0x0500)
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#define MREG_TOP_G_INTP0 (0x0504)
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#define MREG_TOP_G_INTP1 (0x0508)
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#define MREG_TOP_G_INTP2 (0x050C)
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#define MREG_TOP_G_CDMA0 (0x0510)
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#define MREG_TOP_G_CDMA1 (0x0514)
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#define MREG_TOP_G_CDMA2 (0x0518)
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#define MREG_TOP_G_CDMA3 (0x051C)
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#define MREG_TOP_G_CDMA4 (0x0520)
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#define MREG_TOP_G_CDMA5 (0x0524)
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#define MREG_TOP_G_CDMA6 (0x0528)
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#define MREG_TOP_G_CUR0 (0x052C)
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#define MREG_TOP_G_CUR1 (0x0530)
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#define MREG_TOP_G_FIN0 (0x0534)
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#define MREG_TOP_G_FIN1 (0x0538)
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#define MREG_TOP_G_STREAM0 (0x053C)
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#define MREG_TOP_G_STREAM1 (0x0540)
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#define MREG_TOP_G_IDLE (0x0544)
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#define MREG_TOP_ENG0 (0x0550)
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#define MREG_TOP_ENG1 (0x0554)
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#define MREG_TOP_ENG2 (0x0558)
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#define MREG_TOP_ENG11 (0x057C)
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#define MREG_CMD_SIZE (0x180)
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#define MREG_CMD_SWCMD_ID (0x150)
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#define MREG_CMD_EXE_FLOW (0x158)
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#define MREG_CMD_CBL_FUNC (0x0AC)
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#define MREG_CMD_SBL_FUNC (0x11C)
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#define MREG_CMD_CONV_FUNC (0x0BC)
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#define MREG_CMD_ELW_FUNC (0x0CC)
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#define MREG_CMD_ACTI_FUNC (0x0E0)
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#define MREG_CMD_POOL_FUNC_0 (0x0F8)
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#define MREG_CMD_STE_FUNC (0x118)
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/* MDLA PMU */
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#define CFG_PMCR_DEFAULT (0x1F021)
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#define PMU_CNT_SHIFT (0x0010)
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#define PMU_CLR_CMDE_SHIFT (0x5)
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#define PMU_PMCR_CCNT_EN (0x10000)
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#define PMU_PMCR_CCNT_RST (0x4)
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#define PMU_PMCR_CNT_RST (0x2)
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#define PMU_CFG_PMCR (0x0E00)
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#define PMU_CYCLE (0x0E04)
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#define PMU_START_TSTAMP (0x0E08)
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#define PMU_END_TSTAMP (0x0E0C)
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#define PMU_EVENT_OFFSET (0x0E10)
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#define PMU_CNT_OFFSET (0x0E14)
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#endif
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