45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef EARA_THRM_PB_H
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#define EARA_THRM_PB_H
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extern struct ppm_cobra_data *ppm_cobra_pass_tbl(void);
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extern void eara_pass_perf_first_hint(int enable);
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extern struct mt_gpufreq_power_table_info *pass_gpu_table_to_eara(void);
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extern unsigned int mt_gpufreq_get_dvfs_table_num(void);
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extern void (*eara_thrm_gblock_bypass_fp)(int pid,
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unsigned long long bufid, int bypass);
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extern void (*eara_thrm_frame_start_fp)(int pid, unsigned long long bufID,
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int cpu_time, int vpu_time, int mdla_time,
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int cpu_cap, int vpu_cap, int mdla_cap,
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int queuefps, unsigned long long q2q_time,
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int AI_cross_vpu, int AI_cross_mdla, int AI_bg_vpu,
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int AI_bg_mdla, ktime_t cur_time);
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extern void (*eara_thrm_enqueue_end_fp)(int pid, unsigned long long bufID,
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int gpu_time, int gpu_freq, unsigned long long enq);
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/* platform */
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struct thrm_pb_ratio {
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int ratio;
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int vpu_power;
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int mdla_power;
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};
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void eara_thrm_update_gpu_info(int *input_opp_num, int *in_max_opp_idx,
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struct mt_gpufreq_power_table_info **gpu_tbl,
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struct thrm_pb_ratio **opp_ratio);
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int eara_thrm_get_vpu_core_num(void);
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int eara_thrm_get_mdla_core_num(void);
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int eara_thrm_vpu_opp_to_freq(int opp);
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int eara_thrm_mdla_opp_to_freq(int opp);
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int eara_thrm_apu_ready(void);
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int eara_thrm_vpu_onoff(void);
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int eara_thrm_mdla_onoff(void);
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#endif
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