441 lines
14 KiB
C
441 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 MediaTek Inc.
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*/
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#include <linux/delay.h>
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#include <mt-plat/upmu_common.h>
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#include <mt-plat/mtk_chip.h>
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#include <mt-plat/mtk_rtc.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include "include/pmic.h"
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#include "include/pmic_api.h"
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#include "include/pmic_api_buck.h"
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#include "include/regulator_codegen.h"
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#define LP_INIT_SETTING_VERIFIED 1
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unsigned int g_pmic_chip_version = 1;
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int PMIC_MD_INIT_SETTING_V1(void)
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{
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/* No need for PMIC MT6357 */
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return 0;
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}
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int PMIC_check_wdt_status(void)
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{
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unsigned int ret = 0;
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is_wdt_reboot_pmic = pmic_get_register_value(PMIC_WDTRSTB_STATUS);
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ret = pmic_set_register_value(PMIC_TOP_RST_MISC_SET, 0x8);
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udelay(50);
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is_wdt_reboot_pmic_chk = pmic_get_register_value(PMIC_WDTRSTB_STATUS);
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ret = pmic_set_register_value(PMIC_TOP_RST_MISC_CLR, 0x8);
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ret = pmic_set_register_value(PMIC_TOP_RST_MISC_SET, 0x1);
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ret = pmic_get_register_value(PMIC_RG_WDTRSTB_EN);
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return ret;
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}
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int PMIC_check_pwrhold_status(void)
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{
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unsigned int val = 0;
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pmic_read_interface(PMIC_RG_PWRHOLD_ADDR, &val, PMIC_RG_PWRHOLD_MASK,
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PMIC_RG_PWRHOLD_SHIFT);
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return val;
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}
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int PMIC_check_battery(void)
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{
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unsigned int val = 0;
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/* ask shin-shyu programming guide */
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mt6357_upmu_set_rg_baton_en(1);
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/*PMIC_upmu_set_baton_tdet_en(1);*/
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val = mt6357_upmu_get_rgs_baton_undet();
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if (val == 0) {
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pr_debug("bat is exist.\n");
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is_battery_remove = 0;
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return 1;
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}
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pr_debug("bat NOT exist.\n");
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is_battery_remove = 1;
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return 0;
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}
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int PMIC_POWER_HOLD(unsigned int hold)
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{
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if (hold > 1) {
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pr_notice("[PMIC_KERNEL] %s hold = %d only 0 or 1\n",
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__func__, hold);
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return -1;
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}
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if (hold)
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PMICLOG("[PMIC_KERNEL] %s ON\n", __func__);
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else
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PMICLOG("[PMIC_KERNEL] %s OFF\n", __func__);
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/* MT6357 must keep power hold */
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pmic_config_interface_nolock(PMIC_RG_PWRHOLD_ADDR, hold
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, PMIC_RG_PWRHOLD_MASK
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, PMIC_RG_PWRHOLD_SHIFT);
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PMICLOG("[PMIC_KERNEL] MT6357 PowerHold = 0x%x\n"
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, upmu_get_reg_value(MT6357_PPCCTL0));
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return 0;
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}
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unsigned int PMIC_LP_CHIP_VER(void)
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{
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unsigned int ret = 0;
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unsigned short chip_ver = 0;
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#if defined(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES)
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/* PMIC special flavor project */
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if (strncmp(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES,
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"mediatek/evb6739_64_lp", 22) == 0 ||
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strncmp(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES,
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"mediatek/k39v1_64_lp", 20) == 0)
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return 2;
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#endif
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#if defined(CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE_NAMES)
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/* PMIC special flavor project */
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if (strncmp(CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE_NAMES,
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"evb6739_lp", 10) == 0 ||
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strncmp(CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE_NAMES,
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"k39v1_lp", 8) == 0)
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return 2;
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#endif
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chip_ver = pmic_get_register_value(PMIC_SWCID);
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ret = ((chip_ver & 0x00F0) >> 4);
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return ret;
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}
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unsigned int PMIC_CHIP_VER(void)
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{
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unsigned int ret = 0;
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unsigned short chip_ver = 0;
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chip_ver = pmic_get_register_value(PMIC_SWCID);
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ret = ((chip_ver & 0x00F0) >> 4);
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return ret;
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}
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#if defined(CONFIG_MACH_MT6739)
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void PMIC_LP_INIT_SETTING(void)
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{
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g_pmic_chip_version = PMIC_CHIP_VER();
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#if LP_INIT_SETTING_VERIFIED
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/*Suspend*/
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pmic_buck_vproc_lp(SW, 1, SW_OFF);
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pmic_buck_vcore_lp(SRCLKEN0, 1, HW_LP);
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pmic_buck_vmodem_lp(SRCLKEN0, 1, HW_LP);
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pmic_buck_vs1_lp(SRCLKEN0, 1, HW_LP);
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pmic_buck_vpa_lp(SW, 1, SW_OFF);
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pmic_ldo_vsram_proc_lp(SW, 1, SW_OFF);
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pmic_ldo_vsram_others_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vfe28_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vxo22_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vrf18_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vrf12_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vefuse_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn33_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn28_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn18_lp(SW, 1, SW_OFF);
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pmic_ldo_vcama_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamd_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamio_lp(SW, 1, SW_OFF);
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pmic_ldo_vldo28_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vaux18_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vaud28_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vio28_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vio18_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vdram_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vmc_lp(SW, 1, SW_OFF);
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pmic_ldo_vmch_lp(SW, 1, SW_OFF);
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pmic_ldo_vemc_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim1_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim2_lp(SW, 1, SW_OFF);
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pmic_ldo_vibr_lp(SW, 1, SW_OFF);
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pmic_ldo_vusb33_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_tref_lp(SW, 1, SW_OFF);
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/*Deepidle*/
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if (PMIC_CHIP_VER() == 1) {
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pmic_buck_vproc_lp(SW, 1, SW_LP);
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pmic_buck_vcore_lp(SW, 1, SW_ON);
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pmic_buck_vmodem_lp(SRCLKEN2, 1, HW_LP);
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pmic_buck_vs1_lp(SRCLKEN2, 1, HW_LP);
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pmic_buck_vpa_lp(SW, 1, SW_OFF);
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pmic_ldo_vsram_proc_lp(SW, 1, SW_LP);
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pmic_ldo_vsram_others_lp(SW, 1, SW_ON);
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pmic_ldo_vfe28_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vxo22_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vrf18_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vrf12_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vefuse_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn33_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn28_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn18_lp(SW, 1, SW_OFF);
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pmic_ldo_vcama_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamd_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamio_lp(SW, 1, SW_OFF);
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pmic_ldo_vldo28_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vaux18_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vaud28_lp(SW, 1, SW_ON);
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pmic_ldo_vio28_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vio18_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vdram_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vmc_lp(SW, 1, SW_OFF);
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pmic_ldo_vmch_lp(SW, 1, SW_OFF);
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pmic_ldo_vemc_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim1_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim2_lp(SW, 1, SW_OFF);
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pmic_ldo_vibr_lp(SW, 1, SW_OFF);
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pmic_ldo_vusb33_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_tref_lp(SW, 1, SW_OFF);
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} else if (PMIC_CHIP_VER() >= 2) {
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pmic_buck_vproc_lp(SW, 1, SW_LP);
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pmic_buck_vcore_lp(SRCLKEN2, 1, HW_LP);
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pmic_buck_vmodem_lp(SRCLKEN2, 1, HW_LP);
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pmic_buck_vs1_lp(SRCLKEN2, 1, HW_LP);
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pmic_buck_vpa_lp(SW, 1, SW_OFF);
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pmic_ldo_vsram_proc_lp(SW, 1, SW_LP);
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pmic_ldo_vsram_others_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vfe28_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vxo22_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vrf18_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vrf12_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vefuse_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn33_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn28_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn18_lp(SW, 1, SW_OFF);
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pmic_ldo_vcama_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamd_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamio_lp(SW, 1, SW_OFF);
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pmic_ldo_vldo28_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vaux18_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vaud28_lp(SW, 1, SW_ON);
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pmic_ldo_vio28_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vio18_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vdram_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vmc_lp(SW, 1, SW_OFF);
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pmic_ldo_vmch_lp(SW, 1, SW_OFF);
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pmic_ldo_vemc_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim1_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim2_lp(SW, 1, SW_OFF);
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pmic_ldo_vibr_lp(SW, 1, SW_OFF);
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pmic_ldo_vusb33_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_tref_lp(SW, 1, SW_OFF);
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} else
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PMICLOG("[PMIC_LP_INIT_SETTING_v1_1705] Chip Ver = %d\n"
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, PMIC_CHIP_VER());
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#endif /*LP_INIT_SETTING_VERIFIED*/
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}
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#elif defined(CONFIG_MACH_MT6765)
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void PMIC_LP_INIT_SETTING(void)
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{
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g_pmic_chip_version = PMIC_CHIP_VER();
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PMICLOG("[PMIC_LP_INIT_SETTING_v1] Chip Ver = %d\n"
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, g_pmic_chip_version);
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#if LP_INIT_SETTING_VERIFIED
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/*Suspend*/
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pmic_buck_vproc_lp(SW, 1, SW_OFF);
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/*pmic_buck_vcore_lp(SRCLKEN0, 1, HW_LP);*/
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pmic_buck_vmodem_lp(SRCLKEN0, 1, HW_LP);
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pmic_buck_vs1_lp(SRCLKEN0, 1, HW_LP);
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pmic_buck_vpa_lp(SW, 1, SW_OFF);
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pmic_ldo_vsram_proc_lp(SW, 1, SW_OFF);
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pmic_ldo_vsram_others_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vfe28_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vxo22_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vrf18_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vrf12_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vefuse_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn33_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn28_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn18_lp(SW, 1, SW_OFF);
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pmic_ldo_vcama_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamd_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamio_lp(SW, 1, SW_OFF);
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pmic_ldo_vldo28_lp(SW, 1, SW_OFF);
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pmic_ldo_vaux18_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vaud28_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vio28_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vio18_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vdram_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vmc_lp(SW, 1, SW_OFF);
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pmic_ldo_vmch_lp(SW, 1, SW_OFF);
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pmic_ldo_vemc_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim1_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim2_lp(SW, 1, SW_OFF);
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pmic_ldo_vibr_lp(SW, 1, SW_OFF);
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pmic_ldo_vusb33_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_tref_lp(SRCLKEN0, 1, HW_OFF);
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/*Deepidle*/
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pmic_buck_vproc_lp(SW, 1, SW_OFF);
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/*pmic_buck_vcore_lp(SRCLKEN2, 1, HW_LP);*/
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pmic_buck_vmodem_lp(SRCLKEN2, 1, HW_LP);
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pmic_buck_vs1_lp(SRCLKEN2, 1, HW_LP);
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pmic_buck_vpa_lp(SW, 1, SW_OFF);
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pmic_ldo_vsram_proc_lp(SW, 1, SW_OFF);
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pmic_ldo_vsram_others_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vfe28_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vxo22_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vrf18_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vrf12_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vefuse_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn33_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn28_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn18_lp(SW, 1, SW_OFF);
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pmic_ldo_vcama_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamd_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamio_lp(SW, 1, SW_OFF);
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pmic_ldo_vldo28_lp(SW, 1, SW_OFF);
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pmic_ldo_vaux18_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vaud28_lp(SW, 1, SW_ON);
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pmic_ldo_vio28_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vio18_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vdram_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_vmc_lp(SW, 1, SW_OFF);
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pmic_ldo_vmch_lp(SW, 1, SW_OFF);
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pmic_ldo_vemc_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim1_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim2_lp(SW, 1, SW_OFF);
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pmic_ldo_vibr_lp(SW, 1, SW_OFF);
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pmic_ldo_vusb33_lp(SRCLKEN2, 1, HW_LP);
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pmic_ldo_tref_lp(SRCLKEN2, 1, HW_OFF);
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#endif /*LP_INIT_SETTING_VERIFIED*/
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}
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#elif defined(CONFIG_MACH_MT6761)
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void PMIC_LP_INIT_SETTING(void)
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{
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int i = 0;
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g_pmic_chip_version = PMIC_CHIP_VER();
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PMICLOG("[PMIC_LP_INIT_SETTING_v1] Chip Ver = %d mrv=%d\n"
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, g_pmic_chip_version
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, is_pmic_mrv());
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#if LP_INIT_SETTING_VERIFIED
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/* Suspend */
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pmic_buck_vproc_lp(SW, 1, SW_OFF);
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pmic_buck_vcore_lp(SRCLKEN0, 1, HW_LP);
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pmic_buck_vmodem_lp(SRCLKEN0, 1, HW_LP);
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pmic_buck_vs1_lp(SRCLKEN0, 1, HW_LP);
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pmic_buck_vpa_lp(SW, 1, SW_OFF);
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/*pmic_ldo_vsram_proc_lp(SW, 1, SW_OFF);*/
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/*pmic_ldo_vsram_others_lp(SRCLKEN0, 1, HW_LP);*/
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pmic_ldo_vfe28_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vxo22_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vrf18_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vrf12_lp(SRCLKEN1, 1, HW_OFF);
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pmic_ldo_vefuse_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn33_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn28_lp(SW, 1, SW_OFF);
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pmic_ldo_vcn18_lp(SW, 1, SW_OFF);
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pmic_ldo_vcama_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamd_lp(SW, 1, SW_OFF);
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pmic_ldo_vcamio_lp(SW, 1, SW_OFF);
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pmic_ldo_vldo28_lp(SW, 1, SW_OFF);
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pmic_ldo_vaux18_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vaud28_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vio28_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vio18_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vdram_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_vmc_lp(SW, 1, SW_OFF);
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pmic_ldo_vmch_lp(SW, 1, SW_OFF);
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pmic_ldo_vemc_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim1_lp(SW, 1, SW_OFF);
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pmic_ldo_vsim2_lp(SW, 1, SW_OFF);
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pmic_ldo_vibr_lp(SW, 1, SW_OFF);
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pmic_ldo_vusb33_lp(SRCLKEN0, 1, HW_LP);
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pmic_ldo_tref_lp(SRCLKEN0, 1, HW_OFF);
|
|
/*Deepidle*/
|
|
pmic_buck_vproc_lp(SW, 1, SW_OFF);
|
|
pmic_buck_vcore_lp(SRCLKEN2, 1, HW_LP);
|
|
pmic_buck_vmodem_lp(SRCLKEN2, 1, HW_LP);
|
|
pmic_buck_vs1_lp(SRCLKEN2, 1, HW_LP);
|
|
pmic_buck_vpa_lp(SW, 1, SW_OFF);
|
|
/*pmic_ldo_vsram_proc_lp(SW, 1, SW_OFF);*/
|
|
/*pmic_ldo_vsram_others_lp(SRCLKEN2, 1, HW_LP);*/
|
|
pmic_ldo_vfe28_lp(SRCLKEN1, 1, HW_OFF);
|
|
pmic_ldo_vxo22_lp(SRCLKEN2, 1, HW_LP);
|
|
pmic_ldo_vrf18_lp(SRCLKEN1, 1, HW_OFF);
|
|
pmic_ldo_vrf12_lp(SRCLKEN1, 1, HW_OFF);
|
|
pmic_ldo_vefuse_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vcn33_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vcn28_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vcn18_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vcama_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vcamd_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vcamio_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vldo28_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vaux18_lp(SRCLKEN2, 1, HW_LP);
|
|
pmic_ldo_vaud28_lp(SW, 1, SW_ON);
|
|
pmic_ldo_vio28_lp(SRCLKEN2, 1, HW_LP);
|
|
pmic_ldo_vio18_lp(SRCLKEN2, 1, HW_LP);
|
|
pmic_ldo_vdram_lp(SRCLKEN2, 1, HW_LP);
|
|
pmic_ldo_vmc_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vmch_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vemc_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vsim1_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vsim2_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vibr_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vusb33_lp(SRCLKEN2, 1, HW_LP);
|
|
pmic_ldo_tref_lp(SRCLKEN2, 1, HW_OFF);
|
|
|
|
/* Workaround setting for MT6357 MRV */
|
|
if (is_pmic_mrv()) {
|
|
/* Suspend */
|
|
pmic_ldo_vsram_others_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vsram_proc_lp(SRCLKEN0, 1, HW_LP);
|
|
/* Deepidle */
|
|
pmic_ldo_vsram_others_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vsram_proc_lp(SRCLKEN2, 1, HW_LP);
|
|
/* Update regulator ops */
|
|
for (i = 0; i < pmic_regulator_ldo_matches_size; i++) {
|
|
if (strncmp(mt_ldos[i].desc.name,
|
|
"vsram_others", 12) == 0) {
|
|
mt_ldos[i].en_cb =
|
|
mt6357_upmu_set_rg_ldo_vsram_proc_en;
|
|
mt_ldos[i].vol_cb =
|
|
mt6357_upmu_set_rg_ldo_vsram_proc_vosel;
|
|
mt_ldos[i].da_en_cb =
|
|
mt6357_upmu_get_da_vsram_proc_en;
|
|
mt_ldos[i].da_vol_cb =
|
|
mt6357_upmu_get_da_vsram_proc_vosel;
|
|
} else if (strncmp(mt_ldos[i].desc.name,
|
|
"vsram_proc", 10) == 0) {
|
|
mt_ldos[i].en_cb =
|
|
mt6357_upmu_set_rg_ldo_vsram_others_en;
|
|
mt_ldos[i].vol_cb =
|
|
mt6357_upmu_set_rg_ldo_vsram_others_vosel;
|
|
mt_ldos[i].da_en_cb =
|
|
mt6357_upmu_get_da_vsram_others_en;
|
|
mt_ldos[i].da_vol_cb =
|
|
mt6357_upmu_get_da_vsram_others_vosel;
|
|
}
|
|
}
|
|
} else {
|
|
/* Suspend */
|
|
pmic_ldo_vsram_proc_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vsram_others_lp(SRCLKEN0, 1, HW_LP);
|
|
/* Deepidle */
|
|
pmic_ldo_vsram_proc_lp(SW, 1, SW_OFF);
|
|
pmic_ldo_vsram_others_lp(SRCLKEN2, 1, HW_LP);
|
|
}
|
|
#endif /*LP_INIT_SETTING_VERIFIED*/
|
|
}
|
|
#endif
|