616 lines
16 KiB
C
616 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/kthread.h>
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#include <linux/mutex.h>
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#include <linux/device.h>
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#include <linux/pm_wakeup.h>
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#include <linux/delay.h>
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#include <linux/ratelimit.h>
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#include <linux/timekeeping.h>
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#include <linux/math64.h>
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#include <linux/of_address.h>
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#include <linux/iio/consumer.h>
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#include <linux/iio/adc/mt635x-auxadc-internal.h>
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#include "include/pmic.h"
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#include "include/pmic_auxadc.h"
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#ifdef CONFIG_MTK_AEE_FEATURE
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#include <mt-plat/aee.h>
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#endif
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#include <mt-plat/upmu_common.h>
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#include <mt-plat/mtk_auxadc_intf.h>
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#ifdef CONFIG_MTK_PMIC_WRAP_HAL
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#include <mach/mtk_pmic_wrap.h>
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#endif
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#ifndef CONFIG_MTK_GAUGE_VERSION
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#define CONFIG_MTK_GAUGE_VERSION 0
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#endif
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#if (CONFIG_MTK_GAUGE_VERSION == 30)
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#include <mt-plat/v1/mtk_battery.h>
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#include <mtk_battery_internal.h>
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#endif
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static struct device *pmic_auxadc_dev;
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static int auxadc_bat_temp_cali(int bat_temp, int precision_factor);
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static bool mts_enable = true;
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/*********************************
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* PMIC AUXADC Exported API
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*********************************/
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static DEFINE_MUTEX(auxadc_ch3_mutex);
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static unsigned int g_pmic_pad_vbif28_vol;
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unsigned int pmic_get_vbif28_volt(void)
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{
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return g_pmic_pad_vbif28_vol;
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}
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bool is_isense_supported(void)
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{
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/* PMIC MT6359 does not support ISENSE */
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return false;
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}
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void pmic_auxadc_suspend(void)
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{
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/* only enable MDRT wakeup when enter suspend */
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pmic_set_register_value(PMIC_AUXADC_MDRT_DET_WKUP_EN, 1);
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/* no need to disable BAT_TEMP detect, remove wk_auxadc_bgd_ctrl */
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/* special call to restore bat_temp_prev when enter suspend */
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auxadc_bat_temp_cali(-1, -1);
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}
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void pmic_auxadc_resume(void)
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{
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/* disable MDRT wakeup when leave suspend */
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pmic_set_register_value(PMIC_AUXADC_MDRT_DET_WKUP_EN, 0);
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/* no need to disable BAT_TEMP detect, remove wk_auxadc_bgd_ctrl */
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}
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void lockadcch3(void)
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{
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mutex_lock(&auxadc_ch3_mutex);
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}
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void unlockadcch3(void)
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{
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mutex_unlock(&auxadc_ch3_mutex);
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}
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void wk_auxadc_reset(void)
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{
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pmic_set_register_value(PMIC_HK_AUXADC_KEY, 0x6359);
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pmic_set_register_value(PMIC_RG_AUXADC_RST, 1);
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pmic_set_register_value(PMIC_RG_AUXADC_RST, 0);
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pmic_set_register_value(PMIC_BANK_AUXADC_SWRST, 1);
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pmic_set_register_value(PMIC_BANK_AUXADC_SWRST, 0);
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pmic_set_register_value(PMIC_HK_AUXADC_KEY, 0);
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/* avoid GPS can't receive AUXADC ready after reset, request again */
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if (PMIC_CHIP_VER() != 0x5910)
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pmic_set_register_value(PMIC_AUXADC_RQST_CH7, 1);
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pmic_set_register_value(PMIC_AUXADC_RQST_DCXO_BY_GPS, 1);
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pr_notice("reset AUXADC done\n");
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/* special call to restore bat_temp_prev after reset AUXADC */
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auxadc_bat_temp_cali(-1, -1);
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}
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/*********************************
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* PMIC AUXADC debug register dump
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*********************************/
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#define DBG_REG_ENABLE 1
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#define DBG_REG_SIZE 384
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#define BAT_TEMP_AEE_DBG 0
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struct pmic_adc_dbg_st {
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int ktime_sec;
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unsigned short reg[DBG_REG_SIZE];
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};
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static unsigned int adc_dbg_addr[DBG_REG_SIZE];
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static void wk_auxadc_dbg_dump(void)
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{
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unsigned char reg_log[861] = "", reg_str[21] = "";
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unsigned short i, j;
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static unsigned char dbg_stamp;
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static struct pmic_adc_dbg_st pmic_adc_dbg[4];
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if (adc_dbg_addr[0] == 0) {
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/* DBG_REG_ENABLE is 0 */
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return;
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}
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for (i = 0; adc_dbg_addr[i] != 0; i++)
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pmic_adc_dbg[dbg_stamp].reg[i] =
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upmu_get_reg_value(adc_dbg_addr[i]);
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pmic_adc_dbg[dbg_stamp].ktime_sec = (int)get_monotonic_coarse().tv_sec;
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dbg_stamp++;
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if (dbg_stamp >= 4)
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dbg_stamp = 0;
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for (i = 0; i < 4; i++) {
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if (pmic_adc_dbg[dbg_stamp].ktime_sec == 0) {
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dbg_stamp++;
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if (dbg_stamp >= 4)
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dbg_stamp = 0;
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continue;
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}
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for (j = 0; adc_dbg_addr[j] != 0; j++) {
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if (j != 0 && j % 43 == 0) {
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pr_notice("%d %s\n",
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pmic_adc_dbg[dbg_stamp].ktime_sec,
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reg_log);
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strncpy(reg_log, "", 860);
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}
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snprintf(reg_str, 20, "Reg[0x%x]=0x%x, ",
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adc_dbg_addr[j],
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pmic_adc_dbg[dbg_stamp].reg[j]);
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strncat(reg_log, reg_str, 860);
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}
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pr_notice("%d %s\n\n",
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pmic_adc_dbg[dbg_stamp].ktime_sec,
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reg_log);
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strncpy(reg_log, "", 860);
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dbg_stamp++;
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if (dbg_stamp >= 4)
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dbg_stamp = 0;
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}
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}
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/* BAT_TEMP filter Maxima and minima then average */
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static int bat_temp_filter(int *arr, unsigned short size)
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{
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unsigned char i, i_max, i_min = 0;
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int arr_max = 0, arr_min = arr[0];
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int sum = 0;
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for (i = 0; i < size; i++) {
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sum += arr[i];
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if (arr[i] > arr_max) {
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arr_max = arr[i];
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i_max = i;
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} else if (arr[i] < arr_min) {
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arr_min = arr[i];
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i_min = i;
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}
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}
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sum = sum - arr_max - arr_min;
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return (sum/(size - 2));
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}
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static int wk_bat_temp_dbg(int bat_temp_prev, int bat_temp)
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{
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int vbif28, bat_temp_new = bat_temp;
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int arr_bat_temp[5], vbat;
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unsigned short i;
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vbif28 = auxadc_priv_read_channel(pmic_auxadc_dev, AUXADC_VBIF);
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pr_notice("BAT_TEMP_PREV:%d,BAT_TEMP:%d,VBIF28:%d\n",
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bat_temp_prev, bat_temp, vbif28);
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if (bat_temp < 200 || abs(bat_temp_prev - bat_temp) > 100) {
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wk_auxadc_dbg_dump();
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for (i = 0; i < 5; i++) {
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arr_bat_temp[i] =
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auxadc_priv_read_channel(pmic_auxadc_dev,
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AUXADC_BAT_TEMP);
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}
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bat_temp_new = bat_temp_filter(arr_bat_temp, 5);
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pr_notice("%d,%d,%d,%d,%d, BAT_TEMP_NEW:%d\n",
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arr_bat_temp[0], arr_bat_temp[1], arr_bat_temp[2],
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arr_bat_temp[3], arr_bat_temp[4], bat_temp_new);
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/* Reset AuxADC to observe VBAT/IBAT/BAT_TEMP */
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wk_auxadc_reset();
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for (i = 0; i < 5; i++) {
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vbat = auxadc_priv_read_channel(pmic_auxadc_dev,
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AUXADC_BATADC);
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arr_bat_temp[i] =
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auxadc_priv_read_channel(pmic_auxadc_dev,
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AUXADC_BAT_TEMP);
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pr_notice("[CH3_DBG] %d,%d\n",
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vbat, arr_bat_temp[i]);
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}
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bat_temp_new = bat_temp_filter(arr_bat_temp, 5);
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pr_notice("Final BAT_TEMP_NEW:%d\n", bat_temp_new);
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}
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return bat_temp_new;
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}
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static void wk_auxadc_dbg_init(void)
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{
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#if DBG_REG_ENABLE
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unsigned short i;
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unsigned int addr = 0xFA2;
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/* All of AUXADC */
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for (i = 0; addr <= 0x127A; i++) {
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adc_dbg_addr[i] = addr;
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addr += 0x2;
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}
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/* Clock related */
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adc_dbg_addr[i++] = MT6359_HK_TOP_CLK_CON0;
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adc_dbg_addr[i++] = MT6359_HK_TOP_CLK_CON1;
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/* RST related */
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adc_dbg_addr[i++] = MT6359_HK_TOP_RST_CON0;
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/* Others */
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adc_dbg_addr[i++] = MT6359_BATON_ANA_CON0;
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adc_dbg_addr[i++] = MT6359_PCHR_VREF_ELR_0;
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#endif
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}
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/*********************************
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* PMIC AUXADC MDRT debug(MTS=Modem Temp Share)
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*********************************/
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/* global variable */
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static unsigned int mdrt_adc;
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static struct wakeup_source *mdrt_wakelock;
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static struct mutex mdrt_mutex;
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static struct task_struct *mdrt_thread_handle;
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/* wake up the thread to polling MDRT data in ms period */
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void wake_up_mdrt_thread(void)
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{
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HKLOG("[%s]\n", __func__);
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if (mdrt_thread_handle != NULL) {
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__pm_stay_awake(mdrt_wakelock);
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wake_up_process(mdrt_thread_handle);
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} else
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pr_notice(PMICTAG "[%s] mdrt_thread_handle not ready\n",
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__func__);
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}
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/* dump MDRT related register */
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static void mdrt_reg_dump(void)
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{
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#ifdef CONFIG_MTK_PMIC_WRAP_HAL
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pwrap_dump_all_register();
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#endif
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pr_notice("AUXADC_ADC15 = 0x%x\n",
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upmu_get_reg_value(MT6359_AUXADC_ADC15));
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pr_notice("AUXADC_ADC16 = 0x%x\n",
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upmu_get_reg_value(MT6359_AUXADC_ADC16));
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pr_notice("AUXADC_ADC17 = 0x%x\n",
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upmu_get_reg_value(MT6359_AUXADC_ADC17));
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pr_notice("AUXADC_MDRT_0 = 0x%x\n",
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upmu_get_reg_value(MT6359_AUXADC_MDRT_0));
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pr_notice("AUXADC_MDRT_1 = 0x%x\n",
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upmu_get_reg_value(MT6359_AUXADC_MDRT_1));
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pr_notice("AUXADC_MDRT_2 = 0x%x\n",
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upmu_get_reg_value(MT6359_AUXADC_MDRT_2));
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pr_notice("AUXADC_MDRT_3 = 0x%x\n",
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upmu_get_reg_value(MT6359_AUXADC_MDRT_3));
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pr_notice("AUXADC_MDRT_4 = 0x%x\n",
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upmu_get_reg_value(MT6359_AUXADC_MDRT_4));
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pr_notice("AUXADC_MDRT_5 = 0x%x\n",
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upmu_get_reg_value(MT6359_AUXADC_MDRT_5));
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/*--AUXADC CLK--*/
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pr_notice("RG_AUXADC_CK_PDN = 0x%x, RG_AUXADC_CK_PDN_HWEN = 0x%x\n",
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pmic_get_register_value(PMIC_RG_AUXADC_CK_PDN),
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pmic_get_register_value(PMIC_RG_AUXADC_CK_PDN_HWEN));
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}
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/* Check MDRT_ADC data has changed or not */
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void mdrt_monitor(void)
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{
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static unsigned int mdrt_cnt;
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static int mdrt_timestamp;
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int mdrt_timestamp_cur = 0;
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unsigned int temp_mdrt_adc = 0;
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if (mdrt_adc == 0)
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return;
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mdrt_timestamp_cur = (int)get_monotonic_coarse().tv_sec;
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if ((mdrt_timestamp_cur - mdrt_timestamp) < 5)
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return;
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mdrt_timestamp = mdrt_timestamp_cur;
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temp_mdrt_adc = pmic_get_register_value(PMIC_AUXADC_ADC_OUT_MDRT);
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pr_notice("[MDRT_ADC] OLD = 0x%x, NOW = 0x%x, CNT = %d\n",
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mdrt_adc, temp_mdrt_adc, mdrt_cnt);
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if (temp_mdrt_adc != mdrt_adc) {
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mdrt_cnt = 0;
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mdrt_adc = temp_mdrt_adc;
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return;
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}
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mdrt_cnt++;
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if (mdrt_cnt >= 7 && mdrt_cnt < 9)
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mdrt_reg_dump();
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if (mdrt_cnt > 15) {
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mdrt_reg_dump();
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mdrt_cnt = 0;
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wake_up_mdrt_thread();
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}
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mdrt_adc = temp_mdrt_adc;
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}
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static int mdrt_polling_rdy(unsigned int *trig_prd,
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unsigned int *rdy_time, unsigned int *mdrt_adc)
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{
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while (pmic_get_register_value(PMIC_AUXADC_ADC_RDY_MDRT) == 1) {
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if (*trig_prd > 100) {
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pr_notice("[MDRT_ADC] no trigger\n");
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return -1;
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}
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(*trig_prd)++;
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mdelay(1);
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}
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while (pmic_get_register_value(PMIC_AUXADC_ADC_RDY_MDRT) == 0) {
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if (*rdy_time > 100) {
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pr_notice("[MDRT_ADC] no ready\n");
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wk_auxadc_reset();
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return -2;
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}
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(*rdy_time)++;
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mdelay(1);
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}
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*mdrt_adc = pmic_get_register_value(PMIC_AUXADC_ADC_OUT_MDRT);
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return 0;
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}
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static int mdrt_kthread(void *x)
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{
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unsigned int polling_cnt;
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unsigned int trig_prd;
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unsigned int rdy_time;
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unsigned int temp_mdrt_adc;
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/* Run on a process content */
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while (1) {
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mutex_lock(&mdrt_mutex);
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polling_cnt = 0;
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temp_mdrt_adc = pmic_get_register_value(
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PMIC_AUXADC_ADC_OUT_MDRT);
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while (mdrt_adc == temp_mdrt_adc) {
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trig_prd = 0;
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rdy_time = 0;
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mdrt_polling_rdy(&trig_prd,
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&rdy_time, &temp_mdrt_adc);
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if (polling_cnt % 20 == 0) {
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pr_notice("[MDRT_ADC] trig_prd=%d, rdy_time=%d, MDRT_OUT=%d\n"
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, trig_prd, rdy_time,
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temp_mdrt_adc);
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}
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if (polling_cnt == 156) { /* 156 * 32ms ~= 5s*/
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pr_notice("[MDRT_ADC] (%d) reset AUXADC\n",
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polling_cnt);
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wk_auxadc_reset();
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}
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if (polling_cnt >= 312) { /* 312 * 32ms ~= 10s*/
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mdrt_reg_dump();
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#ifdef CONFIG_MTK_AEE_FEATURE
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aee_kernel_warning("PMIC AUXADC:MDRT", "MDRT");
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#endif
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break;
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}
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polling_cnt++;
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}
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mutex_unlock(&mdrt_mutex);
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__pm_relax(mdrt_wakelock);
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set_current_state(TASK_INTERRUPTIBLE);
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schedule();
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/* Fix Cove.Scan, should not happened */
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if (polling_cnt >= 0x1000)
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break;
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}
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return 0;
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}
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static void mdrt_monitor_init(void)
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{
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//wakeup_source_init(&mdrt_wakelock, "MDRT Monitor wakelock");
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mdrt_wakelock = wakeup_source_register(NULL, "MDRT Monitor wakelock");
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mutex_init(&mdrt_mutex);
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mdrt_adc = pmic_get_register_value(PMIC_AUXADC_ADC_OUT_MDRT);
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mdrt_thread_handle = kthread_create(mdrt_kthread, NULL, "mdrt_thread");
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if (IS_ERR(mdrt_thread_handle)) {
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mdrt_thread_handle = NULL;
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pr_notice(PMICTAG "[%s] creation fails\n", __func__);
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} else
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HKLOG("[%s] creation Done\n", __func__);
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}
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/*********************************
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* Legacy API for getting PMIC AUXADC value
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*********************************/
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struct legacy_auxadc_t {
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const char *channel_name;
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struct iio_channel *chan;
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};
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#define LEGACY_AUXADC_GEN(_name) \
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{ \
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.channel_name = "AUXADC_"#_name,\
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}
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static struct legacy_auxadc_t legacy_auxadc[] = {
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LEGACY_AUXADC_GEN(BATADC),
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LEGACY_AUXADC_GEN(VCDT),
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LEGACY_AUXADC_GEN(BAT_TEMP),
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LEGACY_AUXADC_GEN(CHIP_TEMP),
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LEGACY_AUXADC_GEN(VCORE_TEMP),
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LEGACY_AUXADC_GEN(VPROC_TEMP),
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LEGACY_AUXADC_GEN(VGPU_TEMP),
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LEGACY_AUXADC_GEN(ACCDET),
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LEGACY_AUXADC_GEN(VDCXO),
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LEGACY_AUXADC_GEN(TSX_TEMP),
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LEGACY_AUXADC_GEN(HPOFS_CAL),
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LEGACY_AUXADC_GEN(DCXO_TEMP),
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LEGACY_AUXADC_GEN(VBIF),
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};
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static void legacy_auxadc_init(struct device *dev)
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{
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int i = 0;
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for (i = AUXADC_LIST_START; i <= AUXADC_LIST_END; i++) {
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legacy_auxadc[i].chan =
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devm_iio_channel_get(dev,
|
|
legacy_auxadc[i].channel_name);
|
|
if (IS_ERR(legacy_auxadc[i].chan))
|
|
pr_notice("%s get fail with list %d, dev_name:%s\n",
|
|
legacy_auxadc[i].channel_name, i,
|
|
dev_name(dev));
|
|
}
|
|
}
|
|
|
|
int pmic_get_auxadc_value(int list)
|
|
{
|
|
int bat_cur = 0, is_charging = 0;
|
|
int value = 0, ret = 0;
|
|
|
|
if (list < AUXADC_LIST_START || list > AUXADC_LIST_END) {
|
|
pr_notice("[%s] Invalid channel list(%d)\n", __func__, list);
|
|
return -EINVAL;
|
|
}
|
|
if (!(legacy_auxadc[list].chan) || IS_ERR(legacy_auxadc[list].chan)) {
|
|
pr_notice("[%s] iio channel consumer error(%s)\n",
|
|
__func__, legacy_auxadc[list].channel_name);
|
|
return PTR_ERR(legacy_auxadc[list].chan);
|
|
}
|
|
if (list == AUXADC_LIST_BATTEMP) {
|
|
ret = iio_read_channel_processed(
|
|
legacy_auxadc[AUXADC_LIST_VBIF].chan,
|
|
&g_pmic_pad_vbif28_vol);
|
|
#if (CONFIG_MTK_GAUGE_VERSION == 30)
|
|
is_charging = gauge_get_current(&bat_cur);
|
|
#endif
|
|
if (is_charging == 0)
|
|
bat_cur = 0 - bat_cur;
|
|
pr_notice("[CH3_DBG] bat_cur = %d\n", bat_cur);
|
|
}
|
|
if (list == AUXADC_LIST_HPOFS_CAL) {
|
|
ret = iio_read_channel_raw(
|
|
legacy_auxadc[list].chan, &value);
|
|
} else {
|
|
ret = iio_read_channel_processed(
|
|
legacy_auxadc[list].chan, &value);
|
|
}
|
|
if (ret < 0)
|
|
return ret;
|
|
return value;
|
|
}
|
|
|
|
/*********************************
|
|
* PMIC AUXADC chip setting for IIO ADC driver
|
|
*********************************/
|
|
static void auxadc_batadc_convert(unsigned char convert)
|
|
{
|
|
/* when user wants to get BATADC, starting monitor MDRT for debugging*/
|
|
if (convert == 0)
|
|
mdrt_monitor();
|
|
}
|
|
|
|
static void auxadc_bat_temp_convert(unsigned char convert)
|
|
{
|
|
if (convert == 1)
|
|
mutex_lock(&auxadc_ch3_mutex);
|
|
else if (convert == 0)
|
|
mutex_unlock(&auxadc_ch3_mutex);
|
|
}
|
|
|
|
/* MT6359 no need to set RG_BATON_TDET_EN */
|
|
|
|
static int auxadc_bat_temp_cali(int bat_temp, int precision_factor)
|
|
{
|
|
static int bat_temp_prev;
|
|
static unsigned int dbg_count;
|
|
static unsigned int aee_count;
|
|
|
|
if (bat_temp == -1 && precision_factor == -1) {
|
|
bat_temp_prev = 0;
|
|
return 0;
|
|
}
|
|
if (bat_temp_prev == 0)
|
|
goto out;
|
|
|
|
dbg_count++;
|
|
if (bat_temp < 200 || abs(bat_temp_prev - bat_temp) > 100) {
|
|
/* dump debug log when BAT_TEMP being abnormal */
|
|
bat_temp = wk_bat_temp_dbg(bat_temp_prev, bat_temp);
|
|
#if BAT_TEMP_AEE_DBG
|
|
#ifdef CONFIG_MTK_AEE_FEATURE
|
|
if (aee_count < 2)
|
|
aee_kernel_warning("PMIC AUXADC:BAT_TEMP", "BAT_TEMP");
|
|
#endif
|
|
pr_notice("PMIC AUXADC BAT_TEMP aee_count=%d\n", aee_count);
|
|
#endif
|
|
aee_count++;
|
|
} else if (dbg_count % 50 == 0) {
|
|
/* dump debug log in normal case */
|
|
wk_bat_temp_dbg(bat_temp_prev, bat_temp);
|
|
}
|
|
out:
|
|
bat_temp_prev = bat_temp;
|
|
return bat_temp;
|
|
}
|
|
|
|
static void parsing_cust_setting(void)
|
|
{
|
|
struct device_node *np;
|
|
unsigned int disable_modem = 0;
|
|
|
|
/* check customer setting */
|
|
np = of_find_compatible_node(NULL, NULL,
|
|
"mediatek,mt-pmic-custom-setting");
|
|
if (!np) {
|
|
HKLOG("[%s]Failed to find device-tree node\n", __func__);
|
|
return;
|
|
}
|
|
|
|
if (!of_property_read_u32(np, "disable-modem", &disable_modem)) {
|
|
if (disable_modem)
|
|
mts_enable = false;
|
|
}
|
|
|
|
of_node_put(np);
|
|
}
|
|
|
|
int pmic_auxadc_chip_init(struct device *dev)
|
|
{
|
|
int ret = 0;
|
|
struct iio_channel *chan_vbif;
|
|
|
|
HKLOG("%s\n", __func__);
|
|
pmic_auxadc_dev = dev;
|
|
|
|
auxadc_set_convert_fn(AUXADC_BATADC, auxadc_batadc_convert);
|
|
auxadc_set_convert_fn(AUXADC_BAT_TEMP, auxadc_bat_temp_convert);
|
|
auxadc_set_cali_fn(AUXADC_BAT_TEMP, auxadc_bat_temp_cali);
|
|
|
|
legacy_auxadc_init(dev);
|
|
|
|
wk_auxadc_dbg_init();
|
|
parsing_cust_setting();
|
|
if (mts_enable)
|
|
mdrt_monitor_init();
|
|
/* only enable MDRT wakeup when enter suspend */
|
|
pmic_set_register_value(PMIC_AUXADC_MDRT_DET_WKUP_EN, 0);
|
|
/* set MDRT_WAKEUP AVG_NUM to the same with Ch7(128 samples) */
|
|
pmic_set_register_value(PMIC_AUXADC_AVG_NUM_CH7_WAKEUP, 0x6);
|
|
|
|
/* update VBIF28 by AUXADC */
|
|
chan_vbif = iio_channel_get(dev, "AUXADC_VBIF");
|
|
if (IS_ERR(chan_vbif)) {
|
|
pr_notice("[%s] iio channel consumer error(AUXADC_VBIF)\n",
|
|
__func__);
|
|
} else {
|
|
ret = iio_read_channel_processed(chan_vbif,
|
|
&g_pmic_pad_vbif28_vol);
|
|
iio_channel_release(chan_vbif);
|
|
}
|
|
pr_info("****[%s] VBIF28 = %d, MDRT_ADC = 0x%x\n",
|
|
__func__, pmic_get_vbif28_volt(), mdrt_adc);
|
|
|
|
return ret;
|
|
}
|