610 lines
15 KiB
C
610 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/types.h>
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#include <mt-plat/mtk_pwm_hal_pub.h>
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#include <mach/mtk_pwm_hal.h>
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#include <mach/mtk_pwm_prv.h>
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#include <linux/clk.h>
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#include <mt-plat/mtk_chip.h>
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#include <linux/device.h>
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#ifdef CONFIG_OF
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#endif
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/**********************************
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* Global data
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***********************************/
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enum {
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PWM_CON,
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PWM_HDURATION,
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PWM_LDURATION,
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PWM_GDURATION,
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PWM_BUF0_BASE_ADDR,
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PWM_BUF0_SIZE,
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PWM_BUF1_BASE_ADDR,
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PWM_BUF1_SIZE,
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PWM_SEND_DATA0,
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PWM_SEND_DATA1,
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PWM_WAVE_NUM,
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PWM_DATA_WIDTH,
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PWM_THRESH,
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PWM_SEND_WAVENUM,
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PWM_VALID,
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PWM_BUF_BASE_ADDR2
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} PWM_REG_OFF;
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#ifdef CONFIG_OF
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unsigned long PWM_register[PWM_MAX] = {};
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void __iomem *pwm_infracfg_base;
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#endif
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/**************************************************************/
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enum {
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PWM1_CLK,
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PWM2_CLK,
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PWM3_CLK,
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PWM4_CLK,
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PWM_HCLK,
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PWM_CLK,
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PWM_CLK_NUM,
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};
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const char *pwm_clk_name[] = {
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"PWM1-main",
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"PWM2-main",
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"PWM3-main",
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"PWM4-main",
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"PWM-HCLK-main",
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"PWM-main"
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};
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struct clk *pwm_clk[PWM_CLK_NUM];
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void mt_pwm_power_on_hal(u32 pwm_no, bool pmic_pad, unsigned long *power_flag)
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{
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int clk_en_ret;
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/* Set pwm_main , pwm_hclk_main(for memory and random mode) */
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if (0 == (*power_flag)) {
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pr_debug("[PWM][CCF]enable clk PWM_CLK:%p PWM_HCLK: %p\n",
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pwm_clk[PWM_CLK], pwm_clk[PWM_HCLK]);
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clk_en_ret = clk_prepare_enable(pwm_clk[PWM_CLK]);
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if (clk_en_ret) {
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pr_notice("[PWM][CCF]enable clk PWM_CLK failed. ret:%d, clk_pwm_main:%p\n",
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clk_en_ret, pwm_clk[PWM_CLK]);
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} else
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set_bit(PWM_CLK, power_flag);
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clk_en_ret = clk_prepare_enable(pwm_clk[PWM_HCLK]);
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if (clk_en_ret) {
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pr_notice("[PWM][CCF]enable clk PWM_HCLK failed. ret:%d, clk_pwm_hclk_main:%p\n",
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clk_en_ret, pwm_clk[PWM_HCLK]);
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} else
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set_bit(PWM_HCLK, power_flag);
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}
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/* Set pwm_no clk */
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if (!test_bit(pwm_no, power_flag)) {
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pr_debug("[PWM][CCF]enable clk_pwm%d :%p\n",
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pwm_no, pwm_clk[pwm_no]);
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clk_en_ret = clk_prepare_enable(pwm_clk[pwm_no]);
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if (clk_en_ret) {
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pr_notice("[PWM][CCF]enable clk_pwm_main failed. ret:%d, clk_pwm%d :%p\n",
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clk_en_ret, pwm_no, pwm_clk[pwm_no]);
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} else
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set_bit(pwm_no, power_flag);
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}
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}
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void mt_pwm_power_off_hal(u32 pwm_no, bool pmic_pad, unsigned long *power_flag)
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{
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if (test_bit(pwm_no, power_flag)) {
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pr_debug("[PWM][CCF]disable clk_pwm%d :%p\n",
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pwm_no, pwm_clk[pwm_no]);
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clk_disable_unprepare(pwm_clk[pwm_no]);
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clear_bit(pwm_no, power_flag);
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}
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if ((*power_flag) == ((1 << PWM_HCLK) | (1 << PWM_CLK))) {
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/* Disable PWM-main, PWM-HCLK-main */
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pr_debug("[PWM][CCF]disable clk_pwm :%p, clk_pwm_hclk :%p\n",
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pwm_clk[PWM_CLK], pwm_clk[PWM_HCLK]);
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if (test_bit(PWM_HCLK, power_flag)) {
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clk_disable_unprepare(pwm_clk[PWM_HCLK]);
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clear_bit(PWM_HCLK, power_flag);
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}
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if (test_bit(PWM_CLK, power_flag)) {
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clk_disable_unprepare(pwm_clk[PWM_CLK]);
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clear_bit(PWM_CLK, power_flag);
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}
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}
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}
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void mt_pwm_init_power_flag(unsigned long *power_flag)
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{
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PWM_register[PWM1] = (unsigned long)pwm_base + 0x0010;
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PWM_register[PWM2] = (unsigned long)pwm_base + 0x0050;
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PWM_register[PWM3] = (unsigned long)pwm_base + 0x0090;
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PWM_register[PWM4] = (unsigned long)pwm_base + 0x00d0;
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}
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s32 mt_pwm_sel_pmic_hal(u32 pwm_no)
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{
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pr_debug("mt_pwm_sel_pmic\n");
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return -EINVALID;
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}
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s32 mt_pwm_sel_ap_hal(u32 pwm_no)
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{
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pr_debug("mt_pwm_sel_ap\n");
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return -EINVALID;
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}
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void mt_set_pwm_enable_hal(u32 pwm_no)
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{
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SETREG32(PWM_ENABLE, 1 << pwm_no);
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}
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void mt_set_pwm_disable_hal(u32 pwm_no)
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{
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CLRREG32(PWM_ENABLE, 1 << pwm_no);
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}
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void mt_set_pwm_enable_seqmode_hal(void)
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{
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}
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void mt_set_pwm_disable_seqmode_hal(void)
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{
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}
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s32 mt_set_pwm_test_sel_hal(u32 val)
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{
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return 0;
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}
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void mt_set_pwm_clk_hal(u32 pwm_no, u32 clksrc, u32 div)
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{
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unsigned long reg_con;
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reg_con = PWM_register[pwm_no] + 4 * PWM_CON;
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MASKREG32(reg_con, PWM_CON_CLKDIV_MASK, div);
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if ((clksrc & 0x80000000) != 0) {
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clksrc &= ~(0x80000000);
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if (clksrc == CLK_BLOCK_BY_1625_OR_32K) {/* old mode: 32k clk*/
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SETREG32(reg_con, 1 << PWM_CON_CLKSEL_OLD_OFFSET);
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SETREG32(reg_con, 1 << PWM_CON_CLKSEL_OFFSET);
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pr_info("%s: PWM old clock set 32K!\n", __func__);
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} else {
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CLRREG32(reg_con, 1 << PWM_CON_CLKSEL_OLD_OFFSET);
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SETREG32(reg_con, 1 << PWM_CON_CLKSEL_OFFSET);
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pr_info("%s: PWM old clock set 26M/1625!\n", __func__);
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}
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} else {
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CLRREG32(reg_con, 1 << PWM_CON_CLKSEL_OLD_OFFSET);
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if (clksrc == CLK_BLOCK) {
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CLRREG32(reg_con, 1 << PWM_CON_CLKSEL_OFFSET);
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pr_info("%s: PWM new clock set 26M!\n", __func__);
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} else if (clksrc == CLK_BLOCK_BY_1625_OR_32K) {
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SETREG32(reg_con, 1 << PWM_CON_CLKSEL_OFFSET);
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pr_info("%s: PWM new clock set 26M/1625!\n", __func__);
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} else
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pr_info("clksrc(%u) set err\n", clksrc);
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}
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}
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s32 mt_get_pwm_clk_hal(u32 pwm_no)
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{
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s32 clk, clksrc, clkdiv;
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unsigned long reg_con, reg_val;
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reg_con = PWM_register[pwm_no] + 4 * PWM_CON;
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reg_val = INREG32(reg_con);
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if (((reg_val & PWM_CON_CLKSEL_MASK) >> PWM_CON_CLKSEL_OFFSET) == 1)
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if (((reg_val & PWM_CON_OLD_MODE_MASK) >>
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PWM_CON_OLD_MODE_OFFSET) == 1)
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clksrc = 32 * 1024;
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else
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clksrc = BLOCK_CLK;
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else
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clksrc = BLOCK_CLK / 1625;
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clkdiv = 2 << (reg_val & PWM_CON_CLKDIV_MASK);
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if (clkdiv <= 0) {
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pr_debug("clkdiv less zero, not valid\n");
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return -ERROR;
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}
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clk = clksrc / clkdiv;
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pr_debug("CLK is :%d\n", clk);
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return clk;
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}
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s32 mt_set_pwm_con_datasrc_hal(u32 pwm_no, u32 val)
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{
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unsigned long reg_con;
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reg_con = PWM_register[pwm_no] + 4 * PWM_CON;
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if (val == PWM_FIFO)
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CLRREG32(reg_con, 1 << PWM_CON_SRCSEL_OFFSET);
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else if (val == MEMORY)
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SETREG32(reg_con, 1 << PWM_CON_SRCSEL_OFFSET);
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else
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return 1;
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return 0;
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}
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s32 mt_set_pwm_con_mode_hal(u32 pwm_no, u32 val)
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{
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unsigned long reg_con;
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reg_con = PWM_register[pwm_no] + 4 * PWM_CON;
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if (val == PERIOD)
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CLRREG32(reg_con, 1 << PWM_CON_MODE_OFFSET);
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else if (val == RAND)
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SETREG32(reg_con, 1 << PWM_CON_MODE_OFFSET);
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else
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return 1;
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return 0;
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}
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s32 mt_set_pwm_con_idleval_hal(u32 pwm_no, uint16_t val)
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{
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unsigned long reg_con;
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reg_con = PWM_register[pwm_no] + 4 * PWM_CON;
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if (val == IDLE_TRUE)
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SETREG32(reg_con, 1 << PWM_CON_IDLE_VALUE_OFFSET);
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else if (val == IDLE_FALSE)
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CLRREG32(reg_con, 1 << PWM_CON_IDLE_VALUE_OFFSET);
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else
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return 1;
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return 0;
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}
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s32 mt_set_pwm_con_guardval_hal(u32 pwm_no, uint16_t val)
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{
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unsigned long reg_con;
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reg_con = PWM_register[pwm_no] + 4 * PWM_CON;
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if (val == GUARD_TRUE)
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SETREG32(reg_con, 1 << PWM_CON_GUARD_VALUE_OFFSET);
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else if (val == GUARD_FALSE)
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CLRREG32(reg_con, 1 << PWM_CON_GUARD_VALUE_OFFSET);
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else
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return 1;
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return 0;
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}
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void mt_set_pwm_con_stpbit_hal(u32 pwm_no, u32 stpbit, u32 srcsel)
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{
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unsigned long reg_con;
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reg_con = PWM_register[pwm_no] + 4 * PWM_CON;
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if (srcsel == PWM_FIFO)
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MASKREG32(reg_con, PWM_CON_STOP_BITS_MASK,
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stpbit << PWM_CON_STOP_BITS_OFFSET);
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if (srcsel == MEMORY)
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MASKREG32(reg_con,
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PWM_CON_STOP_BITS_MASK &
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(0x1f << PWM_CON_STOP_BITS_OFFSET),
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stpbit << PWM_CON_STOP_BITS_OFFSET);
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}
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s32 mt_set_pwm_con_oldmode_hal(u32 pwm_no, u32 val)
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{
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unsigned long reg_con;
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reg_con = PWM_register[pwm_no] + 4 * PWM_CON;
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if (val == OLDMODE_DISABLE)
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CLRREG32(reg_con, 1 << PWM_CON_OLD_MODE_OFFSET);
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else if (val == OLDMODE_ENABLE)
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SETREG32(reg_con, 1 << PWM_CON_OLD_MODE_OFFSET);
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else
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return 1;
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return 0;
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}
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void mt_set_pwm_HiDur_hal(u32 pwm_no, uint16_t DurVal)
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{ /* only low 16 bits are valid */
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unsigned long reg_HiDur;
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reg_HiDur = PWM_register[pwm_no] + 4 * PWM_HDURATION;
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OUTREG32(reg_HiDur, DurVal);
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}
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void mt_set_pwm_LowDur_hal(u32 pwm_no, uint16_t DurVal)
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{
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unsigned long reg_LowDur;
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reg_LowDur = PWM_register[pwm_no] + 4 * PWM_LDURATION;
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OUTREG32(reg_LowDur, DurVal);
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}
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void mt_set_pwm_GuardDur_hal(u32 pwm_no, uint16_t DurVal)
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{
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unsigned long reg_GuardDur;
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reg_GuardDur = PWM_register[pwm_no] + 4 * PWM_GDURATION;
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OUTREG32(reg_GuardDur, DurVal);
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}
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void mt_set_pwm_send_data0_hal(u32 pwm_no, u32 data)
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{
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unsigned long reg_data0;
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reg_data0 = PWM_register[pwm_no] + 4 * PWM_SEND_DATA0;
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OUTREG32(reg_data0, data);
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}
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void mt_set_pwm_send_data1_hal(u32 pwm_no, u32 data)
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{
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unsigned long reg_data1;
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reg_data1 = PWM_register[pwm_no] + 4 * PWM_SEND_DATA1;
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OUTREG32(reg_data1, data);
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}
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void mt_set_pwm_wave_num_hal(u32 pwm_no, uint16_t num)
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{
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unsigned long reg_wave_num;
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reg_wave_num = PWM_register[pwm_no] + 4 * PWM_WAVE_NUM;
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OUTREG32(reg_wave_num, num);
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}
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void mt_set_pwm_data_width_hal(u32 pwm_no, uint16_t width)
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{
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unsigned long reg_data_width;
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reg_data_width = PWM_register[pwm_no] + 4 * PWM_DATA_WIDTH;
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OUTREG32(reg_data_width, width);
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}
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void mt_set_pwm_thresh_hal(u32 pwm_no, uint16_t thresh)
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{
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unsigned long reg_thresh;
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reg_thresh = PWM_register[pwm_no] + 4 * PWM_THRESH;
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OUTREG32(reg_thresh, thresh);
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}
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s32 mt_get_pwm_send_wavenum_hal(u32 pwm_no)
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{
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unsigned long reg_send_wavenum = 0;
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reg_send_wavenum = PWM_register[pwm_no] + 4 * PWM_SEND_WAVENUM;
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return INREG32(reg_send_wavenum);
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}
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void mt_set_intr_enable_hal(u32 pwm_intr_enable_bit)
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{
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SETREG32(PWM_INT_ENABLE, 1 << pwm_intr_enable_bit);
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}
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s32 mt_get_intr_status_hal(u32 pwm_intr_status_bit)
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{
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unsigned long int_status;
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int_status = INREG32(PWM_INT_STATUS);
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int_status = (int_status >> pwm_intr_status_bit) & 0x01;
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return int_status;
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}
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void mt_set_intr_ack_hal(u32 pwm_intr_ack_bit)
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{
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SETREG32(PWM_INT_ACK, 1 << pwm_intr_ack_bit);
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}
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void mt_set_pwm_buf0_addr_hal(u32 pwm_no, dma_addr_t addr)
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{
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unsigned long reg_buff0_addr, reg_buff0_addr2;
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unsigned int upper_32_addr;
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unsigned int lower_32_addr;
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reg_buff0_addr = PWM_register[pwm_no] + 4 * PWM_BUF0_BASE_ADDR;
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reg_buff0_addr2 = PWM_register[pwm_no] + 4 * PWM_BUF_BASE_ADDR2;
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lower_32_addr = lower_32_bits(addr);
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OUTREG32_DMA(reg_buff0_addr, lower_32_addr);
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CLRREG32(reg_buff0_addr2, 0xF);
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if (addr > 0xFFFFFFFF) {
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upper_32_addr = upper_32_bits(addr);
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SETREG32(reg_buff0_addr2, upper_32_addr);
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}
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}
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void mt_set_pwm_buf0_size_hal(u32 pwm_no, uint16_t size)
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{
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unsigned long reg_buff0_size;
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reg_buff0_size = PWM_register[pwm_no] + 4 * PWM_BUF0_SIZE;
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OUTREG32(reg_buff0_size, size);
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}
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void mt_pwm_dump_regs_hal(void)
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{
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int i = 0;
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unsigned long reg_val = 0;
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pr_info("=========> [PWM DUMP RG START] <=========\n ");
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for (i = PWM1; i < PWM_MAX; i++) {
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reg_val = INREG32(PWM_register[i] + 4 * PWM_CON);
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pr_info("[PWM%d_CON]: 0x%lx\n", i + 1, reg_val);
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reg_val = INREG32(PWM_register[i] + 4 * PWM_HDURATION);
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pr_info("[PWM%d_HDURATION]: 0x%lx\n", i + 1, reg_val);
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reg_val = INREG32(PWM_register[i] + 4 * PWM_LDURATION);
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pr_info("[PWM%d_LDURATION]: 0x%lx\n", i + 1, reg_val);
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reg_val = INREG32(PWM_register[i] + 4 * PWM_GDURATION);
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pr_info("[PWM%d_GDURATION]: 0x%lx\n", i + 1, reg_val);
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reg_val = INREG32(PWM_register[i] + 4 * PWM_BUF0_BASE_ADDR);
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pr_info("[PWM%d_BUF0_BASE_ADDR]: 0x%lx\n", i, reg_val);
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reg_val = INREG32(PWM_register[i] + 4 * PWM_BUF0_SIZE);
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pr_info("[PWM%d_BUF0_SIZE]: 0x%lx\n", i, reg_val);
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reg_val = INREG32(PWM_register[i] + 4 * PWM_BUF1_BASE_ADDR);
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pr_info("[PWM%d_BUF1_BASE_ADDR]: 0x%lx\n", i, reg_val);
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|
reg_val = INREG32(PWM_register[i] + 4 * PWM_BUF1_SIZE);
|
|
pr_info("[PWM%d_BUF1_SIZE]: 0x%lx\n", i + 1, reg_val);
|
|
|
|
reg_val = INREG32(PWM_register[i] + 4 * PWM_SEND_DATA0);
|
|
pr_info("[PWM%d_SEND_DATA0]: 0x%lx]\n", i + 1, reg_val);
|
|
reg_val = INREG32(PWM_register[i] + 4 * PWM_SEND_DATA1);
|
|
pr_info("[PWM%d_PWM_SEND_DATA1]: 0x%lx\n", i + 1, reg_val);
|
|
reg_val = INREG32(PWM_register[i] + 4 * PWM_WAVE_NUM);
|
|
pr_info("[PWM%d_WAVE_NUM]: 0x%lx\n", i + 1, reg_val);
|
|
reg_val = INREG32(PWM_register[i] + 4 * PWM_DATA_WIDTH);
|
|
pr_info("[PWM%d_WIDTH]: 0x%lx\n", i + 1, reg_val);
|
|
|
|
reg_val = INREG32(PWM_register[i] + 4 * PWM_THRESH);
|
|
pr_info("[PWM%d_THRESH]: 0x%lx\n", i + 1, reg_val);
|
|
reg_val = INREG32(PWM_register[i] + 4 * PWM_SEND_WAVENUM);
|
|
pr_info("[PWM%d_SEND_WAVENUM]: 0x%lx\n\r", i + 1, reg_val);
|
|
reg_val = INREG32(PWM_register[i] + 4 * PWM_BUF_BASE_ADDR2);
|
|
pr_info("[PWM%d_BUF_BASE_ADDR2]: 0x%lx\n\r", i + 1, reg_val);
|
|
}
|
|
|
|
reg_val = INREG32(PWM_ENABLE);
|
|
pr_info("[PWM_ENABLE]: 0x%lx\n ", reg_val);
|
|
reg_val = INREG32(PWM_CK_26M_SEL);
|
|
pr_info("[PWM_26M_SEL]: 0x%lx\n ", reg_val);
|
|
/*pr_info("peri pdn0 clock: 0x%x\n", INREG32(INFRA_PDN_STA0));*/
|
|
reg_val = INREG32(PWM_INT_ENABLE);
|
|
pr_info("[PWM_INT_ENABLE]:0x%lx\n ", reg_val);
|
|
reg_val = INREG32(PWM_INT_STATUS);
|
|
pr_info("[PWM_INT_STATUS]: 0x%lx\n ", reg_val);
|
|
reg_val = INREG32(PWM_EN_STATUS);
|
|
pr_info("[PWM_EN_STATUS]: 0x%lx\n ", reg_val);
|
|
pr_info("=========> [PWM DUMP RG END] <=========\n ");
|
|
|
|
}
|
|
|
|
void pwm_debug_store_hal(void)
|
|
{
|
|
/* dump clock status */
|
|
/*pr_debug("peri pdn0 clock: 0x%x\n", INREG32(INFRA_PDN_STA0));*/
|
|
}
|
|
|
|
void pwm_debug_show_hal(void)
|
|
{
|
|
mt_pwm_dump_regs_hal();
|
|
}
|
|
|
|
/*----------3dLCM support-----------*/
|
|
/*
|
|
*base pwm2, select pwm3&4&5 same as pwm2 or inversion of pwm2
|
|
*/
|
|
void mt_set_pwm_3dlcm_enable_hal(u8 enable)
|
|
{
|
|
SETREG32(PWM_3DLCM, 1 << PWM_3DLCM_ENABLE_OFFSET);
|
|
}
|
|
|
|
/*
|
|
*set "pwm_no" inversion of pwm base or not
|
|
*/
|
|
void mt_set_pwm_3dlcm_inv_hal(u32 pwm_no, u8 inv)
|
|
{
|
|
/*set "pwm_no" as auxiliary first */
|
|
SETREG32(PWM_3DLCM, 1 << (pwm_no + 16));
|
|
|
|
if (inv)
|
|
SETREG32(PWM_3DLCM, 1 << (pwm_no + 1));
|
|
else
|
|
CLRREG32(PWM_3DLCM, 1 << (pwm_no + 1));
|
|
}
|
|
|
|
void mt_set_pwm_3dlcm_base_hal(u32 pwm_no)
|
|
{
|
|
CLRREG32(PWM_3DLCM, 0x7F << 8);
|
|
SETREG32(PWM_3DLCM, 1 << (pwm_no + 8));
|
|
}
|
|
|
|
void mt_pwm_26M_clk_enable_hal(u32 enable)
|
|
{
|
|
unsigned long reg_con;
|
|
|
|
/* select 66M or 26M */
|
|
reg_con = (unsigned long)PWM_CK_26M_SEL;
|
|
if (enable)
|
|
SETREG32(reg_con, 1 << PWM_CK_26M_SEL_OFFSET);
|
|
else
|
|
CLRREG32(reg_con, 1 << PWM_CK_26M_SEL_OFFSET);
|
|
|
|
}
|
|
|
|
void mt_pwm_clk_sel_hal(u32 pwm_no, u32 clk_src)
|
|
{
|
|
if (pwm_no > PWM_MAX)
|
|
pr_info("PWM: invalid pwm_no\n");
|
|
switch (clk_src) {
|
|
/* 32K */
|
|
case 0x00:
|
|
CLRREG32(PWM_CLK_SRC_CTRL, 0x3 << (pwm_no * 2));
|
|
CLRREG32(PWM_CLK_SRC_CTRL, 0x3 << PWM_BCLK_SW_CTRL_OFFSET);
|
|
break;
|
|
/* 26M */
|
|
case 0x01:
|
|
CLRREG32(PWM_CLK_SRC_CTRL, 0x3 << (pwm_no * 2));
|
|
CLRREG32(PWM_CLK_SRC_CTRL, 0x3 << PWM_BCLK_SW_CTRL_OFFSET);
|
|
SETREG32(PWM_CLK_SRC_CTRL, 0x1 << (pwm_no * 2));
|
|
SETREG32(PWM_CLK_SRC_CTRL, 0x1 << PWM_BCLK_SW_CTRL_OFFSET);
|
|
break;
|
|
/* 78M not recommend */
|
|
case 0x2:
|
|
CLRREG32(PWM_CLK_SRC_CTRL, 0x3 << (pwm_no * 2));
|
|
CLRREG32(PWM_CLK_SRC_CTRL, 0x3 << PWM_BCLK_SW_CTRL_OFFSET);
|
|
SETREG32(PWM_CLK_SRC_CTRL, 0x2 << (pwm_no * 2));
|
|
SETREG32(PWM_CLK_SRC_CTRL, 0x2 << PWM_BCLK_SW_CTRL_OFFSET);
|
|
break;
|
|
/* 66M, topckgen default */
|
|
case 0x3:
|
|
CLRREG32(PWM_CLK_SRC_CTRL, 0x3 << (pwm_no * 2));
|
|
CLRREG32(PWM_CLK_SRC_CTRL, 0x3 << PWM_BCLK_SW_CTRL_OFFSET);
|
|
SETREG32(PWM_CLK_SRC_CTRL, 0x3 << (pwm_no * 2));
|
|
SETREG32(PWM_CLK_SRC_CTRL, 0x3 << PWM_BCLK_SW_CTRL_OFFSET);
|
|
break;
|
|
default:
|
|
pr_info("PWM: invalid clk_src\n");
|
|
}
|
|
}
|
|
|
|
void mt_pwm_platform_init(void)
|
|
{
|
|
struct device_node *node;
|
|
|
|
node = of_find_compatible_node(NULL, NULL, "mediatek,infracfg_ao");
|
|
if (node) {
|
|
pwm_infracfg_base = of_iomap(node, 0);
|
|
pr_debug("PWM pwm_infracfg_base=0x%p\n", pwm_infracfg_base);
|
|
if (!pwm_infracfg_base)
|
|
pr_debug("PWM pwm_infracfg_base error!!\n");
|
|
}
|
|
}
|
|
|
|
int mt_get_pwm_clk_src(struct platform_device *pdev)
|
|
{
|
|
int i = 0;
|
|
|
|
for (i = PWM1_CLK; i < PWM_CLK_NUM; i++) {
|
|
pwm_clk[i] = devm_clk_get(&pdev->dev, pwm_clk_name[i]);
|
|
if (IS_ERR(pwm_clk[i])) {
|
|
pr_debug("cannot get %s clock\n", pwm_clk_name[i]);
|
|
return PTR_ERR(pwm_clk[i]);
|
|
}
|
|
pr_debug("[PWM] get %s clock, %p\n",
|
|
pwm_clk_name[i], pwm_clk[i]);
|
|
}
|
|
return 0;
|
|
}
|
|
|