422 lines
14 KiB
C
422 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 MediaTek Inc.
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*/
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#ifndef __MT_RTC_HW_H__
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#define __MT_RTC_HW_H__
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#include <mach/upmu_hw.h>
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extern unsigned int pmic_config_interface_nolock(unsigned int RegNum,
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unsigned int val, unsigned int MASK, unsigned int SHIFT);
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/* RTC registers */
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#define RTC_BBPU (PMIC_PWREN_ADDR)
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#define RTC_BBPU_PWREN \
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(PMIC_PWREN_MASK << PMIC_PWREN_SHIFT)
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#define RTC_BBPU_CLR \
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(PMIC_BBPU_CLR_MASK << PMIC_BBPU_CLR_SHIFT)
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#define RTC_BBPU_INIT \
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(PMIC_BBPU_INIT_MASK << PMIC_BBPU_INIT_SHIFT)
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#define RTC_BBPU_AUTO \
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(PMIC_AUTO_MASK << PMIC_AUTO_SHIFT)
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#define RTC_BBPU_CLRPKY \
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(PMIC_CLRPKY_MASK << PMIC_CLRPKY_SHIFT)
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#define RTC_BBPU_RELOAD \
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(PMIC_RELOAD_MASK << PMIC_RELOAD_SHIFT)
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#define RTC_BBPU_CBUSY \
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(PMIC_CBUSY_MASK << PMIC_CBUSY_SHIFT)
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#define RTC_BBPU_KEY \
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(0x43 << PMIC_KEY_BBPU_SHIFT)
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#define RTC_IRQ_STA (PMIC_ALSTA_ADDR)
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#define RTC_IRQ_STA_AL \
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(PMIC_ALSTA_MASK << PMIC_ALSTA_SHIFT)
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#define RTC_IRQ_STA_TC \
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(PMIC_TCSTA_MASK << PMIC_TCSTA_SHIFT)
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#define RTC_IRQ_STA_LP \
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(PMIC_LPSTA_MASK << PMIC_LPSTA_SHIFT)
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#define RTC_IRQ_EN (PMIC_AL_EN_ADDR)
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#define RTC_IRQ_EN_AL \
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(PMIC_AL_EN_MASK << PMIC_AL_EN_SHIFT)
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#define RTC_IRQ_EN_TC \
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(PMIC_TC_EN_MASK << PMIC_TC_EN_SHIFT)
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#define RTC_IRQ_EN_ONESHOT \
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(PMIC_ONESHOT_MASK << PMIC_ONESHOT_SHIFT)
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#define RTC_IRQ_EN_LP \
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(PMIC_LP_EN_MASK << PMIC_LP_EN_SHIFT)
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#define RTC_IRQ_EN_ONESHOT_AL \
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(RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
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#define RTC_CII_EN (PMIC_SECCII_ADDR)
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#define RTC_CII_SEC \
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(PMIC_SECCII_MASK << PMIC_SECCII_SHIFT)
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#define RTC_CII_MIN \
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(PMIC_MINCII_MASK << PMIC_MINCII_SHIFT)
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#define RTC_CII_HOU \
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(PMIC_HOUCII_MASK << PMIC_HOUCII_SHIFT)
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#define RTC_CII_DOM \
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(PMIC_DOMCII_MASK << PMIC_DOMCII_SHIFT)
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#define RTC_CII_DOW \
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(PMIC_DOWCII_MASK << PMIC_DOWCII_SHIFT)
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#define RTC_CII_MTH \
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(PMIC_MTHCII_MASK << PMIC_MTHCII_SHIFT)
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#define RTC_CII_YEA \
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(PMIC_YEACII_MASK << PMIC_YEACII_SHIFT)
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#define RTC_CII_1_2_SEC \
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(PMIC_SECCII_1_2_MASK << PMIC_SECCII_1_2_SHIFT)
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#define RTC_CII_1_4_SEC \
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(PMIC_SECCII_1_4_MASK << PMIC_SECCII_1_4_SHIFT)
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#define RTC_CII_1_8_SEC \
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(PMIC_SECCII_1_8_MASK << PMIC_SECCII_1_8_SHIFT)
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#define RTC_AL_MASK (PMIC_SEC_MSK_ADDR)
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#define RTC_AL_MASK_SEC \
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(PMIC_SEC_MSK_MASK << PMIC_SEC_MSK_SHIFT)
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#define RTC_AL_MASK_MIN \
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(PMIC_MIN_MSK_MASK << PMIC_MIN_MSK_SHIFT)
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#define RTC_AL_MASK_HOU \
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(PMIC_HOU_MSK_MASK << PMIC_HOU_MSK_SHIFT)
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#define RTC_AL_MASK_DOM \
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(PMIC_DOM_MSK_MASK << PMIC_DOM_MSK_SHIFT)
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#define RTC_AL_MASK_DOW \
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(PMIC_DOW_MSK_MASK << PMIC_DOW_MSK_SHIFT)
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#define RTC_AL_MASK_MTH \
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(PMIC_MTH_MSK_MASK << PMIC_MTH_MSK_SHIFT)
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#define RTC_AL_MASK_YEA \
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(PMIC_YEA_MSK_MASK << PMIC_YEA_MSK_SHIFT)
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#define RTC_TC_SEC (PMIC_TC_SECOND_ADDR)
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#define RTC_TC_MIN (PMIC_TC_MINUTE_ADDR)
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#define RTC_TC_HOU (PMIC_TC_HOUR_ADDR)
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#define RTC_TC_DOM (PMIC_TC_DOM_ADDR)
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#define RTC_TC_DOW (PMIC_TC_DOW_ADDR)
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#define RTC_TC_MTH (PMIC_TC_MONTH_ADDR)
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#define RTC_TC_MTH_MASK (PMIC_TC_MONTH_MASK)
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#define RTC_TC_YEA (PMIC_TC_YEAR_ADDR)
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#define RTC_AL_SEC (PMIC_AL_SECOND_ADDR)
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#define RTC_AL_SEC_MASK (PMIC_AL_SECOND_MASK)
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#define RTC_BBPU_AUTO_PDN_SEL \
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(PMIC_BBPU_AUTO_PDN_SEL_MASK << PMIC_BBPU_AUTO_PDN_SEL_SHIFT)
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#define RTC_BBPU_2SEC_CK_SEL \
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(PMIC_BBPU_2SEC_CK_SEL_MASK << PMIC_BBPU_2SEC_CK_SEL_SHIFT)
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#define RTC_BBPU_2SEC_EN \
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(PMIC_BBPU_2SEC_EN_MASK << PMIC_BBPU_2SEC_EN_SHIFT)
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#define RTC_BBPU_2SEC_MODE \
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(PMIC_BBPU_2SEC_MODE_MASK << PMIC_BBPU_2SEC_MODE_SHIFT)
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/* RTC mask include shift */
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#define RTC_BBPU_2SEC_MODE_MSK \
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(PMIC_BBPU_2SEC_MODE_MASK << PMIC_BBPU_2SEC_MODE_SHIFT)
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#define RTC_BBPU_2SEC_MODE_SHIFT (PMIC_BBPU_2SEC_MODE_SHIFT)
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#define RTC_BBPU_2SEC_STAT_CLEAR \
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(PMIC_BBPU_2SEC_STAT_CLEAR_MASK << PMIC_BBPU_2SEC_STAT_CLEAR_SHIFT)
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#define RTC_BBPU_2SEC_STAT_STA \
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(PMIC_BBPU_2SEC_STAT_STA_MASK << PMIC_BBPU_2SEC_STAT_STA_SHIFT)
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#define RTC_LPD_OPT_SHIFT (PMIC_RTC_LPD_OPT_SHIFT)
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#define RTC_LPD_OPT_MASK \
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(PMIC_RTC_LPD_OPT_MASK << PMIC_RTC_LPD_OPT_SHIFT)
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#define RTC_LPD_OPT_XOSC_AND_EOSC_LPD (0U << PMIC_RTC_LPD_OPT_SHIFT)
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#define RTC_LPD_OPT_EOSC_LPD (1U << PMIC_RTC_LPD_OPT_SHIFT)
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#define RTC_LPD_OPT_XOSC_LPD (2U << PMIC_RTC_LPD_OPT_SHIFT)
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#define RTC_LPD_OPT_F32K_CK_ALIVE (3U << PMIC_RTC_LPD_OPT_SHIFT)
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#define RTC_K_EOSC32_VTCXO_ON_SEL \
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(PMIC_K_EOSC32_VTCXO_ON_SEL_MASK << PMIC_K_EOSC32_VTCXO_ON_SEL_SHIFT)
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#define RTC_AL_MIN (PMIC_AL_MINUTE_ADDR)
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#define RTC_AL_MIN_MASK \
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(PMIC_AL_MINUTE_MASK << PMIC_AL_MINUTE_SHIFT)
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/*
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* RTC_NEW_SPARE0: RTC_AL_HOU bit0~4
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* bit 8 ~ 15 : For design used, can't be overwrited.
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*/
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#define RTC_AL_HOU (PMIC_AL_HOUR_ADDR)
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#define RTC_AL_HOU_MASK \
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(PMIC_AL_HOUR_MASK << PMIC_AL_HOUR_SHIFT)
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#define RTC_NEW_SPARE0 \
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(PMIC_NEW_SPARE0_MASK << PMIC_NEW_SPARE0_SHIFT)
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#define RTC_AL_HOU_FG_SHIFT 8
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#define RTC_AL_HOU_FG_MASK 0xff00
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/*
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* RTC_NEW_SPARE1: RTC_AL_DOM bit0~4
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* bit 8 ~ 15 : for 2 second reboot desing used,
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* can't be overwrited.
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*/
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#define RTC_AL_DOM (PMIC_AL_DOM_ADDR)
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#define RTC_AL_DOM_MASK \
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(PMIC_AL_DOM_MASK << PMIC_AL_DOM_SHIFT)
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#define RTC_NEW_SPARE1 \
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(PMIC_NEW_SPARE1_MASK << PMIC_NEW_SPARE1_SHIFT)
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#define RTC_SPAR_CONDITION (1U << 8) /* by uvlo */
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#define RTC_AUTOMATICALLY_SPAR (1U << 9) /* clear by sw */
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#define RTC_ALARM_CLEAR_METHOD (1U << 11) /* by sw */
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/*
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* RTC_NEW_SPARE2: RTC_AL_DOW bit0~2
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* bit 8 ~ 15 : reserved bits
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*/
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#define RTC_AL_DOW (PMIC_AL_DOW_ADDR)
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#define RTC_AL_DOW_MASK \
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(PMIC_AL_DOW_MASK << PMIC_AL_DOW_SHIFT)
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#define RTC_NEW_SPARE2 \
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(PMIC_NEW_SPARE2_MASK << PMIC_NEW_SPARE2_SHIFT)
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/*
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* RTC_NEW_SPARE3: RTC_AL_MTH bit0~3
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* bit 8 ~ 15 : Fuel Gauge
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*/
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#define RTC_AL_MTH (PMIC_AL_MONTH_ADDR)
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#define RTC_AL_MTH_MASK \
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(PMIC_AL_MONTH_MASK << PMIC_AL_MONTH_SHIFT)
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#define RTC_NEW_SPARE3 \
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(PMIC_NEW_SPARE3_MASK << PMIC_NEW_SPARE3_SHIFT)
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#define RTC_AL_MTH_FG_SHIFT 8
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#define RTC_AL_MTH_FG_MASK 0xff00
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#define RTC_AL_YEA (PMIC_AL_YEAR_ADDR)
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#define RTC_AL_YEA_MASK \
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(PMIC_AL_YEAR_MASK << PMIC_AL_YEAR_SHIFT)
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#define RTC_K_EOSC_RSV_0 (1U << 8)
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#define RTC_K_EOSC_RSV_1 (1U << 9)
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#define RTC_K_EOSC_RSV_2 (1U << 10)
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#define RTC_K_EOSC_RSV_3 (1U << 11)
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#define RTC_K_EOSC_RSV_4 (1U << 12)
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#define RTC_K_EOSC_RSV_5 (1U << 13)
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#define RTC_K_EOSC_RSV_6 (1U << 14)
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#define RTC_K_EOSC_RSV_7 (1U << 15)
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#define RTC_OSC32CON (PMIC_XOSCCALI_ADDR)
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#define RTC_OSC32CON_UNLOCK1 0x1a57
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#define RTC_OSC32CON_UNLOCK2 0x2b68
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/*
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*Default 4'b0111, 2nd step suggest to set to
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* 4'b0000 EOSC_CALI = charging cap calibration
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*/
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#define RTC_XOSCCALI_MASK \
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(PMIC_XOSCCALI_MASK << PMIC_XOSCCALI_SHIFT)
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/* 0 (32k crystal exist) 1 (32k crystal doesn't exist)*/
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#define RTC_XOSC32_ENB \
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(PMIC_RTC_XOSC32_ENB_MASK << PMIC_RTC_XOSC32_ENB_SHIFT)
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#define RTC_EMBCK_SEL_MODE \
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(PMIC_RTC_EMBCK_SEL_MODE_MASK << PMIC_RTC_EMBCK_SEL_MODE_SHIFT)
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#define RTC_EMBCK_SRC_SEL \
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(PMIC_RTC_EMBCK_SRC_SEL_MASK << PMIC_RTC_EMBCK_SRC_SEL_SHIFT)
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#define RTC_EMBCK_SEL_OPTION \
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(PMIC_RTC_EMBCK_SEL_OPTION_MASK << PMIC_RTC_EMBCK_SEL_OPTION_SHIFT)
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#define RTC_GPS_CKOUT_EN \
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(PMIC_RTC_GPS_CKOUT_EN_MASK << PMIC_RTC_GPS_CKOUT_EN_SHIFT)
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#define RTC_EOSC32_VCT_EN \
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(PMIC_RTC_EOSC32_VCT_EN_MASK << PMIC_RTC_EOSC32_VCT_EN_SHIFT)
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#define RTC_EOSC32_CHOP_EN \
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(PMIC_RTC_EOSC32_CHOP_EN_MASK << PMIC_RTC_EOSC32_CHOP_EN_SHIFT)
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/*
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* Keep RG_EOSC_RSV[0] to low for lower EOSC
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* leakage current hardware design change.
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*/
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#define RTC_GP_OSC32_CON \
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(2U << PMIC_RTC_GP_OSC32_CON_SHIFT)
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#define RTC_REG_XOSC32_ENB \
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(PMIC_RTC_REG_XOSC32_ENB_MASK << PMIC_RTC_REG_XOSC32_ENB_SHIFT)
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/* 0: emb_hw 1: emb_k_eosc_32 2:dcxo_ck 3: eosc32_ck*/
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#define RTC_EMBCK_SEL_HW \
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(0 << PMIC_RTC_EMBCK_SEL_MODE_SHIFT)
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#define RTC_EMBCK_SEL_K_EOSC \
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(1U << PMIC_RTC_EMBCK_SEL_MODE_SHIFT)
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#define RTC_EMBCK_SEL_DCXO \
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(2U << PMIC_RTC_EMBCK_SEL_MODE_SHIFT)
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#define RTC_EMBCK_SEL_EOSC \
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(3U << PMIC_RTC_EMBCK_SEL_MODE_SHIFT)
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#define OSC32CON_ANALOG_SETTING \
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(RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN | RTC_EOSC32_VCT_EN | \
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RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION | RTC_EMBCK_SEL_K_EOSC)
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#define RTC_XOSCCALI_START 0x0000
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#define RTC_XOSCCALI_END 0x001f
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#define RTC_POWERKEY1 (PMIC_RTC_POWERKEY1_ADDR)
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#define RTC_POWERKEY2 (PMIC_RTC_POWERKEY2_ADDR)
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#define RTC_POWERKEY1_KEY 0xa357
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#define RTC_POWERKEY2_KEY 0x67d2
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/*
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* RTC_PDN1:
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* bit 0 - 3 : Android bits
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* bit 4 - 5 : Recovery bits (0x10: factory data reset)
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* bit 6 : Bypass PWRKEY bit
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* bit 7 : Power-On Time bit
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* bit 8 : RTC_GPIO_USER_WIFI bit
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* bit 9 : RTC_GPIO_USER_GPS bit
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* bit 10 : RTC_GPIO_USER_BT bit
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* bit 11 : RTC_GPIO_USER_FM bit
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* bit 12 : RTC_GPIO_USER_PMIC bit
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* bit 13 : Fast Boot
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* bit 14 : Kernel Power Off Charging
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* bit 15 : Debug bit
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*/
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#define RTC_PDN1 (PMIC_RTC_PDN1_ADDR)
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#define RTC_PDN1_ANDROID_MASK 0x000f
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#define RTC_PDN1_RECOVERY_MASK 0x0030
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#define RTC_PDN1_FAC_RESET (1U << 4)
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#define RTC_PDN1_BYPASS_PWR (1U << 6)
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#define RTC_PDN1_PWRON_TIME (1U << 7)
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#define RTC_PDN1_GPIO_WIFI (1U << 8)
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#define RTC_PDN1_GPIO_GPS (1U << 9)
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#define RTC_PDN1_GPIO_BT (1U << 10)
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#define RTC_PDN1_GPIO_FM (1U << 11)
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#define RTC_PDN1_GPIO_PMIC (1U << 12)
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#define RTC_PDN1_FAST_BOOT (1U << 13)
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#define RTC_PDN1_KPOC (1U << 14)
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#define RTC_PDN1_DEBUG (1U << 15)
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#define RTC_GPIO_USER_MASK (RTC_PDN1_GPIO_WIFI | RTC_PDN1_GPIO_GPS\
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| RTC_PDN1_GPIO_BT | RTC_PDN1_GPIO_FM | RTC_PDN1_GPIO_PMIC)
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/*
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* RTC_PDN2:
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* bit 0 - 3 : MTH in power-on time
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* bit 4 : Power-On Alarm bit
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* bit 5 - 6 : UART bits
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* bit 7 : autoboot bit
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* bit 8 - 14: YEA in power-on time
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* bit 15 : Power-On Logo bit
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*/
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#define RTC_PDN2 (PMIC_RTC_PDN2_ADDR)
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#define RTC_PDN2_PWRON_MTH_MASK 0x000f
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#define RTC_PDN2_PWRON_MTH_SHIFT 0
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#define RTC_PDN2_PWRON_ALARM (1U << 4)
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#define RTC_PDN2_UART_MASK 0x0060
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#define RTC_PDN2_UART_SHIFT 5
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#define RTC_PDN2_PWRON_YEA_MASK 0x7f00
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#define RTC_PDN2_AUTOBOOT (1U << 7)
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#define RTC_PDN2_PWRON_YEA_SHIFT 8
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#define RTC_PDN2_PWRON_LOGO (1U << 15)
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/*
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* RTC_SPAR0:
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* bit 0 - 5 : SEC in power-on time
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* bit 6 : 32K less bit. True:with 32K, False:Without 32K
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* bit 7 - 15: reserved bits
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*/
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#define RTC_SPAR0 (PMIC_RTC_SPAR0_ADDR)
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#define RTC_SPAR0_PWRON_SEC_MASK 0x003f
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#define RTC_SPAR0_PWRON_SEC_SHIFT 0
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#define RTC_SPAR0_32K_LESS (1U << 6)
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#define RTC_SPAR0_LP_DET (1U << 7)
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/*
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* RTC_SPAR1:
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* bit 0 - 5 : MIN in power-on time
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* bit 6 - 10 : HOU in power-on time
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* bit 11 - 15: DOM in power-on time
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*/
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#define RTC_SPAR1 (PMIC_RTC_SPAR1_ADDR)
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#define RTC_SPAR1_PWRON_MIN_MASK 0x003f
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#define RTC_SPAR1_PWRON_MIN_SHIFT 0
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#define RTC_SPAR1_PWRON_HOU_MASK 0x07c0
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#define RTC_SPAR1_PWRON_HOU_SHIFT 6
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#define RTC_SPAR1_PWRON_DOM_MASK 0xf800
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#define RTC_SPAR1_PWRON_DOM_SHIFT 11
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#define RTC_PROT (PMIC_RTC_PROT_ADDR)
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#define RTC_PROT_UNLOCK1 0x586a
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#define RTC_PROT_UNLOCK2 0x9136
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#define RTC_DIFF (PMIC_RTC_DIFF_ADDR)
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#define RTC_POWER_DETECTED \
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(PMIC_POWER_DETECTED_MASK << PMIC_POWER_DETECTED_SHIFT)
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#define RTC_K_EOSC32_RSV \
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(PMIC_K_EOSC32_RSV_MASK << PMIC_K_EOSC32_RSV_SHIFT)
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#define RTC_CALI_RD_SEL_SHIFT (PMIC_CALI_RD_SEL_SHIFT)
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#define RTC_CALI_RD_SEL \
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(PMIC_CALI_RD_SEL_MASK << PMIC_CALI_RD_SEL_SHIFT)
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#define RTC_CALI (PMIC_RTC_CALI_ADDR)
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#define RTC_CALI_MASK \
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(PMIC_RTC_CALI_MASK << PMIC_RTC_CALI_SHIFT)
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#define RTC_CALI_WR_SEL \
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(PMIC_CALI_WR_SEL_MASK << PMIC_CALI_WR_SEL_SHIFT)
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#define RTC_CALI_WR_SEL_SHIFT (PMIC_CALI_WR_SEL_SHIFT)
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#define RTC_K_EOSC32_OVERFLOW \
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(PMIC_K_EOSC32_OVERFLOW_MASK << PMIC_K_EOSC32_OVERFLOW_SHIFT)
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#define RTC_WRTGR (PMIC_WRTGR_ADDR)
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#define RTC_CON \
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(PMIC_VBAT_LPSTA_RAW_ADDR)
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#define RTC_VBAT_LPSTA_RAW \
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(PMIC_VBAT_LPSTA_RAW_MASK << PMIC_VBAT_LPSTA_RAW_SHIFT)
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#define RTC_EOSC32_LPEN \
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(PMIC_EOSC32_LPEN_MASK << PMIC_EOSC32_LPEN_SHIFT)
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#define RTC_XOSC32_LPEN \
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(PMIC_XOSC32_LPEN_MASK << PMIC_XOSC32_LPEN_SHIFT)
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#define RTC_CON_LPRST \
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(PMIC_LPRST_MASK << PMIC_LPRST_SHIFT)
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#define RTC_CON_CDBO \
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(PMIC_CDBO_MASK << PMIC_CDBO_SHIFT)
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#define RTC_CON_F32KOB \
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(PMIC_F32KOB_MASK << PMIC_F32KOB_SHIFT) /* 0: RTC_GPIO exports 32K */
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#define RTC_CON_GPO \
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(PMIC_GPO_MASK << PMIC_GPO_SHIFT)
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/* 1: GPO mode, 0: GPI mode */
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#define RTC_CON_GOE \
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(PMIC_GOE_MASK << PMIC_GOE_SHIFT)
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#define RTC_CON_GSR \
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(PMIC_GSR_MASK << PMIC_GSR_SHIFT)
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#define RTC_CON_GSMT \
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(PMIC_GSMT_MASK << PMIC_GSMT_SHIFT)
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#define RTC_CON_GPEN \
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(PMIC_GPEN_MASK << PMIC_GPEN_SHIFT)
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#define RTC_CON_GPU \
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(PMIC_GPU_MASK << PMIC_GPU_SHIFT)
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#define RTC_CON_GE4 \
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(PMIC_GE4_MASK << PMIC_GE4_SHIFT)
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#define RTC_CON_GE8 \
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(PMIC_GE8_MASK << PMIC_GE8_SHIFT)
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#define RTC_CON_GPI \
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(PMIC_GPI_MASK << PMIC_GPI_SHIFT)
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#define RTC_CON_LPSTA_RAW \
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(PMIC_LPSTA_RAW_MASK << PMIC_LPSTA_RAW_SHIFT) /* 32K was stopped */
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#define RTC_INT_CNT (PMIC_RTC_INT_CNT_ADDR)
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/* power on alarm time setting */
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#define RTC_PWRON_YEA RTC_PDN2
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#define RTC_PWRON_YEA_MASK 0x7f00
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#define RTC_PWRON_YEA_SHIFT 8
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#define RTC_PWRON_MTH RTC_PDN2
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#define RTC_PWRON_MTH_MASK 0x000f
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#define RTC_PWRON_MTH_SHIFT 0
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#define RTC_PWRON_SEC RTC_SPAR0
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#define RTC_PWRON_SEC_MASK 0x003f
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#define RTC_PWRON_SEC_SHIFT 0
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#define RTC_PWRON_MIN RTC_SPAR1
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#define RTC_PWRON_MIN_MASK 0x003f
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#define RTC_PWRON_MIN_SHIFT 0
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#define RTC_PWRON_HOU RTC_SPAR1
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#define RTC_PWRON_HOU_MASK 0x07c0
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#define RTC_PWRON_HOU_SHIFT 6
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#define RTC_PWRON_DOM RTC_SPAR1
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#define RTC_PWRON_DOM_MASK 0xf800
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#define RTC_PWRON_DOM_SHIFT 11
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extern u16 rtc_spare_reg[][3];
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#endif /* __MT_RTC_HW_H__ */
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