237 lines
8.8 KiB
C
237 lines
8.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 MediaTek Inc.
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*/
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#ifndef __SMI_CONF_H__
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#define __SMI_CONF_H__
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#include <soc/mediatek/smi.h>
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#include "smi_hw.h"
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#include "../smi_reg.h"
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#include "../smi_conf_dbg.h"
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#define SMI_SCEN_NUM (1)
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#define SMI_ESL_INIT (0)
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#define SMI_ESL_VPWFD (SMI_ESL_INIT)
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#define SMI_ESL_VR4K (SMI_ESL_INIT)
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#define SMI_ESL_ICFP (SMI_ESL_INIT)
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static u32 smi_scen_map[SMI_BWC_SCEN_CNT] = {
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SMI_ESL_INIT, SMI_ESL_INIT, SMI_ESL_INIT,
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SMI_ESL_INIT, SMI_ESL_INIT, SMI_ESL_INIT,
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SMI_ESL_VPWFD, SMI_ESL_VPWFD, SMI_ESL_VPWFD,
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SMI_ESL_VPWFD, SMI_ESL_VPWFD,
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SMI_ESL_VR4K, SMI_ESL_VR4K, SMI_ESL_VR4K, SMI_ESL_VR4K,
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SMI_ESL_ICFP, SMI_ESL_ICFP, SMI_ESL_ICFP, SMI_ESL_INIT
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};
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static u32 smi_larb_cmd_gp_en_port[SMI_LARB_NUM][2] = {
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{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},
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};
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static u32 smi_larb_bw_thrt_en_port[SMI_LARB_NUM][2] = { /* non-HRT */
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{0, 0}, {5, SMI_LARB1_PORT_NUM}, {0, SMI_LARB2_PORT_NUM},
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{0, SMI_LARB3_PORT_NUM}, {0, 0}, {0, SMI_LARB5_PORT_NUM},
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{0, 0}, {0, 0},
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};
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/* conf */
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#define SMI_LARB0_CONF_NUM (11)
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struct mtk_smi_pair smi_larb0_conf_pair[SMI_LARB0_CONF_NUM] = {
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{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},
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{SMI_LARB_WRR_PORT(0), 0xb}, {SMI_LARB_WRR_PORT(1), 0xb},
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{SMI_LARB_WRR_PORT(2), 0xb}, {SMI_LARB_WRR_PORT(3), 0x5},
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{SMI_LARB_WRR_PORT(4), 0x5}, {SMI_LARB_WRR_PORT(5), 0xb},
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{SMI_LARB_WRR_PORT(6), 0xb}, {SMI_LARB_WRR_PORT(7), 0xb},
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{SMI_LARB_WRR_PORT(8), 0xb},
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};
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#define SMI_LARB1_CONF_NUM (16)
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struct mtk_smi_pair smi_larb1_conf_pair[SMI_LARB1_CONF_NUM] = {
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{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},
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{SMI_LARB_WRR_PORT(0), 0xb}, {SMI_LARB_WRR_PORT(1), 0xb},
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{SMI_LARB_WRR_PORT(2), 0x5}, {SMI_LARB_WRR_PORT(3), 0x5},
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{SMI_LARB_WRR_PORT(4), 0xb}, {SMI_LARB_WRR_PORT(5), 0x1},
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{SMI_LARB_WRR_PORT(6), 0x1}, {SMI_LARB_WRR_PORT(7), 0x1},
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{SMI_LARB_WRR_PORT(8), 0x1}, {SMI_LARB_WRR_PORT(9), 0x1},
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{SMI_LARB_WRR_PORT(10), 0x1}, {SMI_LARB_WRR_PORT(11), 0x1},
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{SMI_LARB_WRR_PORT(12), 0x1}, {SMI_LARB_WRR_PORT(13), 0x4},
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};
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#define SMI_LARB2_CONF_NUM (2)
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struct mtk_smi_pair smi_larb2_conf_pair[SMI_LARB2_CONF_NUM] = {
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{SMI_LARB_CMD_THRT_CON, 0x300256}, {SMI_LARB_SW_FLAG, 0x1},
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};
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#define SMI_LARB3_CONF_NUM (2)
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struct mtk_smi_pair smi_larb3_conf_pair[SMI_LARB3_CONF_NUM] = {
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{SMI_LARB_CMD_THRT_CON, 0x370256}, {SMI_LARB_SW_FLAG, 0x1},
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};
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#define SMI_COMM_CONF_NUM (6)
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struct mtk_smi_pair smi_comm_conf_pair[SMI_COMM_CONF_NUM] = {
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{SMI_L1LEN, 0xb}, {SMI_M4U_TH, 0xe100e10}, {SMI_FIFO_TH1, 0x506090a},
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{SMI_FIFO_TH2, 0x506090a}, {SMI_DCM, 0x4f1}, {SMI_DUMMY, 0x1},
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};
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u32 smi_conf_pair_num[SMI_LARB_NUM + 1] = {
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SMI_LARB0_CONF_NUM, SMI_LARB1_CONF_NUM, SMI_LARB2_CONF_NUM,
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SMI_LARB3_CONF_NUM, SMI_LARB2_CONF_NUM, SMI_LARB2_CONF_NUM,
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SMI_LARB3_CONF_NUM, SMI_LARB3_CONF_NUM,
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SMI_COMM_CONF_NUM,
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};
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struct mtk_smi_pair *smi_conf_pair[SMI_LARB_NUM + 1] = {
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smi_larb0_conf_pair, smi_larb1_conf_pair, smi_larb2_conf_pair,
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smi_larb3_conf_pair, smi_larb2_conf_pair, smi_larb2_conf_pair,
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smi_larb3_conf_pair, smi_larb3_conf_pair,
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smi_comm_conf_pair,
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};
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/* scen: INIT */
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struct mtk_smi_pair smi_larb0_init_pair[SMI_LARB0_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x2}, {SMI_LARB_OSTDL_PORT(1), 0x2},
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{SMI_LARB_OSTDL_PORT(2), 0x1}, {SMI_LARB_OSTDL_PORT(3), 0x1f},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0xa}, {SMI_LARB_OSTDL_PORT(7), 0xa},
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{SMI_LARB_OSTDL_PORT(8), 0x28},
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};
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struct mtk_smi_pair smi_larb1_init_pair[SMI_LARB1_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x2}, {SMI_LARB_OSTDL_PORT(1), 0x1},
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{SMI_LARB_OSTDL_PORT(2), 0x1c}, {SMI_LARB_OSTDL_PORT(3), 0x1c},
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{SMI_LARB_OSTDL_PORT(4), 0xa}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x1}, {SMI_LARB_OSTDL_PORT(7), 0xd},
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{SMI_LARB_OSTDL_PORT(8), 0xd}, {SMI_LARB_OSTDL_PORT(9), 0xe},
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{SMI_LARB_OSTDL_PORT(10), 0x1}, {SMI_LARB_OSTDL_PORT(11), 0xe},
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{SMI_LARB_OSTDL_PORT(12), 0x1}, {SMI_LARB_OSTDL_PORT(13), 0x28},
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};
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struct mtk_smi_pair smi_larb2_init_pair[SMI_LARB2_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x18}, {SMI_LARB_OSTDL_PORT(1), 0x1},
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{SMI_LARB_OSTDL_PORT(2), 0x8}, {SMI_LARB_OSTDL_PORT(3), 0x1},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x1}, {SMI_LARB_OSTDL_PORT(7), 0x1},
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{SMI_LARB_OSTDL_PORT(8), 0x1}, {SMI_LARB_OSTDL_PORT(9), 0x2},
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{SMI_LARB_OSTDL_PORT(10), 0x1}, {SMI_LARB_OSTDL_PORT(11), 0x1},
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};
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struct mtk_smi_pair smi_larb3_init_pair[SMI_LARB3_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1}, {SMI_LARB_OSTDL_PORT(1), 0x3},
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{SMI_LARB_OSTDL_PORT(2), 0x2}, {SMI_LARB_OSTDL_PORT(3), 0x1},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x1}, {SMI_LARB_OSTDL_PORT(7), 0x4},
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{SMI_LARB_OSTDL_PORT(8), 0x2}, {SMI_LARB_OSTDL_PORT(9), 0x1},
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{SMI_LARB_OSTDL_PORT(10), 0x4}, {SMI_LARB_OSTDL_PORT(11), 0x1},
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{SMI_LARB_OSTDL_PORT(12), 0x1}, {SMI_LARB_OSTDL_PORT(13), 0x1},
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{SMI_LARB_OSTDL_PORT(14), 0x1}, {SMI_LARB_OSTDL_PORT(15), 0x4},
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{SMI_LARB_OSTDL_PORT(16), 0xb}, {SMI_LARB_OSTDL_PORT(17), 0x13},
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{SMI_LARB_OSTDL_PORT(18), 0x14},
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};
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struct mtk_smi_pair smi_larb4_init_pair[SMI_LARB4_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1}, {SMI_LARB_OSTDL_PORT(1), 0x1},
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{SMI_LARB_OSTDL_PORT(2), 0x1},
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};
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struct mtk_smi_pair smi_larb5_init_pair[SMI_LARB5_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0xc}, {SMI_LARB_OSTDL_PORT(1), 0x1},
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{SMI_LARB_OSTDL_PORT(2), 0x4}, {SMI_LARB_OSTDL_PORT(3), 0x4},
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{SMI_LARB_OSTDL_PORT(4), 0x1}, {SMI_LARB_OSTDL_PORT(5), 0x2},
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{SMI_LARB_OSTDL_PORT(6), 0x2}, {SMI_LARB_OSTDL_PORT(7), 0x6},
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{SMI_LARB_OSTDL_PORT(8), 0x1}, {SMI_LARB_OSTDL_PORT(9), 0x9},
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{SMI_LARB_OSTDL_PORT(10), 0x2}, {SMI_LARB_OSTDL_PORT(11), 0x2},
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{SMI_LARB_OSTDL_PORT(12), 0x2}, {SMI_LARB_OSTDL_PORT(13), 0x1},
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{SMI_LARB_OSTDL_PORT(14), 0x6}, {SMI_LARB_OSTDL_PORT(15), 0x9},
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{SMI_LARB_OSTDL_PORT(16), 0x1}, {SMI_LARB_OSTDL_PORT(17), 0x1},
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{SMI_LARB_OSTDL_PORT(18), 0x6}, {SMI_LARB_OSTDL_PORT(19), 0x4},
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{SMI_LARB_OSTDL_PORT(20), 0x4}, {SMI_LARB_OSTDL_PORT(21), 0x1},
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{SMI_LARB_OSTDL_PORT(22), 0x1}, {SMI_LARB_OSTDL_PORT(23), 0x1},
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{SMI_LARB_OSTDL_PORT(24), 0x1}, {SMI_LARB_OSTDL_PORT(25), 0x2},
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};
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struct mtk_smi_pair smi_larb6_init_pair[SMI_LARB6_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1f}, {SMI_LARB_OSTDL_PORT(1), 0x14},
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{SMI_LARB_OSTDL_PORT(2), 0x2}, {SMI_LARB_OSTDL_PORT(3), 0x2},
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{SMI_LARB_OSTDL_PORT(4), 0x2}, {SMI_LARB_OSTDL_PORT(5), 0x1},
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{SMI_LARB_OSTDL_PORT(6), 0x16}, {SMI_LARB_OSTDL_PORT(7), 0x8},
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{SMI_LARB_OSTDL_PORT(8), 0x2}, {SMI_LARB_OSTDL_PORT(9), 0x2},
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{SMI_LARB_OSTDL_PORT(10), 0x2}, {SMI_LARB_OSTDL_PORT(11), 0x1},
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{SMI_LARB_OSTDL_PORT(12), 0xa}, {SMI_LARB_OSTDL_PORT(13), 0xa},
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{SMI_LARB_OSTDL_PORT(14), 0x4}, {SMI_LARB_OSTDL_PORT(15), 0x2},
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{SMI_LARB_OSTDL_PORT(16), 0x2}, {SMI_LARB_OSTDL_PORT(17), 0x2},
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{SMI_LARB_OSTDL_PORT(18), 0x2}, {SMI_LARB_OSTDL_PORT(19), 0x2},
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{SMI_LARB_OSTDL_PORT(20), 0x2}, {SMI_LARB_OSTDL_PORT(21), 0x2},
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{SMI_LARB_OSTDL_PORT(22), 0x2}, {SMI_LARB_OSTDL_PORT(23), 0x2},
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{SMI_LARB_OSTDL_PORT(24), 0x2}, {SMI_LARB_OSTDL_PORT(25), 0x1},
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{SMI_LARB_OSTDL_PORT(26), 0x1}, {SMI_LARB_OSTDL_PORT(27), 0x1},
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{SMI_LARB_OSTDL_PORT(28), 0x1}, {SMI_LARB_OSTDL_PORT(29), 0x1},
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{SMI_LARB_OSTDL_PORT(30), 0x1},
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};
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struct mtk_smi_pair smi_larb7_init_pair[SMI_LARB7_PORT_NUM] = {
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{SMI_LARB_OSTDL_PORT(0), 0x1f}, {SMI_LARB_OSTDL_PORT(1), 0x14},
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{SMI_LARB_OSTDL_PORT(2), 0x1f}, {SMI_LARB_OSTDL_PORT(3), 0x1f},
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{SMI_LARB_OSTDL_PORT(4), 0x14},
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};
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struct mtk_smi_pair smi_comm_init_pair[SMI_LARB_NUM + 1] = {
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{SMI_L1ARB(0), 0x0}, {SMI_L1ARB(1), 0x0}, {SMI_L1ARB(2), 0x0},
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{SMI_L1ARB(3), 0x0}, {SMI_L1ARB(4), 0x0}, {SMI_L1ARB(5), 0x0},
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{SMI_L1ARB(6), 0x0}, {SMI_L1ARB(7), 0x0},
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};
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/* scen: ALL */
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struct mtk_smi_pair *smi_larb0_scen_pair[SMI_SCEN_NUM] = {
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smi_larb0_init_pair,
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};
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struct mtk_smi_pair *smi_larb1_scen_pair[SMI_SCEN_NUM] = {
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smi_larb1_init_pair,
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};
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struct mtk_smi_pair *smi_larb2_scen_pair[SMI_SCEN_NUM] = {
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smi_larb2_init_pair,
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};
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struct mtk_smi_pair *smi_larb3_scen_pair[SMI_SCEN_NUM] = {
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smi_larb3_init_pair,
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};
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struct mtk_smi_pair *smi_larb4_scen_pair[SMI_SCEN_NUM] = {
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smi_larb4_init_pair,
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};
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struct mtk_smi_pair *smi_larb5_scen_pair[SMI_SCEN_NUM] = {
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smi_larb5_init_pair,
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};
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struct mtk_smi_pair *smi_larb6_scen_pair[SMI_SCEN_NUM] = {
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smi_larb6_init_pair,
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};
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struct mtk_smi_pair *smi_larb7_scen_pair[SMI_SCEN_NUM] = {
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smi_larb7_init_pair,
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};
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struct mtk_smi_pair *smi_comm_scen_pair[SMI_SCEN_NUM] = {
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smi_comm_init_pair,
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};
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u32 smi_scen_pair_num[SMI_LARB_NUM + 1] = {
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SMI_LARB0_PORT_NUM, SMI_LARB1_PORT_NUM, SMI_LARB2_PORT_NUM,
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SMI_LARB3_PORT_NUM, SMI_LARB4_PORT_NUM, SMI_LARB5_PORT_NUM,
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SMI_LARB6_PORT_NUM, SMI_LARB7_PORT_NUM,
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SMI_COMM_MASTER_NUM,
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};
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struct mtk_smi_pair **smi_scen_pair[SMI_LARB_NUM + 1] = {
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smi_larb0_scen_pair, smi_larb1_scen_pair, smi_larb2_scen_pair,
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smi_larb3_scen_pair, smi_larb4_scen_pair, smi_larb5_scen_pair,
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smi_larb6_scen_pair, smi_larb7_scen_pair,
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smi_comm_scen_pair,
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};
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#endif
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