134 lines
5.1 KiB
C
134 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __SSPM_IPI_DEFINE_H__
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#define __SSPM_IPI_DEFINE_H__
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/* definition of slot size for send PINs */
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#define PINS_SIZE_PLATFORM 3 /* the following will use mbox 0 */
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#define PINS_SIZE_CPU_DVFS 4
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#define PINS_SIZE_QOS 4
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#define PINS_SIZE_TST1 4
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#define PINS_SIZE_FHCTL 9
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/* ============================================================ */
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#define PINS_SIZE_MCDI 2 /* the following will use mbox 1 */
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#define PINS_SIZE_SPM_SUSPEND 8
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#define PINS_SIZE_PMIC 5
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#define PINS_SIZE_PPM 7
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#define PINS_SIZE_THERMAL 4
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#define PINS_SIZE_UPOWER 4
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#define PINS_SIZE_UNUSED 0
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/* ============================================================ */
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/* definition of slot offset for PINs */
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#define PINS_OFFSET_PLATFORM 0 /* the following will use mbox 0 */
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#define PINS_OFFSET_CPU_DVFS (PINS_OFFSET_PLATFORM + PINS_SIZE_PLATFORM)
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#define PINS_OFFSET_QOS (PINS_OFFSET_CPU_DVFS + PINS_SIZE_CPU_DVFS)
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#define PINS_OFFSET_TST1 (PINS_OFFSET_QOS + PINS_SIZE_QOS)
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#define PINS_OFFSET_FHCTL (PINS_OFFSET_TST1 + PINS_SIZE_TST1)
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#define PINS_MBOX0_USED (PINS_OFFSET_FHCTL + PINS_SIZE_FHCTL)
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#if (PINS_MBOX0_USED > IPI_MBOX0_SLOTS)
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#error "MBOX0 cannot hold all pin definitions"
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#endif
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/* ============================================================ */
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#define PINS_OFFSET_MCDI 0 /* the following will use mbox 1 */
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#define PINS_OFFSET_SPM_SUSPEND (PINS_OFFSET_MCDI + PINS_SIZE_MCDI)
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#define PINS_OFFSET_PMIC (PINS_OFFSET_SPM_SUSPEND + \
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PINS_SIZE_SPM_SUSPEND)
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#define PINS_OFFSET_PPM (PINS_OFFSET_PMIC + PINS_SIZE_PMIC)
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#define PINS_OFFSET_THERMAL (PINS_OFFSET_PPM + PINS_SIZE_PPM)
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#define PINS_OFFSET_UPOWER (PINS_OFFSET_THERMAL + PINS_SIZE_THERMAL)
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#define PINS_OFFSET_UNUSED (PINS_OFFSET_UPOWER + PINS_SIZE_UPOWER)
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#define PINS_MBOX1_USED (PINS_OFFSET_UNUSED + PINS_SIZE_UNUSED)
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#if (PINS_MBOX1_USED > IPI_MBOX1_SLOTS)
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#error "MBOX1 cannot hold all pin definitions"
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#endif
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/* ============================================================ */
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/* definition of slot size for received PINs */
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#define PINR_SIZE_PLATFORM 3 /* the following will use mbox 2 */
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#define PINR_SIZE_CPU_DVFS 4
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#define PINR_SIZE_QOS 4
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#define PINR_SIZE_TST1 4
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/* definition of slot offset for PINs */
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#define PINR_OFFSET_PLATFORM 0 /* the following will use mbox 2 */
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#define PINR_OFFSET_CPU_DVFS (PINR_OFFSET_PLATFORM + PINR_SIZE_PLATFORM)
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#define PINR_OFFSET_QOS (PINR_OFFSET_CPU_DVFS + PINR_SIZE_CPU_DVFS)
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#define PINR_OFFSET_TST1 (PINR_OFFSET_QOS + PINR_SIZE_QOS)
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#define PINR_MBOX2_USED (PINR_OFFSET_TST1 + PINR_SIZE_TST1)
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#if (PINR_MBOX2_USED > IPI_MBOX2_SLOTS)
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#error "MBOX2 cannot hold all pin definitions"
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#endif
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/* mutex_send, sema_ack, mbox, slot, size,
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* shared, retdata, lock, share_grp, polling, unused
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*/
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struct _pin_send mt6765_send_pintable[] = {
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{{{0} }, {0}, 0, PINS_OFFSET_PLATFORM, PINS_SIZE_PLATFORM,
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0, 1, 0, 0, 0, 0},
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{{{0} }, {0}, 0, PINS_OFFSET_CPU_DVFS, PINS_SIZE_CPU_DVFS,
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0, 1, 1, 1, 0, 0},
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{{{0} }, {0}, 0, PINS_OFFSET_QOS, PINS_SIZE_QOS,
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0, 1, 1, 1, 0, 0},
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{{{0} }, {0}, 0, PINS_OFFSET_TST1, PINS_SIZE_TST1,
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0, 1, 0, 0, 0, 0},
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{{{0} }, {0}, 0, PINS_OFFSET_FHCTL, PINS_SIZE_FHCTL,
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0, 1, 1, 1, 0, 0},
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/*====================================================================*/
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{{{0} }, {0}, 1, PINS_OFFSET_MCDI, PINS_SIZE_MCDI,
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1, 1, 1, 1, 0, 0},
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{{{0} }, {0}, 1, PINS_OFFSET_SPM_SUSPEND, PINS_SIZE_SPM_SUSPEND,
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1, 1, 1, 1, 0, 0},
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{{{0} }, {0}, 1, PINS_OFFSET_PMIC, PINS_SIZE_PMIC,
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0, 1, 1, 1, 0, 0},
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{{{0} }, {0}, 1, PINS_OFFSET_PPM, PINS_SIZE_PPM,
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0, 1, 1, 1, 0, 0},
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{{{0} }, {0}, 1, PINS_OFFSET_THERMAL, PINS_SIZE_THERMAL,
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0, 1, 0, 0, 0, 0},
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{{{0} }, {0}, 1, PINS_OFFSET_UPOWER, PINS_SIZE_UPOWER,
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0, 1, 1, 1, 0, 0},
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{{{0} }, {0}, 0, PINS_OFFSET_UNUSED, PINS_SIZE_UNUSED,
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0, 0, 0, 0, 0, 0},
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/*====================================================================*/
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};
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#define MT6765_TOTAL_SEND_PIN \
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(sizeof(mt6765_send_pintable)/sizeof(struct _pin_send))
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/* act, mbox, slot, size, shared, retdata, lock, share_grp, unused */
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struct _pin_recv mt6765_recv_pintable[] = {
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{NULL, 2, PINR_OFFSET_PLATFORM, PINR_SIZE_PLATFORM, 0, 1, 0, 0, 0},
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{NULL, 2, PINR_OFFSET_CPU_DVFS, PINR_SIZE_CPU_DVFS, 0, 1, 0, 0, 0},
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{NULL, 2, PINR_OFFSET_QOS, PINR_SIZE_QOS, 0, 1, 0, 0, 0},
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{NULL, 2, PINR_OFFSET_TST1, PINR_SIZE_TST1, 0, 1, 0, 0, 0},
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};
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#define MT6765_TOTAL_RECV_PIN \
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(sizeof(mt6765_recv_pintable)/sizeof(struct _pin_recv))
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/* info for all mbox: start, end, used_slot, mode, unused */
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struct _mbox_info mt6765_mbox_table[IPI_MBOX_TOTAL] = {
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{0, 4, PINS_MBOX0_USED, 2, 0}, /* mbox 0 for send */
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{5, 10, PINS_MBOX1_USED, 2, 0}, /* mbox 1 for send */
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{0, 3, PINR_MBOX2_USED, 1, 0}, /* mbox 2 for recv */
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{0, 0, 0, 0, 0}, /* mbox 3 */
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};
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char *mt6765_pin_name[IPI_ID_TOTAL] = {
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"PLATFORM",
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"CPU_DVFS",
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"QOS",
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"TST1",
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"FHCTL",
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"MCDI",
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"SPM_SUSPEND",
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"PMIC",
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"PPM",
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"Thermal",
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"UPower",
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"UN_USED",
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};
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#endif /* __SSPM_IPI_DEFINE_H__ */
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