232 lines
5.8 KiB
C
232 lines
5.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT6763_THERMAL_H__
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#define __MT6763_THERMAL_H__
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#if IS_ENABLED(CONFIG_MTK_GPU_SUPPORT)
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#include "mtk_gpufreq.h"
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#endif
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/*=============================================================
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* LVTS SW Configs
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*=============================================================
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*/
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#define CFG_THERM_LVTS (0)
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#if CFG_THERM_LVTS
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#define CFG_LVTS_DOMINATOR (1)
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#define LVTS_THERMAL_CONTROLLER_HW_FILTER (1) /* 1, 2, 4, 8, 16 */
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#else
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#define CFG_LVTS_DOMINATOR (0)
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#define LVTS_THERMAL_CONTROLLER_HW_FILTER (0)
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#endif
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/* public thermal sensor enum */
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enum thermal_sensor {
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TS_MCU0 = 0, /* TSMCU0 */
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TS_MCU1, /* TSMCU1 */
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TS_MCU2, /* TSMCU2 */
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TS_MCU3, /* TSMCU3 */
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TS_MCU4, /* TSMCU4 */
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TS_MCU5, /* TSMCU5 */
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TS_MCU6, /* TSMCU6 */
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TS_MCU7, /* TSMCU7 */
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TS_MCU8, /* TSMCU8 */
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TS_MCU9, /* TSMCU9 */
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#if CFG_THERM_LVTS
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TS_LVTS1_0, /* LVTS1-0 */
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TS_LVTS1_1, /* LVTS1-1 */
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TS_LVTS2_0, /* LVTS2-0 */
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TS_LVTS2_1, /* LVTS2-1 */
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TS_LVTS2_2, /* LVTS2-2 */
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TS_LVTS3_0, /* LVTS3-0 */
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TS_LVTS3_1, /* LVTS3-1 */
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TS_LVTS4_0, /* LVTS4-0 */
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TS_LVTS4_1, /* LVTS4-1 */
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TS_LVTS9_0, /* LVTS9-0 */
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#endif
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TS_ABB, /* ABB */
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TS_ENUM_MAX,
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};
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enum thermal_bank_name {
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THERMAL_BANK0 = 0,
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THERMAL_BANK1,
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THERMAL_BANK2,
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THERMAL_BANK3,
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THERMAL_BANK4,
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THERMAL_BANK5,
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THERMAL_BANK6,
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THERMAL_BANK7,
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THERMAL_BANK_NUM
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};
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struct TS_PTPOD {
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unsigned int ts_MTS;
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unsigned int ts_BTS;
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};
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#if !IS_ENABLED(CONFIG_MTK_GPU_SUPPORT)
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struct mt_gpufreq_power_table_info {
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unsigned int gpufreq_khz;
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unsigned int gpufreq_volt;
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unsigned int gpufreq_power;
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};
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#endif
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extern int mtktscpu_limited_dmips;
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extern int tscpu_get_temperature_range(void);
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/* Valid if it returns 1, invalid if it returns 0. */
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extern int tscpu_is_temp_valid(void);
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extern void get_thermal_slope_intercept(
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struct TS_PTPOD *ts_info, enum thermal_bank_name ts_bank);
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#if CFG_THERM_LVTS
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extern void get_lvts_slope_intercept(
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struct TS_PTPOD *ts_info, enum thermal_bank_name ts_bank);
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#endif
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extern void set_taklking_flag(bool flag);
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extern int tscpu_get_cpu_temp(void);
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extern int tscpu_get_temp_by_bank(enum thermal_bank_name ts_bank);
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#define THERMAL_WRAP_WR32(val, addr) \
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mt_reg_sync_writel((val), ((void *)addr))
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extern int get_immediate_cpuL_wrap(void);
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extern int get_immediate_cpuB_wrap(void);
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extern int get_immediate_mcucci_wrap(void);
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extern int get_immediate_gpu_wrap(void);
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extern int get_immediate_mdla_wrap(void);
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extern int get_immediate_vpu_wrap(void);
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extern int get_immediate_top_wrap(void);
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extern int get_immediate_md_wrap(void);
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/* Added for DLPT. */
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extern int tscpu_get_min_cpu_pwr(void);
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extern int tscpu_get_min_gpu_pwr(void);
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extern int tscpu_get_min_vpu_pwr(void);
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extern int tscpu_get_min_mdla_pwr(void);
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/* Five thermal sensors. */
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enum mtk_thermal_sensor_cpu_id_met {
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MTK_THERMAL_SENSOR_TS0 = 0,
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MTK_THERMAL_SENSOR_TS1,
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MTK_THERMAL_SENSOR_TS2,
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MTK_THERMAL_SENSOR_TS3,
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MTK_THERMAL_SENSOR_TS4,
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MTK_THERMAL_SENSOR_TS5,
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MTK_THERMAL_SENSOR_TS6,
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MTK_THERMAL_SENSOR_TS7,
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MTK_THERMAL_SENSOR_TS8,
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MTK_THERMAL_SENSOR_TS9,
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#if CFG_THERM_LVTS
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MTK_THERMAL_SENSOR_LVTS1_0, /* LVTS1-0 */
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MTK_THERMAL_SENSOR_LVTS1_1, /* LVTS1-1 */
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MTK_THERMAL_SENSOR_LVTS2_0, /* LVTS2-0 */
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MTK_THERMAL_SENSOR_LVTS2_1, /* LVTS2-1 */
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MTK_THERMAL_SENSOR_LVTS2_2, /* LVTS2-2 */
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MTK_THERMAL_SENSOR_LVTS3_0, /* LVTS3-0 */
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MTK_THERMAL_SENSOR_LVTS3_1, /* LVTS3-1 */
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MTK_THERMAL_SENSOR_LVTS4_0, /* LVTS4-0 */
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MTK_THERMAL_SENSOR_LVTS4_1, /* LVTS4-1 */
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MTK_THERMAL_SENSOR_LVTS9_0, /* LVTS9-0 */
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#endif
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MTK_THERMAL_SENSOR_TSABB,
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ATM_CPU_LIMIT,
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ATM_GPU_LIMIT,
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MTK_THERMAL_SENSOR_CPU_COUNT
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};
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extern int tscpu_get_cpu_temp_met(enum mtk_thermal_sensor_cpu_id_met id);
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typedef void (*met_thermalsampler_funcMET)(void);
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extern void mt_thermalsampler_registerCB(met_thermalsampler_funcMET pCB);
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extern void mtkTTimer_cancel_timer(void);
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extern void mtkTTimer_start_timer(void);
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extern int mtkts_bts_get_hw_temp(void);
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extern int get_immediate_ts0_wrap(void);
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extern int get_immediate_ts1_wrap(void);
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extern int get_immediate_ts2_wrap(void);
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extern int get_immediate_ts3_wrap(void);
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extern int get_immediate_ts4_wrap(void);
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extern int get_immediate_ts5_wrap(void);
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extern int get_immediate_ts6_wrap(void);
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extern int get_immediate_ts7_wrap(void);
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extern int get_immediate_ts8_wrap(void);
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extern int get_immediate_ts9_wrap(void);
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#if CFG_THERM_LVTS
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extern int get_immediate_tslvts1_0_wrap(void); /* LVTS1-0 */
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extern int get_immediate_tslvts1_1_wrap(void); /* LVTS1-1 */
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extern int get_immediate_tslvts2_0_wrap(void); /* LVTS2-0 */
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extern int get_immediate_tslvts2_1_wrap(void); /* LVTS2-1 */
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extern int get_immediate_tslvts2_2_wrap(void); /* LVTS2-2 */
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extern int get_immediate_tslvts3_0_wrap(void); /* LVTS3-0 */
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extern int get_immediate_tslvts3_1_wrap(void); /* LVTS3-1 */
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extern int get_immediate_tslvts4_0_wrap(void); /* LVTS4-0 */
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extern int get_immediate_tslvts4_1_wrap(void); /* LVTS4-1 */
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extern int get_immediate_tslvts9_0_wrap(void); /* LVTS9-0 */
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#endif
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extern int get_immediate_tsabb_wrap(void);
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extern int (*get_immediate_tsX[TS_ENUM_MAX])(void);
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extern int is_cpu_power_unlimit(void); /* in mtk_ts_cpu.c */
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extern int is_cpu_power_min(void); /* in mtk_ts_cpu.c */
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extern int get_cpu_target_tj(void);
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extern int get_cpu_target_offset(void);
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extern int mtk_gpufreq_register(
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struct mt_gpufreq_power_table_info *freqs, int num);
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extern int get_target_tj(void);
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extern int mtk_thermal_get_tpcb_target(void);
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extern void thermal_set_big_core_speed(
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unsigned int tempMonCtl1, unsigned int tempMonCtl2, unsigned int tempAhbPoll);
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/*
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* return value(1): cooler of abcct/abcct_lcmoff is deactive,
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* and no thermal current limit.
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*/
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extern int mtk_cooler_is_abcct_unlimit(void);
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#endif /* __MT6763_THERMAL_H__ */
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