727 lines
23 KiB
C
727 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2017 MediaTek Inc.
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*/
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#ifndef __TSCPU_SETTINGS_H__
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#define __TSCPU_SETTINGS_H__
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#include "mach/mtk_thermal.h"
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "tzcpu_initcfg.h"
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#include "clatm_initcfg.h"
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#include "tscpu_tsense_config.h"
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#include "tscpu_lvts_config.h"
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/*=============================================================
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* Genernal
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*=============================================================
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*/
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#define MIN(_a_, _b_) ((_a_) > (_b_) ? (_b_) : (_a_))
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#define MAX(_a_, _b_) ((_a_) > (_b_) ? (_a_) : (_b_))
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#define _BIT_(_bit_) (unsigned int)(1 << (_bit_))
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#define _BITMASK_(_bits_) (((unsigned int) -1 >> (31 - ((1) ? _bits_))) \
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& ~((1U << ((0) ? _bits_)) - 1))
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#define THERMAL_TPROFILE_INIT() \
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long long thermal_pTime_us, thermal_cTime_us, thermal_diff_us
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#define THERMAL_GET_PTIME() {thermal_pTime_us = thermal_get_current_time_us()}
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#define THERMAL_GET_CTIME() {thermal_cTime_us = thermal_get_current_time_us()}
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#define THERMAL_TIME_TH 3000
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#define THERMAL_IS_TOO_LONG() \
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do { \
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thermal_diff_us = thermal_cTime_us - thermal_pTime_us; \
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if (thermal_diff_us > THERMAL_TIME_TH) { \
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pr_notice(TSCPU_LOG_TAG "%s: %llu us\n", __func__, \
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thermal_diff_us); \
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} else if (thermal_diff_us < 0) { \
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pr_notice(TSCPU_LOG_TAG \
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"Warning: tProfiling uses incorrect %s %d\n", \
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__func__, __LINE__); \
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} \
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} while (0)
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/*=============================================================
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* CONFIG (SW related)
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*=============================================================
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*/
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/*Enable thermal controller CG*/
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#define THERMAL_EBABLE_TC_CG
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#define ENALBE_UART_LIMIT (0)
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#define TEMP_EN_UART (80000)
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#define TEMP_DIS_UART (85000)
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#define TEMP_TOLERANCE (0)
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#define ENALBE_SW_FILTER (0)
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#define ATM_USES_PPM (1)
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#define THERMAL_GET_AHB_BUS_CLOCK (0)
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#define THERMAL_PERFORMANCE_PROFILE (0)
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/* 1: turn on GPIO toggle monitor; 0: turn off */
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#define THERMAL_GPIO_OUT_TOGGLE (0)
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/* 1: turn on adaptive AP cooler; 0: turn off */
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#define CPT_ADAPTIVE_AP_COOLER (1)
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/* 1: turn on supports to MET logging; 0: turn off */
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#define CONFIG_SUPPORT_MET_MTKTSCPU (0)
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/* Thermal controller HW filtering function.
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* Only 1, 2, 4, 8, 16 are valid values,
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* they means one reading is a avg of X samples
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*/
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#define THERMAL_CONTROLLER_HW_FILTER (2) /* 1, 2, 4, 8, 16 */
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/* 1: turn on thermal controller HW thermal protection; 0: turn off */
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#define THERMAL_CONTROLLER_HW_TP (1)
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/* 1: turn on fast polling in this sw module; 0: turn off */
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#define MTKTSCPU_FAST_POLLING (1)
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#if CPT_ADAPTIVE_AP_COOLER
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#define MAX_CPT_ADAPTIVE_COOLERS (3)
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#define THERMAL_HEADROOM (0)
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#define CONTINUOUS_TM (1)
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#define DYNAMIC_GET_GPU_POWER (1)
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/* 1: turn on precise power budgeting; 0: turn off */
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#define PRECISE_HYBRID_POWER_BUDGET (1)
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#define PHPB_DEFAULT_ON (1)
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#endif
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/* 1: thermal driver fast polling, use hrtimer; 0: turn off */
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/*#define THERMAL_DRV_FAST_POLL_HRTIMER (1)*/
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/* 1: thermal driver update temp to MET directly, use hrtimer; 0: turn off */
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#define THERMAL_DRV_UPDATE_TEMP_DIRECT_TO_MET (1)
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/* Define this in tscpu_settings.h enables this feature.
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* It polls CPU TS in hrtimer and
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* run ATM in RT 98 kthread. This is for MT6799 only.
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*/
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#define FAST_RESPONSE_ATM (1)
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#define THERMAL_INIT_VALUE (0xDA1)
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#define CLEAR_TEMP 26111
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/* Thermal VPU throttling support */
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#ifdef CONFIG_MTK_VPU_SUPPORT
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#define THERMAL_VPU_SUPPORT
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#endif
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/* Thermal MDLA throttling support */
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/* #define THERMAL_MDLA_SUPPORT */
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/* EARA_Thermal power budget allocation support */
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#define EARA_THERMAL_SUPPORT
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#define TS_FILL(n) {#n, n}
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/*#define TS_LEN_ARRAY(name) (sizeof(name)/sizeof(name[0]))*/
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#define MAX_TS_NAME 20
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#define CPU_COOLER_NUM 34
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#define MTK_TS_CPU_RT (0)
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#ifdef CONFIG_MTK_RAM_CONSOLE
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#define CONFIG_THERMAL_AEE_RR_REC (1)
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#else
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#define CONFIG_THERMAL_AEE_RR_REC (0)
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#endif
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#if CFG_THERM_LVTS
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#define CONFIG_LVTS_ERROR_AEE_WARNING (0)
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#else
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#define CONFIG_LVTS_ERROR_AEE_WARNING (0)
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#endif
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#define DUMP_LVTS_REGISTER_FOR_ZERO_RAW_ISSUE (0)
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#if CONFIG_LVTS_ERROR_AEE_WARNING
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#define LVTS_FORCE_ERROR_TRIGGER (0)
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#define LVTS_NUM_SKIP_SAMPLE (500)
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#define HISTORY_SAMPLES (10)
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#define FUTURE_SAMPLES (10)
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#define R_BUFFER_SIZE (HISTORY_SAMPLES + FUTURE_SAMPLES + 1)
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#define LVTS_ERROR_THRESHOLD (10000)
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#define DUMP_LVTS_REGISTER (0)
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#define DUMP_VCORE_VOLTAGE (0)
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#endif
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#define LVTS_VALID_DATA_TIME_PROFILING (0)
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#define LVTS_USE_DOMINATOR_SENSING_POINT (0)
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#define CFG_THERMAL_KERNEL_IGNORE_HOT_SENSOR (0)
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/*=============================================================
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*REG ACCESS
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*=============================================================
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*/
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/* double check */
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#define TS_CONFIGURE TS_CON1_TM /* depend on CPU design*/
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#define TS_CONFIGURE_P TS_CON1_P /* depend on CPU design*/
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/* turn on TS_CON1[5:4] 2'b 00 11001111 -> 0xCF ~(0x30)*/
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#define TS_TURN_ON 0xFFFFFFCF
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#define TS_TURN_OFF 0x00000030 /* turn off thermal*/
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#define thermal_setl(addr, val) mt_reg_sync_writel(readl(addr) | (val), \
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((void *)addr))
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#define thermal_clrl(addr, val) mt_reg_sync_writel(readl(addr) & ~(val), \
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((void *)addr))
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#define MTKTSCPU_TEMP_CRIT 120000 /* 120.000 degree Celsius */
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#define y_curr_repeat_times 1
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#define THERMAL_NAME "mtk-thermal"
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#define TS_MS_TO_NS(x) (x * 1000 * 1000)
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/*cpu core nums*/
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#define TZCPU_NO_CPU_CORES (8)
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#if THERMAL_GET_AHB_BUS_CLOCK
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#define THERMAL_MODULE_SW_CG_SET (therm_clk_infracfg_ao_base + 0x80)
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#define THERMAL_MODULE_SW_CG_CLR (therm_clk_infracfg_ao_base + 0x84)
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#define THERMAL_MODULE_SW_CG_STA (therm_clk_infracfg_ao_base + 0x90)
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#define THERMAL_CG (therm_clk_infracfg_ao_base + 0x80)
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#define THERMAL_DCM (therm_clk_infracfg_ao_base + 0x70)
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#endif
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/*=============================================================
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* Common Structure and Enum
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*=============================================================
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*/
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#if (CONFIG_THERMAL_AEE_RR_REC == 1)
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enum thermal_state {
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TSCPU_SUSPEND = 0,
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TSCPU_RESUME = 1,
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TSCPU_NORMAL = 2,
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TSCPU_INIT = 3,
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TSCPU_PAUSE = 4,
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TSCPU_RELEASE = 5
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};
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enum atm_state {
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ATM_WAKEUP = 0,
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ATM_CPULIMIT = 1,
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ATM_GPULIMIT = 2,
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ATM_DONE = 3,
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};
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#endif
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struct mtk_cpu_power_info {
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unsigned int cpufreq_khz;
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unsigned int cpufreq_ncpu;
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unsigned int cpufreq_power;
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};
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/*=============================================================
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* Tsense Structure and Enum
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*=============================================================
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*/
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/* private thermal sensor enum */
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enum tsmcu_sensor_enum {
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L_TS_MCU0 = 0,
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L_TS_MCU1,
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L_TS_MCU2,
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/* There is no TSMCU3 in MT6785 compared with MT6779 */
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L_TS_MCU4,
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L_TS_MCU5,
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L_TS_MCU6,
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L_TS_MCU7,
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L_TS_MCU8,
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L_TS_MCU9,
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L_TS_ABB,
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L_TS_MCU_NUM
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};
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enum thermal_controller_name {
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THERMAL_CONTROLLER0 = 0, /* TEMPMONCTL0 */
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THERMAL_CONTROLLER1, /* TEMPMONCTL0_1 */
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THERMAL_CONTROLLER2, /* TEMPMONCTL0_2 */
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THERMAL_CONTROLLER_NUM
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};
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struct thermal_controller_speed {
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unsigned int period_unit;
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unsigned int filter_interval_delay;
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unsigned int sensor_interval_delay;
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unsigned int ahb_polling_interval;
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};
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struct thermal_controller {
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enum tsmcu_sensor_enum ts[4]; /* Sensor point 0 ~ 3 */
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int ts_number;
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int dominator_ts_idx; //hw protection ref TS (index of the ts array)
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int tc_offset;
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struct thermal_controller_speed tc_speed;
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};
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/*=============================================================
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* LVTS Structure and Enum
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*=============================================================
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*/
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#if CFG_THERM_LVTS
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/* private thermal sensor enum */
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enum lvts_sensor_enum {
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L_TS_LVTS1_0 = 0,
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L_TS_LVTS1_1,
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L_TS_LVTS2_0,
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L_TS_LVTS2_1,
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L_TS_LVTS2_2,
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L_TS_LVTS3_0,
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L_TS_LVTS3_1,
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L_TS_LVTS4_0,
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/* There is no LVTS4_1 in MT6785 compared with MT6779 */
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/* LVTS9_0 always has no temperature data because
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* there is no HW route to it
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*/
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L_TS_LVTS9_0,
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L_TS_LVTS_NUM
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};
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enum lvts_tc_enum {
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LVTS_CONTROLLER0 = 0, /* LVTSMONCTL0 */
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LVTS_CONTROLLER1, /* LVTSMONCTL0_1 */
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LVTS_CONTROLLER2, /* LVTSMONCTL0_2 */
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LVTS_CONTROLLER3, /* LVTSMONCTL0_3 */
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LVTS_CONTROLLER_NUM
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};
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struct lvts_thermal_controller_speed {
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unsigned int group_interval_delay;
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unsigned int period_unit;
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unsigned int filter_interval_delay;
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unsigned int sensor_interval_delay;
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};
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struct lvts_thermal_controller {
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enum lvts_sensor_enum ts[4]; /* sensor point 0 ~ 3 */
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unsigned int ts_number;
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int dominator_ts_idx; /* hw protection ref TS (index of the ts array) */
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int tc_offset;
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struct lvts_thermal_controller_speed tc_speed;
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};
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#endif
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/*=============================================================
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* Shared variables
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*=============================================================
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*/
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#ifdef CONFIG_OF
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extern u32 thermal_irq_number;
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extern void __iomem *thermal_base;
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extern void __iomem *auxadc_ts_base;
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extern void __iomem *infracfg_ao_base;
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extern void __iomem *th_apmixed_base;
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extern void __iomem *INFRACFG_AO_base;
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extern int thermal_phy_base;
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extern int auxadc_ts_phy_base;
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extern int apmixed_phy_base;
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extern int pericfg_phy_base;
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#endif
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#if PRECISE_HYBRID_POWER_BUDGET
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/* tscpu_prev_cpu_temp: previous CPUSYS temperature
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* tscpu_curr_cpu_temp: current CPUSYS temperature
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* tscpu_prev_gpu_temp: previous GPUSYS temperature
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* tscpu_curr_gpu_temp: current GPUSYS temperature
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*/
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extern int tscpu_curr_cpu_temp;
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extern int tscpu_curr_gpu_temp;
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#endif
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/*
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* In src/mtk_tc.c
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*/
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extern int temp_eUART;
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extern int temp_dUART;
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extern int tscpu_debug_log;
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extern const struct of_device_id mt_thermal_of_match[2];
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extern struct thermal_controller tscpu_g_tc[THERMAL_CONTROLLER_NUM];
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extern int tscpu_polling_trip_temp1;
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extern int tscpu_polling_trip_temp2;
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extern int tscpu_polling_factor1;
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extern int tscpu_polling_factor2;
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/*
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* temperature array to store both tsmcu and lvts (if exist) and export them
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*/
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extern int tscpu_ts_temp[TS_ENUM_MAX];
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extern int tscpu_ts_temp_r[TS_ENUM_MAX]; /* raw data */
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/*
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* temperature array to store temp of tsmcu sensor
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*/
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extern int tscpu_ts_mcu_temp[L_TS_MCU_NUM];
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extern int tscpu_ts_mcu_temp_r[L_TS_MCU_NUM]; /* raw data */
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#if CFG_THERM_LVTS
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/*
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* temperature array to store temp of lvts sensor
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*/
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extern int tscpu_ts_lvts_temp[L_TS_LVTS_NUM];
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extern int tscpu_ts_lvts_temp_r[L_TS_LVTS_NUM]; /* raw data */
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#endif
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#if CONFIG_LVTS_ERROR_AEE_WARNING
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extern int tscpu_ts_mcu_temp_v[L_TS_MCU_NUM];
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extern int tscpu_ts_lvts_temp_v[L_TS_LVTS_NUM];
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#if DUMP_VCORE_VOLTAGE
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extern struct regulator *vcore_reg_id;
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#endif
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#endif
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#if LVTS_VALID_DATA_TIME_PROFILING
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extern unsigned long long int SODI3_count, noValid_count;
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/* If isTempValid is 0, it means no valid temperature data
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* between two SODI3 entry points.
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*/
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extern int isTempValid;
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extern long long int start_timestamp;
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/* count if start_timestamp is bigger than end_timestamp */
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extern int diff_error_count;
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#endif
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/*
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* support LVTS
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*/
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#if CFG_THERM_LVTS
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extern int lvts_rawdata_debug_log;
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extern int lvts_debug_log;
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extern struct lvts_thermal_controller
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lvts_tscpu_g_tc[LVTS_CONTROLLER_NUM];
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#endif
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#if MTKTSCPU_FAST_POLLING
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/* Combined fast_polling_trip_temp and fast_polling_factor,
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* it means polling_delay will be 1/5 of original interval
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* after mtktscpu reports > 65C w/o exit point
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*/
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extern int fast_polling_trip_temp;
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extern int fast_polling_trip_temp_high;
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extern int fast_polling_factor;
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extern int tscpu_cur_fp_factor;
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extern int tscpu_next_fp_factor;
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#endif
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/*In common/thermal_zones/mtk_ts_cpu.c*/
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extern long long int thermal_get_current_time_us(void);
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extern void tscpu_workqueue_cancel_timer(void);
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extern void tscpu_workqueue_start_timer(void);
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extern void __iomem *therm_clk_infracfg_ao_base;
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extern int Num_of_GPU_OPP;
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extern int gpu_max_opp;
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extern struct mt_gpufreq_power_table_info *mtk_gpu_power;
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extern int tscpu_read_curr_temp;
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#if MTKTSCPU_FAST_POLLING
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extern int tscpu_cur_fp_factor;
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#endif
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#if !defined(CONFIG_MTK_CLKMGR)
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extern struct clk *therm_main; /* main clock for Thermal*/
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#endif
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#if CPT_ADAPTIVE_AP_COOLER
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extern int tscpu_g_curr_temp;
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extern int tscpu_g_prev_temp;
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#if (THERMAL_HEADROOM == 1) || (CONTINUOUS_TM == 1)
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extern int bts_cur_temp; /* in mtk_ts_bts.c */
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#endif
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#endif
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extern char *adaptive_cooler_name;
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/* common/coolers/mtk_cooler_atm.c */
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extern unsigned int adaptive_cpu_power_limit;
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extern unsigned int adaptive_gpu_power_limit;
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extern int TARGET_TJS[MAX_CPT_ADAPTIVE_COOLERS];
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#ifdef FAST_RESPONSE_ATM
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extern void atm_cancel_hrtimer(void);
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extern void atm_restart_hrtimer(void);
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#endif
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/* common/coolers/mtk_cooler_dtm.c */
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extern unsigned int static_cpu_power_limit;
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extern unsigned int static_gpu_power_limit;
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extern int tscpu_cpu_dmips[CPU_COOLER_NUM];
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/*=============================================================
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* Shared functions
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*=============================================================
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*/
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/*In mtk_tc_wrapper.c */
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extern int tscpu_get_curr_max_ts_temp(void);
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extern int tscpu_max_temperature(void);
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extern int tscpu_get_curr_temp(void);
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extern int combine_lvts_tsmcu_temp(void);
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extern int tscpu_read_temperature_info(struct seq_file *m, void *v);
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extern int get_io_reg_base(void);
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/*In common/thermal_zones/mtk_ts_cpu.c*/
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extern void thermal_init_interrupt_for_UART(int temp_e, int temp_d);
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extern void tscpu_update_tempinfo(void);
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#if THERMAL_GPIO_OUT_TOGGLE
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void tscpu_set_GPIO_toggle_for_monitor(void);
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#endif
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extern void tscpu_update_tempinfo(void);
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/*In src/mtk_tc.c*/
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extern void tscpu_config_all_tc_hw_protect(int temperature, int temperature2);
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extern void tscpu_reset_thermal(void);
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extern void tscpu_thermal_initial_all_tc(void);
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extern void tscpu_thermal_read_tc_temp(
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int tc_num, enum tsmcu_sensor_enum type, int order);
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extern void tscpu_thermal_cal_prepare(void);
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extern void tscpu_thermal_cal_prepare_2(unsigned int ret);
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extern int tscpu_thermal_clock_on(void);
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extern int tscpu_thermal_clock_off(void);
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extern int tscpu_dump_cali_info(struct seq_file *m, void *v);
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extern int tscpu_thermal_fast_init(int tc_num);
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extern void thermal_get_AHB_clk_info(void);
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extern void print_risky_temps(char *prefix, int offset, int printLevel);
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extern void thermal_pause_all_periodoc_temp_sensing(void);
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extern void thermal_release_all_periodoc_temp_sensing(void);
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extern int (*max_temperature_in_bank[THERMAL_BANK_NUM])(void);
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extern void thermal_disable_all_periodoc_temp_sensing(void);
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extern void read_all_tc_tsmcu_temperature(void);
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extern irqreturn_t tscpu_thermal_all_tc_interrupt_handler(
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int irq, void *dev_id);
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/*
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* Support LVTS
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*/
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#if CFG_THERM_LVTS
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extern int lvts_get_io_reg_base(void);
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extern int lvts_max_temperature(void);
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extern void lvts_config_all_tc_hw_protect(int temperature, int temperature2);
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extern void lvts_thermal_read_tc_temp(
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int tc_num, enum lvts_sensor_enum type, int order);
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extern void lvts_read_all_tc_temperature(void);
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extern void lvts_reset_and_initial(int tc_num);
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extern int (*lvts_max_temperature_in_bank[THERMAL_BANK_NUM])(void);
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extern void lvts_thermal_lvts_device_init(void);
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extern void lvts_read_temperature(void);
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//extern void lvts_read_temperature(int temp0, int temp1);
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extern void lvts_thermal_cal_prepare(void);
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extern void lvts_device_identification(void);
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extern void lvts_reset_device_and_stop_clk(void);
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extern void lvts_read_device_id_rev(void);
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extern void lvts_Device_Enable_Init_all_Devices(void);
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extern void lvts_device_read_count_RC_N(void);
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extern void lvts_device_enable_auto_rck(void);
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extern void lvts_efuse_setting(void);
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extern void lvts_tscpu_thermal_initial_all_tc(void);
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extern void lvts_pause_all_sensing_points(void);
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extern void lvts_release_all_sensing_points(void);
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extern void lvts_disable_all_sensing_points(void);
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extern void lvts_enable_all_sensing_points(void);
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extern void read_all_tc_lvts_temperature(void);
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extern void lvts_wait_for_all_sensing_point_idle(void);
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extern irqreturn_t lvts_tscpu_thermal_all_tc_interrupt_handler(
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int irq, void *dev_id);
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extern int lvts_tscpu_dump_cali_info(struct seq_file *m, void *v);
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extern void lvts_sodi3_release_thermal_controller(void);
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extern void lvts_tscpu_reset_thermal(void);
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#endif
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/*
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* In drivers/misc/mediatek/gpu/hal/mtk_gpu_utility.c
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|
* It's not our api, ask them to provide header file
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*/
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extern bool mtk_get_gpu_loading(unsigned int *pLoading);
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/*
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* In drivers/misc/mediatek/auxadc/mt_auxadc.c
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|
* It's not our api, ask them to provide header file
|
|
*/
|
|
extern int IMM_IsAdcInitReady(void);
|
|
|
|
#if CONFIG_LVTS_ERROR_AEE_WARNING
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|
extern void dump_efuse_data(void);
|
|
extern int check_lvts_mcu_efuse(void);
|
|
extern int check_auxadc_mcu_efuse(void);
|
|
#if DUMP_LVTS_REGISTER
|
|
extern void read_controller_reg_before_active(void);
|
|
extern void read_controller_reg_when_error(void);
|
|
extern void read_device_reg_before_active(void);
|
|
extern void read_device_reg_when_error(void);
|
|
extern void clear_lvts_register_value_array(void);
|
|
extern void dump_lvts_register_value(void);
|
|
#endif
|
|
#endif
|
|
#if LVTS_VALID_DATA_TIME_PROFILING
|
|
extern void lvts_dump_time_profiling_result(struct seq_file *m);
|
|
#endif
|
|
/*=============================================================
|
|
*LOG
|
|
*=============================================================
|
|
*/
|
|
#define TSCPU_LOG_TAG "[Thermal/TZ/CPU]"
|
|
|
|
#define tscpu_dprintk(fmt, args...) \
|
|
do { \
|
|
if (tscpu_debug_log == 1) { \
|
|
pr_notice(TSCPU_LOG_TAG fmt, ##args); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define tscpu_printk(fmt, args...) pr_notice(TSCPU_LOG_TAG fmt, ##args)
|
|
#define tscpu_warn(fmt, args...) pr_notice(TSCPU_LOG_TAG fmt, ##args)
|
|
|
|
/*
|
|
* Support LVTS
|
|
*/
|
|
#if CFG_THERM_LVTS
|
|
#define LVTS_LOG_TAG "[Thermal/TZ/LVTS]"
|
|
#define LVTS_LOG_REG_TAG "[Thermal/TZ/LVTSREG]"
|
|
|
|
#define lvts_reg_print(fmt, args...) pr_notice(LVTS_LOG_REG_TAG fmt, ##args)
|
|
#define lvts_printk(fmt, args...) pr_notice(LVTS_LOG_TAG fmt, ##args)
|
|
#define lvts_warn(fmt, args...) pr_notice(LVTS_LOG_TAG fmt, ##args)
|
|
#if 0
|
|
#define lvts_dbg_printk(fmt, args...) pr_notice(LVTS_LOG_TAG fmt, ##args)
|
|
#else
|
|
#define lvts_dbg_printk(fmt, args...) \
|
|
do { \
|
|
if (lvts_debug_log == 1) { \
|
|
pr_notice(LVTS_LOG_TAG fmt, ##args); \
|
|
} \
|
|
} while (0)
|
|
#endif
|
|
#endif
|
|
|
|
/*=============================================================
|
|
* Register macro for internal use
|
|
*=============================================================
|
|
*/
|
|
|
|
#if 1
|
|
#define THERM_CTRL_BASE_2 thermal_base
|
|
#define AUXADC_BASE_2 auxadc_ts_base
|
|
#define INFRACFG_AO_BASE_2 infracfg_ao_base
|
|
#define APMIXED_BASE_2 th_apmixed_base
|
|
#else
|
|
#include <mach/mt_reg_base.h>
|
|
#define AUXADC_BASE_2 AUXADC_BASE
|
|
#define THERM_CTRL_BASE_2 THERM_CTRL_BASE
|
|
#define PERICFG_BASE_2 PERICFG_BASE
|
|
#define APMIXED_BASE_2 APMIXED_BASE
|
|
#endif
|
|
|
|
/*******************************************************************************
|
|
* AUXADC Register Definition
|
|
*****************************************************************************
|
|
*/
|
|
|
|
#define AUXADC_CON0_V (AUXADC_BASE_2 + 0x000)
|
|
#define AUXADC_CON1_V (AUXADC_BASE_2 + 0x004)
|
|
#define AUXADC_CON1_SET_V (AUXADC_BASE_2 + 0x008)
|
|
#define AUXADC_CON1_CLR_V (AUXADC_BASE_2 + 0x00C)
|
|
#define AUXADC_CON2_V (AUXADC_BASE_2 + 0x010)
|
|
/*#define AUXADC_CON3_V (AUXADC_BASE_2 + 0x014)*/
|
|
#define AUXADC_DAT0_V (AUXADC_BASE_2 + 0x014)
|
|
#define AUXADC_DAT1_V (AUXADC_BASE_2 + 0x018)
|
|
#define AUXADC_DAT2_V (AUXADC_BASE_2 + 0x01C)
|
|
#define AUXADC_DAT3_V (AUXADC_BASE_2 + 0x020)
|
|
#define AUXADC_DAT4_V (AUXADC_BASE_2 + 0x024)
|
|
#define AUXADC_DAT5_V (AUXADC_BASE_2 + 0x028)
|
|
#define AUXADC_DAT6_V (AUXADC_BASE_2 + 0x02C)
|
|
#define AUXADC_DAT7_V (AUXADC_BASE_2 + 0x030)
|
|
#define AUXADC_DAT8_V (AUXADC_BASE_2 + 0x034)
|
|
#define AUXADC_DAT9_V (AUXADC_BASE_2 + 0x038)
|
|
#define AUXADC_DAT10_V (AUXADC_BASE_2 + 0x03C)
|
|
#define AUXADC_DAT11_V (AUXADC_BASE_2 + 0x040)
|
|
#define AUXADC_MISC_V (AUXADC_BASE_2 + 0x094)
|
|
|
|
#define AUXADC_CON0_P (auxadc_ts_phy_base + 0x000)
|
|
#define AUXADC_CON1_P (auxadc_ts_phy_base + 0x004)
|
|
#define AUXADC_CON1_SET_P (auxadc_ts_phy_base + 0x008)
|
|
#define AUXADC_CON1_CLR_P (auxadc_ts_phy_base + 0x00C)
|
|
#define AUXADC_CON2_P (auxadc_ts_phy_base + 0x010)
|
|
/*#define AUXADC_CON3_P (auxadc_ts_phy_base + 0x014)*/
|
|
#define AUXADC_DAT0_P (auxadc_ts_phy_base + 0x014)
|
|
#define AUXADC_DAT1_P (auxadc_ts_phy_base + 0x018)
|
|
#define AUXADC_DAT2_P (auxadc_ts_phy_base + 0x01C)
|
|
#define AUXADC_DAT3_P (auxadc_ts_phy_base + 0x020)
|
|
#define AUXADC_DAT4_P (auxadc_ts_phy_base + 0x024)
|
|
#define AUXADC_DAT5_P (auxadc_ts_phy_base + 0x028)
|
|
#define AUXADC_DAT6_P (auxadc_ts_phy_base + 0x02C)
|
|
#define AUXADC_DAT7_P (auxadc_ts_phy_base + 0x030)
|
|
#define AUXADC_DAT8_P (auxadc_ts_phy_base + 0x034)
|
|
#define AUXADC_DAT9_P (auxadc_ts_phy_base + 0x038)
|
|
#define AUXADC_DAT10_P (auxadc_ts_phy_base + 0x03C)
|
|
#define AUXADC_DAT11_P (auxadc_ts_phy_base + 0x040)
|
|
|
|
#define AUXADC_MISC_P (auxadc_ts_phy_base + 0x094)
|
|
|
|
/*******************************************************************************
|
|
* Peripheral Configuration Register Definition
|
|
*****************************************************************************
|
|
*/
|
|
|
|
/*APB Module infracfg_ao*/
|
|
#define INFRA_GLOBALCON_RST_0_SET (INFRACFG_AO_BASE_2 + 0x120)
|
|
#define INFRA_GLOBALCON_RST_0_CLR (INFRACFG_AO_BASE_2 + 0x124)
|
|
#define INFRA_GLOBALCON_RST_0_STA (INFRACFG_AO_BASE_2 + 0x128)
|
|
/*******************************************************************************
|
|
* APMixedSys Configuration Register Definition
|
|
*****************************************************************************
|
|
*/
|
|
/* TODO: check base addr. */
|
|
#define TS_CON0_TM (APMIXED_BASE_2 + 0x600) /*yes 0x10212000*/
|
|
#define TS_CON1_TM (APMIXED_BASE_2 + 0x604)
|
|
#define TS_CON0_P (apmixed_phy_base + 0x600)
|
|
#define TS_CON1_P (apmixed_phy_base + 0x604)
|
|
|
|
/*******************************************************************************
|
|
* Thermal Controller Register Mask Definition
|
|
*****************************************************************************
|
|
*/
|
|
|
|
#define THERMAL_COLD_INTERRUPT_0 0x00000001
|
|
#define THERMAL_HOT_INTERRUPT_0 0x00000002
|
|
#define THERMAL_LOW_OFFSET_INTERRUPT_0 0x00000004
|
|
#define THERMAL_HIGH_OFFSET_INTERRUPT_0 0x00000008
|
|
#define THERMAL_HOT2NORMAL_INTERRUPT_0 0x00000010
|
|
#define THERMAL_COLD_INTERRUPT_1 0x00000020
|
|
#define THERMAL_HOT_INTERRUPT_1 0x00000040
|
|
#define THERMAL_LOW_OFFSET_INTERRUPT_1 0x00000080
|
|
#define THERMAL_HIGH_OFFSET_INTERRUPT_1 0x00000100
|
|
#define THERMAL_HOT2NORMAL_INTERRUPT_1 0x00000200
|
|
#define THERMAL_COLD_INTERRUPT_2 0x00000400
|
|
#define THERMAL_HOT_INTERRUPT_2 0x00000800
|
|
#define THERMAL_LOW_OFFSET_INTERRUPT_2 0x00001000
|
|
#define THERMAL_HIGH_OFFSET_INTERRUPT_2 0x00002000
|
|
#define THERMAL_HOT2NORMAL_INTERRUPT_2 0x00004000
|
|
#define THERMAL_AHB_TIMEOUT_INTERRUPT 0x00008000
|
|
#define THERMAL_DEVICE_TIMEOUT_INTERRUPT 0x00008000
|
|
#define THERMAL_IMMEDIATE_INTERRUPT_0 0x00010000
|
|
#define THERMAL_IMMEDIATE_INTERRUPT_1 0x00020000
|
|
#define THERMAL_IMMEDIATE_INTERRUPT_2 0x00040000
|
|
#define THERMAL_FILTER_INTERRUPT_0 0x00080000
|
|
#define THERMAL_FILTER_INTERRUPT_1 0x00100000
|
|
#define THERMAL_FILTER_INTERRUPT_2 0x00200000
|
|
#define THERMAL_COLD_INTERRUPT_3 0x00400000
|
|
#define THERMAL_HOT_INTERRUPT_3 0x00800000
|
|
#define THERMAL_LOW_OFFSET_INTERRUPT_3 0x01000000
|
|
#define THERMAL_HIGH_OFFSET_INTERRUPT_3 0x02000000
|
|
#define THERMAL_HOT2NORMAL_INTERRUPT_3 0x04000000
|
|
#define THERMAL_IMMEDIATE_INTERRUPT_3 0x08000000
|
|
#define THERMAL_FILTER_INTERRUPT_3 0x10000000
|
|
#define THERMAL_PROTECTION_STAGE_1 0x20000000
|
|
#define THERMAL_PROTECTION_STAGE_2 0x40000000
|
|
#define THERMAL_PROTECTION_STAGE_3 0x80000000
|
|
#endif /* __TSCPU_SETTINGS_H__ */
|