429 lines
19 KiB
C
429 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_PLAT_UART_H__
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#define __MTK_PLAT_UART_H__
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#include <asm/irq.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/pinctrl/consumer.h>
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/******************************************************************************
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* Function Configuration
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******************************************************************************/
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#define ENABLE_DEBUG
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#define ENABLE_VFIFO
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/* Fix-me: marked for early porting */
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#define POWER_FEATURE /*control power-on/power-off */
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#define ENABLE_FRACTIONAL
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#define ENABLE_SYSFS
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/* #define UART_USING_FIX_CLK_ENABLE */
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#define UART_FCR_USING_SW_BACK_UP
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#define ENABLE_UART_SLEEP
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/*---------------------------------------------------------------------------*/
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#if defined(WMT_PLAT_ALPS)
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#define ENABLE_RAW_DATA_DUMP
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#endif
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/*---------------------------------------------------------------------------*/
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#if defined(ENABLE_VFIFO) && defined(ENABLE_DEBUG)
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#define ENABLE_VFIFO_DEBUG
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#endif
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/******************************************************************************
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* MACRO & CONSTANT
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******************************************************************************/
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#define DBG_TAG "[UART] "
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#define CFG_UART_AUTOBAUD 0
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/*---------------------------------------------------------------------------*/
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#define UART_VFIFO_SIZE 8192
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#define UART_VFIFO_ALERT_LEN 0x3f
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/*---------------------------------------------------------------------------*/
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#define UART_MAX_TX_PENDING 1024
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/*---------------------------------------------------------------------------*/
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#define UART_MAJOR 204
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#define UART_MINOR 209
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#if defined(CONFIG_FPGA_EARLY_PORTING)
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#define UART_NR 2
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#else
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#define UART_NR 2
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#endif
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#ifndef FALSE
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#define FALSE (0)
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#endif
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#ifndef TRUE
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#define TRUE (1)
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#endif
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/*---------------------------------------------------------------------------*/
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#define WAIT_UART_ACK_TIMES 10
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/*---------------------------------------------------------------------------*/
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#define IRQF_LEVEL_TRIGGER_POLARITY IRQF_TRIGGER_LOW
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#define IRQF_EDGE_TRIGGER_POLARITY IRQF_TRIGGER_FALLING
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/*---- Macro defination remap -----------------------------------------------*/
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#if (defined(CONFIG_FIQ_DEBUGGER_CONSOLE) && defined(CONFIG_FIQ_DEBUGGER))
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#define DEFAULT_FIQ_UART_PORT (3)
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#endif
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/* For ATE factory feature */
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#ifdef ATE_FACTORY_ENABLE
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#define ATE_FACTORY_MODE 6
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#endif
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/*---------------------------------------------------------------------------*/
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#define MTK_SYSCLK_65 65000000
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#define MTK_SYSCLK_49_4 49400000
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#define MTK_SYSCLK_58_5 58500000
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#define MTK_SYSCLK_52 52000000
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#define MTK_SYSCLK_26 26000000
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#define MTK_SYSCLK_13 13000000
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#define MTK_SYSCLK_6144 61440000
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#define MTK_SYSCLK_3072 30720000
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#define MTK_SYSCLK_1536 15360000
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/*---------------------------------------------------------------------------*/
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/* FIXME: MT6593 FPGA porting*/
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#ifdef CONFIG_FPGA_EARLY_PORTING
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#ifdef FIX_TO_26M
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#define UART_SYSCLK MTK_SYSCLK_26
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#else
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#define UART_SYSCLK 12000000
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#endif
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#else
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#define UART_SYSCLK MTK_SYSCLK_26
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#endif
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/*---------------------------------------------------------------------------*/
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#define ISWEXT (0x80000000) /* extended bit in c_iflag */
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/*---------------------------------------------------------------------------*/
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/* the size definition of VFF */
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#define C_UART1_VFF_TX_SIZE (1024) /* the size must be 8-byte alignment */
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#define C_UART1_VFF_RX_SIZE (1024) /* the size must be 8-byte alignment */
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#define C_UART2_VFF_TX_SIZE (8192) /* the size must be 8-byte alignment */
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#define C_UART2_VFF_RX_SIZE (8192) /* the size must be 8-byte alignment */
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#define C_UART3_VFF_TX_SIZE (8192) /* the size must be 8-byte alignment */
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#define C_UART3_VFF_RX_SIZE (8192) /* the size must be 8-byte alignment */
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#define C_UART4_VFF_TX_SIZE (1024) /* the size must be 8-byte alignment */
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#define C_UART4_VFF_RX_SIZE (1024) /* the size must be 8-byte alignment */
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/******************************************************************************
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* LOG SETTING
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******************************************************************************/
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/* Debug message event */
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#define DBG_EVT_NONE 0x00000000 /* No event */
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#define DBG_EVT_DMA 0x00000001 /* DMA related event */
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#define DBG_EVT_INT 0x00000002 /* UART INT event */
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#define DBG_EVT_CFG 0x00000004 /* UART CFG event */
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#define DBG_EVT_FUC 0x00000008 /* Function event */
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#define DBG_EVT_INFO 0x00000010 /* information event */
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#define DBG_EVT_ERR 0x00000020 /* Error event */
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#define DBG_EVT_DAT 0x00000040 /* data dump to uart */
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#define DBG_EVT_BUF 0x00000080 /* data dump to buffer */
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#define DBG_EVT_MSC 0x00000100 /* misc log */
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#define DBG_EVT_ALL 0xffffffff
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/*---------------------------------------------------------------------------*/
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#ifdef ENABLE_DEBUG
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/*---------------------------------------------------------------------------*/
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#define MSG(evt, fmt, args...) \
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do { \
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if ((DBG_EVT_##evt) & uart->evt_mask) { \
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const char *s = #evt; \
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if (DBG_EVT_##evt & DBG_EVT_ERR) \
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pr_notice(" [UART%d]:%c:%4d: " fmt, \
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uart->nport, s[0], __LINE__, ##args); \
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else \
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pr_debug(" [UART%d]:%c: " fmt, uart->nport, s[0], ##args); \
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} \
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} while (0)
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/*---------------------------------------------------------------------------*/
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#define UART_DEBUG_EVT(evt) ((evt) & uart->evt_mask)
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/*---------------------------------------------------------------------------*/
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#define MSG_FUNC_ENTRY(f) MSG(FUC, "%s\n", __func__)
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#define MSG_RAW pr_debug
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/*---------------------------------------------------------------------------*/
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#else /* release mode: only enable error log */
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#define MSG(evt, fmt, args...) MSG##evt(fmt, ##args)
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#define MSGERR(fmt, args...) pr_notice(" [UART%d]:E:%4d: " fmt, uart->nport, __LINE__, ##args)
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#define MSGDMA(fmt, args...)
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#define MSGCFG(fmt, args...)
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#define MSGFUC(fmt, args...)
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#define MSGINFO(fmt, args...)
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#define MSGDAT(fmt, args...)
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#define MSGMSC(fmt, args...)
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#define MSG_RAW(fmt, args...)
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#define MSG_FUNC_ENTRY(f) do {} while (0)
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#endif /**/
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#define MSG_ERR(fmt, args...) pr_notice("[UARTX]:E:%4d: " fmt, __LINE__, ##args)
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#define MSG_TRC(fmt, args...) pr_debug("[UARTX]:T: " fmt, ##args)
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#define DEV_TRC(fmt, args...) pr_debug("[UART%d]:T: " fmt, uart->nport, ##args)
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/*---------------------------------------------------------------------------*/
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#define DRV_NAME "mtk-uart"
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/*---------------------------------------------------------------------------*/
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/******************************************************************************
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* ENUM & STRUCT
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******************************************************************************/
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/* uart port ids */
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enum {
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UART_PORT0 = 0,
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UART_PORT1,
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UART_PORT2,
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UART_PORT3,
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UART_PORT_NUM,
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};
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/*---------------------------------------------------------------------------*/
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#define UART_FIFO_SIZE (16)
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/*---------------------------------------------------------------------------*/
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#define UART_RBR (unsigned long)(base+0x00) /* Read only */
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#define UART_THR (unsigned long)(base+0x00) /* Write only */
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#define UART_IER (unsigned long)(base+0x04)
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#define UART_IIR (unsigned long)(base+0x08) /* Read only */
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#define UART_FCR (unsigned long)(base+0x08) /* Write only */
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#define UART_LCR (unsigned long)(base+0x0c)
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#define UART_MCR (unsigned long)(base+0x10)
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#define UART_LSR (unsigned long)(base+0x14)
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#define UART_MSR (unsigned long)(base+0x18)
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#define UART_SCR (unsigned long)(base+0x1c)
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#define UART_DLL (unsigned long)(base+0x00) /* Only when LCR.DLAB = 1 */
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#define UART_DLH (unsigned long)(base+0x04) /* Only when LCR.DLAB = 1 */
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#define UART_EFR (unsigned long)(base+0x08) /* Only when LCR = 0xbf */
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#define UART_XON1 (unsigned long)(base+0x10) /* Only when LCR = 0xbf */
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#define UART_XON2 (unsigned long)(base+0x14) /* Only when LCR = 0xbf */
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#define UART_XOFF1 (unsigned long)(base+0x18) /* Only when LCR = 0xbf */
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#define UART_XOFF2 (unsigned long)(base+0x1c) /* Only when LCR = 0xbf */
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#define UART_AUTOBAUD_EN (unsigned long)(base+0x20)
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#define UART_HIGHSPEED (unsigned long)(base+0x24)
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#define UART_SAMPLE_COUNT (unsigned long)(base+0x28)
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#define UART_SAMPLE_POINT (unsigned long)(base+0x2c)
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#define UART_AUTOBAUD_REG (unsigned long)(base+0x30)
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#define UART_RATE_FIX_AD (unsigned long)(base+0x34)
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#define UART_AUTOBAUD_SAMPLE (unsigned long)(base+0x38)
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#define UART_GUARD (unsigned long)(base+0x3c)
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#define UART_ESCAPE_DAT (unsigned long)(base+0x40)
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#define UART_ESCAPE_EN (unsigned long)(base+0x44)
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#define UART_SLEEP_EN (unsigned long)(base+0x48)
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#define UART_DMA_EN (unsigned long)(base+0x4c)
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#define UART_RXTRI_AD (unsigned long)(base+0x50)
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#define UART_FRACDIV_L (unsigned long)(base+0x54)
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#define UART_FRACDIV_M (unsigned long)(base+0x58)
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#define UART_FCR_RD (unsigned long)(base+0x5C)
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#define UART_ACTIVE_EN (unsigned long)(base+0x60)
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#define UART_RX_SEL (unsigned long)(base+0xB0)
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#define UART_SLEEP_REQ (unsigned long)(base+0xB4)
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#define UART_SLEEP_ACK (unsigned long)(base+0xB8)
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/* system level, not related to hardware */
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#define UST_DUMMY_READ (1 << 31)
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/*---------------------------------------------------------------------------*/
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/* For MT6589, both RX and TX will not use port to send or receive data */
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/* IER */
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#define UART_IER_ERBFI (1 << 0) /* RX buffer conatins data int. */
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#define UART_IER_ETBEI (1 << 1) /* TX FIFO threshold trigger int. */
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#define UART_IER_ELSI (1 << 2) /* BE, FE, PE, or OE int. */
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#define UART_IER_EDSSI (1 << 3) /* CTS change (DCTS) int. */
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/* When set "1", enable flow control triggered by RX FIFO full when VFIFO_EN is set. */
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#define UART_IER_VFF_FC_EN (1 << 4)
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#define UART_IER_XOFFI (1 << 5)
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#define UART_IER_RTSI (1 << 6)
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#define UART_IER_CTSI (1 << 7)
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#define UART_IER_ALL_INTS (UART_IER_ERBFI|UART_IER_ETBEI|UART_IER_ELSI|\
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UART_IER_EDSSI|UART_IER_XOFFI|UART_IER_RTSI|\
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UART_IER_CTSI)
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#define UART_IER_HW_NORMALINTS (UART_IER_ERBFI|UART_IER_ELSI|UART_IER_EDSSI|UART_IER_VFF_FC_EN)
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#define UART_IER_HW_ALLINTS (UART_IER_ERBFI|UART_IER_ETBEI| \
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UART_IER_ELSI|UART_IER_EDSSI)
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/*---------------------------------------------------------------------------*/
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/* FCR */
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#define UART_FCR_FIFOE (1 << 0)
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#define UART_FCR_CLRR (1 << 1)
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#define UART_FCR_CLRT (1 << 2)
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#define UART_FCR_DMA1 (1 << 3)
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#define UART_FCR_RXFIFO_1B_TRI (0 << 6)
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#define UART_FCR_RXFIFO_6B_TRI (1 << 6)
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#define UART_FCR_RXFIFO_12B_TRI (2 << 6)
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#define UART_FCR_RXFIFO_RX_TRI (3 << 6)
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#define UART_FCR_TXFIFO_1B_TRI (0 << 4)
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#define UART_FCR_TXFIFO_4B_TRI (1 << 4)
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#define UART_FCR_TXFIFO_8B_TRI (2 << 4)
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#define UART_FCR_TXFIFO_14B_TRI (3 << 4)
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#define UART_FCR_FIFO_INIT (UART_FCR_FIFOE|UART_FCR_CLRR|UART_FCR_CLRT)
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#define UART_FCR_NORMAL (UART_FCR_FIFO_INIT | \
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UART_FCR_TXFIFO_4B_TRI| \
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UART_FCR_RXFIFO_12B_TRI)
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/*---------------------------------------------------------------------------*/
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/* LCR */
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#define UART_LCR_BREAK (1 << 6)
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#define UART_LCR_DLAB (1 << 7)
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#define UART_WLS_5 (0 << 0)
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#define UART_WLS_6 (1 << 0)
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#define UART_WLS_7 (2 << 0)
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#define UART_WLS_8 (3 << 0)
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#define UART_WLS_MASK (3 << 0)
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#define UART_1_STOP (0 << 2)
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#define UART_2_STOP (1 << 2)
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#define UART_1_5_STOP (1 << 2) /* Only when WLS=5 */
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#define UART_STOP_MASK (1 << 2)
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#define UART_NONE_PARITY (0 << 3)
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#define UART_ODD_PARITY (0x1 << 3)
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#define UART_EVEN_PARITY (0x3 << 3)
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#define UART_MARK_PARITY (0x5 << 3)
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#define UART_SPACE_PARITY (0x7 << 3)
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#define UART_PARITY_MASK (0x7 << 3)
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/*---------------------------------------------------------------------------*/
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/* MCR */
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#define UART_MCR_DTR (1 << 0)
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#define UART_MCR_RTS (1 << 1)
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#define UART_MCR_OUT1 (1 << 2)
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#define UART_MCR_OUT2 (1 << 3)
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#define UART_MCR_LOOP (1 << 4)
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#define UART_MCR_DCM_EN (1 << 5) /* MT6589 move to bit5 */
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#define UART_MCR_XOFF (1 << 7) /* read only */
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#define UART_MCR_NORMAL (UART_MCR_DTR|UART_MCR_RTS)
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/*---------------------------------------------------------------------------*/
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/* LSR */
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#define UART_LSR_DR (1 << 0)
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#define UART_LSR_OE (1 << 1)
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#define UART_LSR_PE (1 << 2)
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#define UART_LSR_FE (1 << 3)
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#define UART_LSR_BI (1 << 4)
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#define UART_LSR_THRE (1 << 5)
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#define UART_LSR_TEMT (1 << 6)
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#define UART_LSR_FIFOERR (1 << 7)
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/*---------------------------------------------------------------------------*/
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/* MSR */
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#define UART_MSR_DCTS (1 << 0)
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#define UART_MSR_DDSR (1 << 1)
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#define UART_MSR_TERI (1 << 2)
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#define UART_MSR_DDCD (1 << 3)
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#define UART_MSR_CTS (1 << 4)
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#define UART_MSR_DSR (1 << 5)
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#define UART_MSR_RI (1 << 6)
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#define UART_MSR_DCD (1 << 7)
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/*---------------------------------------------------------------------------*/
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/* EFR */
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#define UART_EFR_EN (1 << 4)
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#define UART_EFR_AUTO_RTS (1 << 6)
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#define UART_EFR_AUTO_CTS (1 << 7)
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#define UART_EFR_SW_CTRL_MASK (0xf << 0)
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#define UART_EFR_NO_SW_CTRL (0)
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#define UART_EFR_NO_FLOW_CTRL (0)
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#define UART_EFR_AUTO_RTSCTS (UART_EFR_AUTO_RTS|UART_EFR_AUTO_CTS)
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#define UART_EFR_XON1_XOFF1 (0xa) /* TX/RX XON1/XOFF1 flow control */
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#define UART_EFR_XON2_XOFF2 (0x5) /* TX/RX XON2/XOFF2 flow control */
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#define UART_EFR_XON12_XOFF12 (0xf) /* TX/RX XON1,2/XOFF1,2 flow control */
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#define UART_EFR_XON1_XOFF1_MASK (0xa)
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#define UART_EFR_XON2_XOFF2_MASK (0x5)
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/*---------------------------------------------------------------------------*/
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/* IIR (Read Only) */
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#define UART_IIR_NO_INT_PENDING (0x01)
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#define UART_IIR_RLS (0x06) /* Receiver Line Status */
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#define UART_IIR_RDA (0x04) /* Receive Data Available */
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#define UART_IIR_CTI (0x0C) /* Character Timeout Indicator */
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#define UART_IIR_THRE (0x02) /* Transmit Holding Register Empty */
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#define UART_IIR_MS (0x00) /* Check Modem Status Register */
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#define UART_IIR_SW_FLOW_CTRL (0x10) /* Receive XOFF characters */
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#define UART_IIR_HW_FLOW_CTRL (0x20) /* CTS or RTS Rising Edge */
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#define UART_IIR_FIFO_EN (0xc0)
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#define UART_IIR_INT_MASK (0x3f)
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/*---------------------------------------------------------------------------*/
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/* RateFix */
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#define UART_RATE_FIX (1 << 0)
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/* #define UART_AUTORATE_FIX (1 << 1) */
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#define UART_FREQ_SEL (1 << 1)
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#define UART_RATE_FIX_13M (1 << 0) /* means UARTclk = APBclk / 4 */
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#define UART_AUTORATE_FIX_13M (1 << 1)
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#define UART_FREQ_SEL_13M (1 << 2)
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#define UART_RATE_FIX_ALL_13M (UART_RATE_FIX_13M|UART_AUTORATE_FIX_13M| \
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UART_FREQ_SEL_13M)
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#define UART_RATE_FIX_26M (0 << 0) /* means UARTclk = APBclk / 2 */
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#define UART_AUTORATE_FIX_26M (0 << 1)
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#define UART_FREQ_SEL_26M (0 << 2)
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#define UART_RATE_FIX_16M25 (UART_FREQ_SEL|UART_RATE_FIX)
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#define UART_RATE_FIX_32M5 (UART_RATE_FIX)
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/*---------------------------------------------------------------------------*/
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/* Autobaud sample */
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#define UART_AUTOBADUSAM_13M 7
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#define UART_AUTOBADUSAM_26M 15
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#define UART_AUTOBADUSAM_52M 31
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/* #define UART_AUTOBADUSAM_52M 29 */ /* CHECKME! 28 or 29 ? */
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#define UART_AUTOBAUDSAM_58_5M 31 /* CHECKME! 31 or 32 ? */
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/*---------------------------------------------------------------------------*/
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/* DMA enable */
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#define UART_RX_DMA_EN (1 << 0)
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#define UART_TX_DMA_EN (1 << 1)
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#define UART_TO_CNT_AUTORST (1 << 2)
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/*---------------------------------------------------------------------------*/
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/* Escape character*/
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#define UART_ESCAPE_CH 0x77
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/*---------------------------------------------------------------------------*/
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/* Request UART to sleep*/
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#define UART_CLK_OFF_REQ (1 << 0)
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/*---------------------------------------------------------------------------*/
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/* UART sleep ack*/
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#define UART_CLK_OFF_ACK (1 << 0)
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/*---------------------------------------------------------------------------*/
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/* Debugging */
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struct uart_iir_reg {
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u32 NINT:1;
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u32 ID:5;
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u32 FIFOE:2;
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u32 dummy:24;
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};
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/*---------------------------------------------------------------------------*/
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#define VFF_INT_FLAG(_b) (_b+0x0000)
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#define VFF_INT_EN(_b) (_b+0x0004)
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#define VFF_EN(_b) (_b+0x0008)
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#define VFF_RST(_b) (_b+0x000C)
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#define VFF_STOP(_b) (_b+0x0010)
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#define VFF_FLUSH(_b) (_b+0x0014)
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#define VFF_ADDR(_b) (_b+0x001C)
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#define VFF_LEN(_b) (_b+0x0024)
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#define VFF_THRE(_b) (_b+0x0028)
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#define VFF_WPT(_b) (_b+0x002C)
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#define VFF_RPT(_b) (_b+0x0030)
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#define VFF_W_INT_BUF_SIZE(_b) (_b+0x0034)
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#define VFF_INT_BUF_SIZE(_b) (_b+0x0038)
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#define VFF_VALID_SIZE(_b) (_b+0x003C)
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#define VFF_LEFT_SIZE(_b) (_b+0x0040)
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#define VFF_DEBUG_STATUS(_b) (_b+0x0050)
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#define VFF_4G_DRAM_SUPPORT(_b) (_b+0x0054)
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#define VFF_VPORT_BASE 0xF7070000
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#define VFF_VPORT_CH(id) (VFF_VPORT_BASE + (id) * 0x00000080)
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/*---------------------------------------------------------------------------*/
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/*VFF_INT_FLAG */
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#define VFF_RX_INT_FLAG0_B (1 << 0) /*rx_vff_valid_size >= rx_vff_thre */
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/*when UART issues flush to DMA and all data in UART VFIFO is transferred to VFF */
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#define VFF_RX_INT_FLAG1_B (1 << 1)
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#define VFF_TX_INT_FLAG0_B (1 << 0) /*tx_vff_left_size >= tx_vff_thrs */
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#define VFF_INT_FLAG_CLR_B (0 << 0)
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/*VFF_INT_EN*/
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#define VFF_RX_INT_EN0_B (1 << 0) /*rx_vff_valid_size >= rx_vff_thre */
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/*when UART issues flush to DMA and all data in UART VFIFO is transferred to VFF */
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#define VFF_RX_INT_EN1_B (1 << 1)
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#define VFF_TX_INT_EN_B (1 << 0) /*tx_vff_left_size >= tx_vff_thrs */
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#define VFF_INT_EN_CLR_B (0 << 0)
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/*VFF_RST*/
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#define VFF_WARM_RST_B (1 << 0)
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#define VFF_HARD_RST_B (1 << 1)
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/*VFF_EN*/
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#define VFF_EN_B (1 << 0)
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/*VFF_STOP*/
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#define VFF_STOP_B (1 << 0)
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#define VFF_STOP_CLR_B (0 << 0)
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/*VFF_FLUSH*/
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#define VFF_FLUSH_B (1 << 0)
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#define VFF_FLUSH_CLR_B (0 << 0)
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#define VFF_TX_THRE(n) ((n)*7/8) /* tx_vff_left_size >= tx_vff_thrs */
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#define VFF_RX_THRE(n) ((n)*3/4) /* trigger level of rx vfifo */
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/*---------------------------------------------------------------------------*/
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#endif /* MTK_UART_H */
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