752 lines
11 KiB
C
752 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#define LOG_TAG "INFO"
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#include "ddp_info.h"
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#include "ddp_debug.h"
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#include "ddp_log.h"
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static const char reg_magic[] = "no_regs_info";
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static struct ddp_module ddp_modules[DISP_MODULE_NUM] = {
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/*
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* {module_id,
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* module_type,
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* module_name,
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* can_connect,
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* module_driver,
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*
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* {reg_dt_name,
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* reg_pa_check,
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* reg_irq_check,
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* irq_max_bit,
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* reg_va,
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* reg_irq}
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* },
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*/
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{DISP_MODULE_OVL0,
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DISP_T_OVL,
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"ovl0",
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1,
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&ddp_driver_ovl,
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{"mediatek,disp_ovl0",
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0x1400a000,
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233,
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14,
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0,
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0}
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},
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{DISP_MODULE_OVL1,
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DISP_T_OVL,
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"ovl1",
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0,
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NULL,
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{reg_magic,},
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},
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{DISP_MODULE_OVL0_2L,
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DISP_T_OVL,
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"ovl0_2l",
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0,
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NULL,
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{reg_magic,},
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},
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{DISP_MODULE_OVL1_2L,
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DISP_T_OVL,
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"ovl1_2l",
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0,
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NULL,
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{reg_magic,},
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},
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{DISP_MODULE_OVL0_VIRTUAL,
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DISP_T_UNKNOWN,
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"ovl0_virtual",
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0,
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NULL,
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{reg_magic,},
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},
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{DISP_MODULE_OVL0_2L_VIRTUAL,
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DISP_T_UNKNOWN,
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"ovl0_2l_virtual",
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0,
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NULL,
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{reg_magic,},
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},
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{DISP_MODULE_OVL1_2L_VIRTUAL,
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DISP_T_UNKNOWN,
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"ovl1_2l_virtual",
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0,
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NULL,
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{reg_magic,},
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},
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{DISP_MODULE_RDMA0,
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DISP_T_RDMA,
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"rdma0",
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1,
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&ddp_driver_rdma,
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{"mediatek,disp_rdma0",
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0x1400b000,
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234,
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7,
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0,
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0}
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},
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{DISP_MODULE_RDMA1,
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DISP_T_RDMA,
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"rdma1",
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0,
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NULL,
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{reg_magic,},
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},
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{DISP_MODULE_RDMA2,
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DISP_T_RDMA,
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"rdma2",
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0,
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NULL,
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{reg_magic,},
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},
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{DISP_MODULE_WDMA0,
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DISP_T_WDMA,
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"wdma0",
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1,
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&ddp_driver_wdma,
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{"mediatek,disp_wdma0",
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0x1400c000,
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235,
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2,
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0,
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0}
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},
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{DISP_MODULE_WDMA1,
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DISP_T_WDMA,
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"wdma1",
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0,
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NULL,
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{reg_magic,},
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},
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{DISP_MODULE_WDMA_VIRTUAL0,
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DISP_T_UNKNOWN,
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"wdma_virtual0",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_WDMA_VIRTUAL1,
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DISP_T_UNKNOWN,
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"wdma_virtual1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_COLOR0,
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DISP_T_COLOR,
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"color0",
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1,
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&ddp_driver_color,
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{"mediatek,disp_color0",
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0x1400d000,
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236,
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0,
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0,
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0}
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},
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{DISP_MODULE_COLOR1,
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DISP_T_COLOR,
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"color1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_CCORR0,
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DISP_T_CCORR,
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"ccorr0",
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1,
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&ddp_driver_ccorr,
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{"mediatek,disp_ccorr0",
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0x1400e000,
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237,
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1,
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0,
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0}
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},
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{DISP_MODULE_CCORR1,
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DISP_T_CCORR,
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"ccorr1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_AAL0,
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DISP_T_AAL,
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"aal0",
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1,
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&ddp_driver_aal,
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{"mediatek,disp_aal0",
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0x1400f000,
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238,
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1,
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0,
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0}
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},
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{DISP_MODULE_AAL1,
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DISP_T_AAL,
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"aal1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_GAMMA0,
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DISP_T_GAMMA,
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"gamma0",
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1,
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&ddp_driver_gamma,
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{"mediatek,disp_gamma0",
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0x14010000,
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239,
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0,
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0,
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0}
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},
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{DISP_MODULE_GAMMA1,
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DISP_T_GAMMA,
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"gamma1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_OD,
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DISP_T_OD,
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"od",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_DITHER0,
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DISP_T_DITHER,
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"dither0",
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1,
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&ddp_driver_dither,
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{"mediatek,disp_dither0",
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0x14011000,
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240,
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0,
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0,
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0}
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},
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{DISP_MODULE_DITHER1,
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DISP_T_DITHER,
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"dither1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_PATH0,
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DISP_T_UNKNOWN,
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"path0",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_PATH1,
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DISP_T_UNKNOWN,
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"path1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_UFOE,
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DISP_T_UFOE,
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"ufoe",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_UFOE_VIRTUAL,
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DISP_T_UFOE,
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"ufoe",
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1,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_DSC,
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DISP_T_DSC,
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"dsc",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_DSC_2ND,
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DISP_T_DSC,
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"dsc2",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_SPLIT0,
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DISP_T_UNKNOWN,
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"split0",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_DPI,
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DISP_T_DPI,
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"dpi0",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_DBI,
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DISP_T_DBI,
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"dbi0",
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1,
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NULL, /*TODO: will be filled later */
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{"mediatek,dbi0",
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0x14013000,
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242,
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15,
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0,
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0}
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},
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{DISP_MODULE_DSI0,
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DISP_T_DSI,
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"dsi0",
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1,
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&ddp_driver_dsi0,
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{"mediatek,dsi0",
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0x14012000,
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241,
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15,
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0,
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0}
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},
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{DISP_MODULE_DSI1,
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DISP_T_DSI,
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"dsi1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_DSIDUAL,
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DISP_T_DSI,
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"dsidual",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_PWM0,
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DISP_T_PWM,
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"pwm0",
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0,
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&ddp_driver_pwm,
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{"mediatek,disp_pwm0",
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0x1100e000,
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158,
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0,
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0,
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0}
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},
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{DISP_MODULE_PWM1,
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DISP_T_PWM,
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"pwm1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_CONFIG,
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DISP_T_UNKNOWN,
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"config",
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0,
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NULL,
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{"mediatek,mmsys_config",
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0x14000000,
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0,
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0,
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0,
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0}
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},
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{DISP_MODULE_MUTEX,
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DISP_T_UNKNOWN,
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"mutex",
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0,
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NULL,
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{"mediatek,disp_mutex",
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0x14001000,
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226,
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21,
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0,
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0}
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},
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{DISP_MODULE_SMI_COMMON,
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DISP_T_UNKNOWN,
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"sim_common",
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0,
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NULL,
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{"mediatek,smi_common",
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0x14002000,
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0,
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0,
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0,
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0}
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},
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{DISP_MODULE_SMI_LARB0,
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DISP_T_UNKNOWN,
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"smi_larb0",
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0,
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NULL,
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{"mediatek,smi_larb0",
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0x14003000,
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261,
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0,
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0,
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0}
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},
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{DISP_MODULE_SMI_LARB1,
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DISP_T_UNKNOWN,
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"smi_larb1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_MIPI0,
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DISP_T_UNKNOWN,
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"mipi0",
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0,
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NULL,
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{"mediatek,mipi_tx0",
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0x11c80000,
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179,
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0,
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0,
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0}
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},
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{DISP_MODULE_MIPI1,
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DISP_T_UNKNOWN,
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"mipi1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_RSZ0,
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DISP_T_RSZ,
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"rsz0",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_RSZ1,
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DISP_T_RSZ,
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"rsz1",
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0,
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NULL,
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{reg_magic,}
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},
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{DISP_MODULE_UNKNOWN,
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DISP_T_UNKNOWN,
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"unknown",
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0,
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NULL,
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{reg_magic,}
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},
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};
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unsigned int is_ddp_module(enum DISP_MODULE_ENUM module)
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{
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if (module >= 0 && module < DISP_MODULE_NUM)
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return 1;
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return 0;
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}
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unsigned int is_ddp_module_has_reg_info(enum DISP_MODULE_ENUM module)
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{
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if (!is_ddp_module(module))
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return 0;
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if (strcmp(ddp_modules[module].reg_info.reg_dt_name, reg_magic))
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return 1;
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return 0;
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}
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const char *ddp_get_module_name(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module(module))
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return ddp_modules[module].module_name;
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DDPERR("%s: invalid module id=%d\n", __func__, module);
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return "unknown";
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}
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unsigned int _can_connect(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module(module))
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return ddp_modules[module].can_connect;
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DDPDBG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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struct DDP_MODULE_DRIVER *ddp_get_module_driver(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module(module))
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return ddp_modules[module].module_driver;
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DDPDBG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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const char *ddp_get_module_dtname(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module(module))
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return ddp_modules[module].reg_info.reg_dt_name;
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DDPDBG("%s: invalid module id=%d\n", __func__, module);
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return "unknown";
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}
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unsigned int ddp_get_module_checkirq(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
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return ddp_modules[module].reg_info.reg_irq_check;
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DDPDBG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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unsigned long ddp_get_module_pa(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
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return ddp_modules[module].reg_info.reg_pa_check;
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DDPDBG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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unsigned int ddp_get_module_max_irq_bit(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
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return ddp_modules[module].reg_info.irq_max_bit;
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DDPDBG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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unsigned int ddp_is_irq_enable(enum DISP_MODULE_ENUM module)
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{
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if (ddp_get_module_max_irq_bit(module))
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return 1;
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return 0;
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}
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void ddp_module_irq_disable(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module)) {
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ddp_modules[module].reg_info.irq_max_bit = 0;
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return;
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}
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DDPDBG("%s: invalid module id=%d\n", __func__, module);
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}
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void ddp_set_module_va(enum DISP_MODULE_ENUM module, unsigned long va)
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{
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if (is_ddp_module_has_reg_info(module)) {
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ddp_modules[module].reg_info.reg_va = va;
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return;
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}
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DDPDBG("%s: invalid module id=%d\n", __func__, module);
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}
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void ddp_set_module_irq(enum DISP_MODULE_ENUM module, unsigned int irq)
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{
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if (is_ddp_module_has_reg_info(module)) {
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ddp_modules[module].reg_info.reg_irq = irq;
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return;
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}
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DDPDBG("%s: invalid module id=%d\n", __func__, module);
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}
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unsigned long ddp_get_module_va(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
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return ddp_modules[module].reg_info.reg_va;
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return 0;
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}
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unsigned int ddp_get_module_irq(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
|
|
return ddp_modules[module].reg_info.reg_irq;
|
|
|
|
/*("%s: invalid module id=%d\n", __func__, module);*/
|
|
return 0;
|
|
}
|
|
|
|
unsigned int is_reg_addr_valid(unsigned int isVa, unsigned long addr)
|
|
{
|
|
unsigned int i = 0;
|
|
|
|
for (i = 0; i < DISP_MODULE_NUM; i++) {
|
|
if ((isVa == 1) && (addr >= ddp_get_module_va(i)) &&
|
|
(addr < ddp_get_module_va(i) + 0x1000))
|
|
break;
|
|
if ((isVa == 0) && (addr >= ddp_get_module_pa(i)) &&
|
|
(addr < ddp_get_module_pa(i) + 0x1000))
|
|
break;
|
|
}
|
|
|
|
if (i < DISP_MODULE_NUM) {
|
|
DDPMSG("addr valid, isVa=0x%x, addr=0x%lx, module=%s!\n", isVa,
|
|
addr, ddp_get_module_name(i));
|
|
return i;
|
|
}
|
|
|
|
DDPERR("%s: return fail, isVa=0x%x, addr=0x%lx!\n",
|
|
__func__, isVa, addr);
|
|
return 0;
|
|
}
|
|
|
|
unsigned int ddp_get_module_num_by_t(enum DISP_MODULE_TYPE_ENUM module_t)
|
|
{
|
|
int i;
|
|
int cnt = 0;
|
|
|
|
for (i = 0; i < DISP_MODULE_NUM; i++) {
|
|
if (ddp_modules[i].module_type == module_t)
|
|
cnt++;
|
|
}
|
|
|
|
return cnt;
|
|
}
|
|
|
|
enum DISP_MODULE_ENUM
|
|
ddp_get_module_id_by_idx(enum DISP_MODULE_TYPE_ENUM module_t, unsigned int idx)
|
|
{
|
|
int i;
|
|
int index = 0;
|
|
|
|
for (i = 0; i < DISP_MODULE_NUM; i++) {
|
|
if (ddp_modules[i].module_type == module_t)
|
|
index++;
|
|
if (index == (idx + 1))
|
|
return i;
|
|
}
|
|
|
|
return DISP_MODULE_UNKNOWN;
|
|
}
|
|
|
|
enum DISP_MODULE_ENUM disp_irq_to_module(unsigned int irq)
|
|
{
|
|
int i;
|
|
|
|
if (irq == 0)
|
|
return DISP_MODULE_UNKNOWN;
|
|
|
|
for (i = 0; i < DISP_MODULE_NUM; i++) {
|
|
if (irq == ddp_get_module_irq(i))
|
|
return i;
|
|
}
|
|
|
|
DDPERR("cannot find module for irq %d\n", irq);
|
|
WARN_ON(1);
|
|
return DISP_MODULE_UNKNOWN;
|
|
}
|
|
|
|
const char *ddp_get_ioctl_name(enum DDP_IOCTL_NAME ioctl)
|
|
{
|
|
switch (ioctl) {
|
|
case DDP_SWITCH_DSI_MODE:
|
|
return "DDP_SWITCH_DSI_MODE";
|
|
case DDP_STOP_VIDEO_MODE:
|
|
return "DDP_STOP_VIDEO_MODE";
|
|
case DDP_BACK_LIGHT:
|
|
return "DDP_BACK_LIGHT";
|
|
case DDP_SWITCH_LCM_MODE:
|
|
return "DDP_SWITCH_LCM_MODE";
|
|
case DDP_DPI_FACTORY_TEST:
|
|
return "DDP_DPI_FACTORY_TEST";
|
|
case DDP_DSI_IDLE_CLK_CLOSED:
|
|
return "DDP_DSI_IDLE_CLK_CLOSED";
|
|
case DDP_DSI_IDLE_CLK_OPEN:
|
|
return "DDP_DSI_IDLE_CLK_OPEN";
|
|
case DDP_DSI_PORCH_CHANGE:
|
|
return "DDP_DSI_PORCH_CHANGE";
|
|
case DDP_PHY_CLK_CHANGE:
|
|
return "DDP_PHY_CLK_CHANGE";
|
|
case DDP_ENTER_ULPS:
|
|
return "DDP_ENTER_ULPS";
|
|
case DDP_EXIT_ULPS:
|
|
return "DDP_EXIT_ULPS";
|
|
case DDP_RDMA_GOLDEN_SETTING:
|
|
return "DDP_RDMA_GOLDEN_SETTING";
|
|
case DDP_OVL_GOLDEN_SETTING:
|
|
return "DDP_OVL_GOLDEN_SETTING";
|
|
case DDP_PARTIAL_UPDATE:
|
|
return "DDP_PARTIAL_UPDATE";
|
|
case DDP_UPDATE_PLL_CLK_ONLY:
|
|
return "DDP_UPDATE_PLL_CLK_ONLY";
|
|
case DDP_DSI_SW_INIT:
|
|
return "DDP_DSI_SW_INIT";
|
|
case DDP_DSI_MIPI_POWER_ON:
|
|
return "DDP_DSI_MIPI_POWER_ON";
|
|
default:
|
|
break;
|
|
}
|
|
return "unknown";
|
|
}
|