201 lines
3.4 KiB
C
201 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "ddp_reg.h"
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#include "ddp_clkmgr.h"
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#include "ddp_pwm_mux.h"
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#define PWM_MSG(fmt, arg...) pr_debug("[PWM] " fmt "\n", ##arg)
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#define PWM_ERR(fmt, arg...) pr_debug("[PWM] " fmt "\n", ##arg)
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#define PWM_NOTICE(fmt, arg...) pr_debug("[PWM] " fmt "\n", ##arg)
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/*#define BYPASS_CLK_SELECT*/
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/*
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*
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* dummy function
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*
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*/
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#ifdef BYPASS_CLK_SELECT
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int disp_pwm_set_pwmmux(unsigned int clk_req)
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{
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return 0;
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}
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int disp_pwm_clksource_enable(int clk_req)
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{
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return 0;
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}
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int disp_pwm_clksource_disable(int clk_req)
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{
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return 0;
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}
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bool disp_pwm_mux_is_osc(void)
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{
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return false;
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}
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#else
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/*
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*
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* variable for get clock node fromdts
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*
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*/
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static void __iomem *disp_pmw_mux_base;
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#ifndef MUX_DISPPWM_ADDR /* disp pwm source clock select register address */
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#define MUX_DISPPWM_ADDR (disp_pmw_mux_base + 0xB0)
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#endif
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#ifdef HARD_CODE_CONFIG
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/* disp pwm source clock update register address */
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#ifndef MUX_UPDATE_ADDR
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#define MUX_UPDATE_ADDR (disp_pmw_mux_base + 0x4)
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#endif
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#endif
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/* clock hard code access API */
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#define DRV_Reg32(addr) INREG32(addr)
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#define clk_readl(addr) DRV_Reg32(addr)
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#define clk_writel(addr, val) mt_reg_sync_writel(val, addr)
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static int g_pwm_mux_clock_source = -1;
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/*
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*
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* disp pwm source clock select mux api
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*
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*/
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enum DDP_CLK_ID disp_pwm_get_clkid(unsigned int clk_req)
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{
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enum DDP_CLK_ID clkid = -1;
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switch (clk_req) {
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case 0:
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clkid = CLK26M;
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break;
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case 1:
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clkid = UNIVPLL2_D4;
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break;
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case 2:
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clkid = UNIVPLL2_D8;
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break;
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case 3:
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clkid = UNIVPLL3_D8;
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break;
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default:
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clkid = -1;
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break;
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}
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return clkid;
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}
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/*
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*
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* get disp pwm source mux node
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*
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*/
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#define DTSI_TOPCKGEN "mediatek,topckgen"
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static int disp_pwm_get_muxbase(void)
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{
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int ret = 0;
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struct device_node *node;
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if (disp_pmw_mux_base != NULL) {
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PWM_MSG("TOPCKGEN node exist");
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return 0;
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}
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node = of_find_compatible_node(NULL, NULL, DTSI_TOPCKGEN);
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if (!node) {
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PWM_ERR("DISP find TOPCKGEN node failed\n");
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return -1;
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}
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disp_pmw_mux_base = of_iomap(node, 0);
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if (!disp_pmw_mux_base) {
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PWM_ERR("DISP TOPCKGEN base failed\n");
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return -1;
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}
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PWM_MSG("find TOPCKGEN node");
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return ret;
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}
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static unsigned int disp_pwm_get_pwmmux(void)
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{
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unsigned int regsrc = 0;
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if (MUX_DISPPWM_ADDR != NULL)
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regsrc = clk_readl(MUX_DISPPWM_ADDR);
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else
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PWM_ERR("mux addr illegal");
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return regsrc;
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}
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/*
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*
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* disp pwm source clock select mux api
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*
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*/
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int disp_pwm_set_pwmmux(unsigned int clk_req)
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{
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unsigned int reg_before, reg_after;
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enum DDP_CLK_ID clkid = -1;
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clkid = disp_pwm_get_clkid(clk_req);
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disp_pwm_get_muxbase();
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reg_before = disp_pwm_get_pwmmux();
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PWM_NOTICE("clk_req=%d clkid=%d", clk_req, clkid);
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if (clkid != -1) {
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ddp_clk_prepare_enable(MUX_PWM);
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ddp_clk_set_parent(MUX_PWM, clkid);
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ddp_clk_disable_unprepare(MUX_PWM);
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}
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reg_after = disp_pwm_get_pwmmux();
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g_pwm_mux_clock_source = (reg_after) & 0x3;
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PWM_NOTICE("PWM_MUX %x->%x", reg_before, reg_after);
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return 0;
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}
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/*
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*
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* disp pwm clock source power on /power off api
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*
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*/
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int disp_pwm_clksource_enable(int clk_req)
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{
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return 0;
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}
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int disp_pwm_clksource_disable(int clk_req)
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{
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return 0;
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}
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/*
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*
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* disp pwm clock source query api
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*
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*/
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bool disp_pwm_mux_is_osc(void)
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{
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return false;
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}
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#endif /* BYPASS_CLK_SELECT */
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