127 lines
6.1 KiB
C
127 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2019 MediaTek Inc.
|
|
*/
|
|
|
|
#ifndef _DDP_REG_MMSYS_H_
|
|
#define _DDP_REG_MMSYS_H_
|
|
|
|
/* field definition */
|
|
/* ------------------------------------------------------------- */
|
|
/* Config */
|
|
#define DISP_REG_CONFIG_MMSYS_INTEN (DISPSYS_CONFIG_BASE + 0x0)
|
|
#define DISP_REG_CONFIG_MMSYS_INTSTA (DISPSYS_CONFIG_BASE + 0x4)
|
|
#define DISP_REG_CONFIG_MFG_APB_TX_CON (DISPSYS_CONFIG_BASE + 0xc)
|
|
|
|
#define DISP_REG_CONFIG_MMSYS_MISC (DISPSYS_CONFIG_BASE + 0x0F0)
|
|
|
|
#define DISP_REG_CONFIG_MMSYS_SODI_REQ_MASK (DISPSYS_CONFIG_BASE + 0x0F8)
|
|
#define DISP_REG_CONFIG_MMSYS_CG_CON0 (DISPSYS_CONFIG_BASE + 0x100)
|
|
#define DISP_REG_CONFIG_MMSYS_CG_SET0 (DISPSYS_CONFIG_BASE + 0x104)
|
|
#define DISP_REG_CONFIG_MMSYS_CG_CLR0 (DISPSYS_CONFIG_BASE + 0x108)
|
|
#define MMSYS_CG_FLD_FAKE_ENG REG_FLD(1, 11)
|
|
#define DISP_REG_CONFIG_MMSYS_CG_CON1 (DISPSYS_CONFIG_BASE + 0x110)
|
|
#define DISP_REG_CONFIG_MMSYS_CG_SET1 (DISPSYS_CONFIG_BASE + 0x114)
|
|
#define DISP_REG_CONFIG_MMSYS_CG_CLR1 (DISPSYS_CONFIG_BASE + 0x118)
|
|
#define DISP_REG_CONFIG_MMSYS_HW_DCM_1ST_DIS0 (DISPSYS_CONFIG_BASE + 0x120)
|
|
#define DISP_REG_CONFIG_MMSYS_HW_DCM_1ST_DIS_SET0 (DISPSYS_CONFIG_BASE + 0x124)
|
|
#define DISP_REG_CONFIG_MMSYS_HW_DCM_1ST_DIS_CLR0 (DISPSYS_CONFIG_BASE + 0x128)
|
|
#define DISP_REG_CONFIG_MMSYS_HW_DCM_2ST_DIS0 (DISPSYS_CONFIG_BASE + 0x130)
|
|
#define DISP_REG_CONFIG_MMSYS_HW_DCM_2ST_DIS_SET0 (DISPSYS_CONFIG_BASE + 0x134)
|
|
#define DISP_REG_CONFIG_MMSYS_HW_DCM_2ST_DIS_CLR0 (DISPSYS_CONFIG_BASE + 0x138)
|
|
#define DISP_REG_CONFIG_MMSYS_SW0_RST_B (DISPSYS_CONFIG_BASE + 0x140)
|
|
#define DISP_REG_CONFIG_MMSYS_SW1_RST_B (DISPSYS_CONFIG_BASE + 0x144)
|
|
#define DISP_REG_CONFIG_MMSYS_LCM_RST_B (DISPSYS_CONFIG_BASE + 0x150)
|
|
|
|
|
|
#define DISP_REG_CONFIG_PROC_TRACK_EMI_BUSY_CON (DISPSYS_CONFIG_BASE + 0x190)
|
|
|
|
#define DISP_REG_CONFIG_DISP_FAKE_ENG_EN (DISPSYS_CONFIG_BASE + 0x200)
|
|
#define DISP_REG_CONFIG_DISP_FAKE_ENG_RST (DISPSYS_CONFIG_BASE + 0x204)
|
|
#define DISP_REG_CONFIG_DISP_FAKE_ENG_CON0 (DISPSYS_CONFIG_BASE + 0x208)
|
|
#define DISP_REG_CONFIG_DISP_FAKE_ENG_CON1 (DISPSYS_CONFIG_BASE + 0x20c)
|
|
#define DISP_REG_CONFIG_DISP_FAKE_ENG_RD_ADDR (DISPSYS_CONFIG_BASE + 0x210)
|
|
#define DISP_REG_CONFIG_DISP_FAKE_ENG_WR_ADDR (DISPSYS_CONFIG_BASE + 0x214)
|
|
#define DISP_REG_CONFIG_DISP_FAKE_ENG_STATE (DISPSYS_CONFIG_BASE + 0x218)
|
|
|
|
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_CON (DISPSYS_CONFIG_BASE + 0x800)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_DONE (DISPSYS_CONFIG_BASE + 0x804)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_HOLDB (DISPSYS_CONFIG_BASE + 0x808)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_MODE (DISPSYS_CONFIG_BASE + 0x80c)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_FAIL0 (DISPSYS_CONFIG_BASE + 0x810)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_FAIL1 (DISPSYS_CONFIG_BASE + 0x814)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_FAIL2 (DISPSYS_CONFIG_BASE + 0x818)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_FAIL3 (DISPSYS_CONFIG_BASE + 0x81c)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_DEBUG (DISPSYS_CONFIG_BASE + 0x820)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_DIAG_SCANOUT (DISPSYS_CONFIG_BASE + 0x824)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_PRE_FUSE (DISPSYS_CONFIG_BASE + 0x828)
|
|
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_BSEL0 (DISPSYS_CONFIG_BASE + 0x82c)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_BSEL1 (DISPSYS_CONFIG_BASE + 0x830)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_BSEL2 (DISPSYS_CONFIG_BASE + 0x834)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_BSEL3 (DISPSYS_CONFIG_BASE + 0x838)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_HDEN (DISPSYS_CONFIG_BASE + 0x83C)
|
|
|
|
#define DISP_REG_CONFIG_MDP_RDMA0_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x840)
|
|
|
|
#define DISP_REG_CONFIG_MDP_RSZ_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x848)
|
|
|
|
#define DISP_REG_CONFIG_MDP_TDSHP_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x84c)
|
|
|
|
#define DISP_REG_CONFIG_MDP_WROT0_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x854)
|
|
#define DISP_REG_CONFIG_MDP_WDMA0_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x858)
|
|
|
|
#define DISP_REG_CONFIG_DISP_OVL_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x85c)
|
|
|
|
#define DISP_REG_CONFIG_DISP_RDMA_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x864)
|
|
#define DISP_REG_CONFIG_DISP_WDMA0_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x868)
|
|
|
|
#define DISP_REG_CONFIG_DISP_GAMMA_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x870)
|
|
#define DISP_REG_CONFIG_DSI_MEM_DELSEL (DISPSYS_CONFIG_BASE + 0x874)
|
|
|
|
#define DISP_REG_CONFIG_MMSYS_DEBUG_OUT_SEL (DISPSYS_CONFIG_BASE + 0x88C)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_RP_RST_B (DISPSYS_CONFIG_BASE + 0x890)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_RP_FAIL0 (DISPSYS_CONFIG_BASE + 0x894)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_RP_FAIL1 (DISPSYS_CONFIG_BASE + 0x898)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_RP_OK0 (DISPSYS_CONFIG_BASE + 0x89c)
|
|
#define DISP_REG_CONFIG_MMSYS_MBIST_RP_OK1 (DISPSYS_CONFIG_BASE + 0x8A0)
|
|
|
|
#define DISP_REG_CONFIG_MMSYS_DUMMY0 (DISPSYS_CONFIG_BASE + 0x8A4)
|
|
#define DISP_REG_CONFIG_MMSYS_DUMMY1 (DISPSYS_CONFIG_BASE + 0x8A8)
|
|
#define DISP_REG_CONFIG_MMSYS_DUMMY2 (DISPSYS_CONFIG_BASE + 0x8AC)
|
|
#define DISP_REG_CONFIG_MMSYS_DUMMY3 (DISPSYS_CONFIG_BASE + 0x8B0)
|
|
#define DISP_REG_CONFIG_SMI_LARB0_GREQ (DISPSYS_CONFIG_BASE + 0x8DC)
|
|
|
|
|
|
#define DISP_REG_CONFIG_HRT_WEIGHT_READ (DISPSYS_CONFIG_BASE + 0x8F0)
|
|
|
|
#define DISP_REG_CONFIG_MMSYS_MOUT_RST (DISPSYS_CONFIG_BASE + 0xF00)
|
|
|
|
#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN (DISPSYS_CONFIG_BASE + 0xF0C)
|
|
#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN (DISPSYS_CONFIG_BASE + 0xF1C)
|
|
|
|
#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN (DISPSYS_CONFIG_BASE + 0xF20)
|
|
#define DISP_REG_CONFIG_DISP_COLOR_SEL_IN (DISPSYS_CONFIG_BASE + 0xF24)
|
|
#define DISP_REG_CONFIG_DISP_DBI_SEL_IN (DISPSYS_CONFIG_BASE + 0xF28)
|
|
#define DISP_REG_CONFIG_DISP_WDMA0_SEL_IN (DISPSYS_CONFIG_BASE + 0xF2C)
|
|
#define DISP_REG_CONFIG_DISP_DSI0_SEL_IN (DISPSYS_CONFIG_BASE + 0xF30)
|
|
|
|
|
|
#define DISP_REG_CONFIG_DISP_UFOE_SEL_IN (DISPSYS_CONFIG_BASE + 0xF48)
|
|
#define DISP_REG_CONFIG_DISP_DITHER_MOUT_EN (DISPSYS_CONFIG_BASE + 0xF4C)
|
|
|
|
#define DISP_REG_CONFIG_DISP_DL_VALID_0 (DISPSYS_CONFIG_BASE + 0xF58)
|
|
#define DISP_REG_CONFIG_DISP_DL_VALID_1 (DISPSYS_CONFIG_BASE + 0xF5C)
|
|
|
|
|
|
#define DISP_REG_CONFIG_DISP_DL_READY_0 (DISPSYS_CONFIG_BASE + 0xF60)
|
|
#define DISP_REG_CONFIG_DISP_DL_READY_1 (DISPSYS_CONFIG_BASE + 0xF64)
|
|
|
|
|
|
|
|
/* field definition */
|
|
/* ------------------------------------------------------------- */
|
|
|
|
#endif
|