250 lines
7.0 KiB
C
250 lines
7.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DDP_DRV_H__
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#define __DDP_DRV_H__
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#include <linux/ioctl.h>
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#include "ddp_hal.h"
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#include "ddp_info.h"
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#include "ddp_aal.h"
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#include "ddp_gamma.h"
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#include "ddp_pq.h"
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struct DISP_WRITE_REG {
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unsigned int reg;
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unsigned int val;
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unsigned int mask;
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};
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struct DISP_READ_REG {
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unsigned int reg;
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unsigned int val;
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unsigned int mask;
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};
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struct DISP_EXEC_COMMAND {
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int taskID;
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uint32_t scenario;
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uint32_t priority;
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uint32_t engineFlag;
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uint32_t *pFrameBaseSW;
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uint32_t *pTileBaseSW;
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uint32_t blockSize;
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};
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/* PQ */
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#define COLOR_TUNING_INDEX 19
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#define THSHP_PARAM_MAX 146 /* TDSHP_3_0 */
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#define PARTIAL_Y_INDEX 10
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#define GLOBAL_SAT_SIZE 10
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#define CONTRAST_SIZE 10
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#define BRIGHTNESS_SIZE 10
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#define PARTIAL_Y_SIZE 16
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#define PQ_HUE_ADJ_PHASE_CNT 4
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#define PQ_SAT_ADJ_PHASE_CNT 4
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#define PQ_PARTIALS_CONTROL 5
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#define PURP_TONE_SIZE 3
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#define SKIN_TONE_SIZE 8 /* (-6) */
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#define GRASS_TONE_SIZE 6 /* (-2) */
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#define SKY_TONE_SIZE 3
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#define CCORR_COEF_CNT 4 /* ccorr feature */
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enum DISP_INTERLACE_FORMAT {
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DISP_INTERLACE_FORMAT_NONE,
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DISP_INTERLACE_FORMAT_TOP_FIELD,
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DISP_INTERLACE_FORMAT_BOTTOM_FIELD
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};
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struct device *disp_get_device(void);
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#ifdef CONFIG_MTK_IOMMU_V2
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#define DISP_LARB_COUNT 1
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struct disp_iommu_device {
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struct platform_device *larb_pdev[DISP_LARB_COUNT];
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struct platform_device *iommu_pdev;
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unsigned int inited;
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};
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struct disp_iommu_device *disp_get_iommu_dev(void);
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#endif
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#define DISP_IOCTL_MAGIC 'x'
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/* also defined in atci_pq_cmd.h */
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#define DISP_IOCTL_WRITE_REG \
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_IOW(DISP_IOCTL_MAGIC, 1, struct DISP_WRITE_REG)
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#define DISP_IOCTL_READ_REG \
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_IOWR(DISP_IOCTL_MAGIC, 2, struct DISP_READ_REG)
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#define DISP_IOCTL_DUMP_REG \
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_IOR(DISP_IOCTL_MAGIC, 4, int)
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#define DISP_IOCTL_LOCK_THREAD \
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_IOR(DISP_IOCTL_MAGIC, 5, int)
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#define DISP_IOCTL_UNLOCK_THREAD \
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_IOR(DISP_IOCTL_MAGIC, 6, int)
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#define DISP_IOCTL_MARK_CMQ \
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_IOR(DISP_IOCTL_MAGIC, 7, int)
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#define DISP_IOCTL_WAIT_CMQ \
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_IOR(DISP_IOCTL_MAGIC, 8, int)
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#define DISP_IOCTL_SYNC_REG \
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_IOR(DISP_IOCTL_MAGIC, 9, int)
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#define DISP_IOCTL_LOCK_MUTEX \
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_IOW(DISP_IOCTL_MAGIC, 20, int)
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#define DISP_IOCTL_UNLOCK_MUTEX \
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_IOR(DISP_IOCTL_MAGIC, 21, int)
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#define DISP_IOCTL_LOCK_RESOURCE \
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_IOW(DISP_IOCTL_MAGIC, 25, int)
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#define DISP_IOCTL_UNLOCK_RESOURCE \
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_IOR(DISP_IOCTL_MAGIC, 26, int)
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#define DISP_IOCTL_SET_INTR \
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_IOR(DISP_IOCTL_MAGIC, 10, int)
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#define DISP_IOCTL_TEST_PATH \
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_IOR(DISP_IOCTL_MAGIC, 11, int)
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#define DISP_IOCTL_CLOCK_ON \
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_IOR(DISP_IOCTL_MAGIC, 12, int)
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#define DISP_IOCTL_CLOCK_OFF \
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_IOR(DISP_IOCTL_MAGIC, 13, int)
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#define DISP_IOCTL_RUN_DPF \
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_IOW(DISP_IOCTL_MAGIC, 30, int)
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#define DISP_IOCTL_CHECK_OVL \
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_IOR(DISP_IOCTL_MAGIC, 31, int)
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#define DISP_IOCTL_EXEC_COMMAND \
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_IOW(DISP_IOCTL_MAGIC, 33, struct DISP_EXEC_COMMAND)
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#define DISP_IOCTL_RESOURCE_REQUIRE \
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_IOR(DISP_IOCTL_MAGIC, 34, int)
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/* Add for AAL control - S */
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/* 0 : disable AAL event, 1 : enable AAL event */
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#define DISP_IOCTL_AAL_EVENTCTL \
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_IOW(DISP_IOCTL_MAGIC, 15, int)
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/* Get AAL statistics data. */
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#define DISP_IOCTL_AAL_GET_HIST \
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_IOR(DISP_IOCTL_MAGIC, 16, struct DISP_AAL_HIST)
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/* Update AAL setting */
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#define DISP_IOCTL_AAL_SET_PARAM \
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_IOW(DISP_IOCTL_MAGIC, 17, struct DISP_AAL_PARAM)
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#define DISP_IOCTL_AAL_INIT_REG \
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_IOW(DISP_IOCTL_MAGIC, 18, struct DISP_AAL_INITREG)
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#define DISP_IOCTL_SET_SMARTBACKLIGHT \
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_IOW(DISP_IOCTL_MAGIC, 19, int)
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/* Add for AAL control - E */
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#define DISP_IOCTL_SET_GAMMALUT \
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_IOW(DISP_IOCTL_MAGIC, 23, struct DISP_GAMMA_LUT_T)
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#define DISP_IOCTL_SET_CCORR \
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_IOW(DISP_IOCTL_MAGIC, 24, struct DISP_CCORR_COEF_T)
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/* Add for PQ transition control */
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/* 0 : disable CCORR event, 1 : enable CCORR event */
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#define DISP_IOCTL_CCORR_EVENTCTL \
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_IOW(DISP_IOCTL_MAGIC, 110, int)
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/* Get CCORR interrupt */
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#define DISP_IOCTL_CCORR_GET_IRQ \
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_IOR(DISP_IOCTL_MAGIC, 111, int)
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#define DISP_IOCTL_SUPPORT_COLOR_TRANSFORM \
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_IOW(DISP_IOCTL_MAGIC, 112, struct DISP_COLOR_TRANSFORM)
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/*---------------------------------------------------------------------------*/
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/* DDP Kernel Mode API (for Kernel Trap) */
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/* --------------------------------------------------------------------------*/
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/* DDPK Bitblit */
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#define DISP_IOCTL_SET_CLKON \
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_IOW(DISP_IOCTL_MAGIC, 50, enum DISP_MODULE_ENUM)
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#define DISP_IOCTL_SET_CLKOFF \
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_IOW(DISP_IOCTL_MAGIC, 51, enum DISP_MODULE_ENUM)
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#define DISP_IOCTL_MUTEX_CONTROL \
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_IOW(DISP_IOCTL_MAGIC, 55, int) /* also defined in atci_pq_cmd.h */
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#define DISP_IOCTL_GET_LCMINDEX \
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_IOR(DISP_IOCTL_MAGIC, 56, int)
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/* PQ setting */
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#define DISP_IOCTL_SET_PQPARAM \
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_IOW(DISP_IOCTL_MAGIC, 60, struct DISP_PQ_PARAM)
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#define DISP_IOCTL_GET_PQPARAM \
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_IOR(DISP_IOCTL_MAGIC, 61, struct DISP_PQ_PARAM)
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#define DISP_IOCTL_GET_PQINDEX \
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_IOR(DISP_IOCTL_MAGIC, 63, struct DISPLAY_PQ_T)
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#define DISP_IOCTL_SET_PQINDEX \
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_IOW(DISP_IOCTL_MAGIC, 64, struct DISPLAY_PQ_T)
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#define DISP_IOCTL_SET_TDSHPINDEX \
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_IOW(DISP_IOCTL_MAGIC, 65, struct DISPLAY_TDSHP_T)
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#define DISP_IOCTL_GET_TDSHPINDEX \
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_IOR(DISP_IOCTL_MAGIC, 66, struct DISPLAY_TDSHP_T)
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#define DISP_IOCTL_SET_PQ_CAM_PARAM \
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_IOW(DISP_IOCTL_MAGIC, 67, struct DISP_PQ_PARAM)
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#define DISP_IOCTL_GET_PQ_CAM_PARAM \
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_IOR(DISP_IOCTL_MAGIC, 68, struct DISP_PQ_PARAM)
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#define DISP_IOCTL_SET_PQ_GAL_PARAM \
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_IOW(DISP_IOCTL_MAGIC, 69, struct DISP_PQ_PARAM)
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#define DISP_IOCTL_GET_PQ_GAL_PARAM \
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_IOR(DISP_IOCTL_MAGIC, 70, struct DISP_PQ_PARAM)
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#define DISP_IOCTL_PQ_SET_BYPASS_COLOR \
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_IOW(DISP_IOCTL_MAGIC, 71, int)
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#define DISP_IOCTL_PQ_SET_WINDOW \
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_IOW(DISP_IOCTL_MAGIC, 72, struct DISP_PQ_WIN_PARAM)
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#define DISP_IOCTL_PQ_GET_TDSHP_FLAG \
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_IOR(DISP_IOCTL_MAGIC, 73, int)
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#define DISP_IOCTL_PQ_SET_TDSHP_FLAG \
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_IOW(DISP_IOCTL_MAGIC, 74, int)
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#define DISP_IOCTL_PQ_GET_DC_PARAM \
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_IOR(DISP_IOCTL_MAGIC, 75, struct DISP_PQ_DC_PARAM)
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#define DISP_IOCTL_PQ_SET_DC_PARAM \
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_IOW(DISP_IOCTL_MAGIC, 76, struct DISP_PQ_DC_PARAM)
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#define DISP_IOCTL_WRITE_SW_REG \
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_IOW(DISP_IOCTL_MAGIC, 77, struct DISP_WRITE_REG)
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#define DISP_IOCTL_READ_SW_REG \
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_IOWR(DISP_IOCTL_MAGIC, 78, struct DISP_READ_REG)
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#define DISP_IOCTL_SET_COLOR_REG \
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_IOWR(DISP_IOCTL_MAGIC, 79, struct DISPLAY_COLOR_REG)
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/* OD */
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#define DISP_IOCTL_OD_CTL \
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_IOWR(DISP_IOCTL_MAGIC, 80, struct DISP_OD_CMD)
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/* OVL */
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#define DISP_IOCTL_OVL_ENABLE_CASCADE \
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_IOW(DISP_IOCTL_MAGIC, 90, int)
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#define DISP_IOCTL_OVL_DISABLE_CASCADE \
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_IOW(DISP_IOCTL_MAGIC, 91, int)
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/*PQ setting*/
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#define DISP_IOCTL_PQ_GET_DS_PARAM \
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_IOR(DISP_IOCTL_MAGIC, 100, struct DISP_PQ_DS_PARAM)
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#define DISP_IOCTL_PQ_GET_MDP_COLOR_CAP \
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_IOR(DISP_IOCTL_MAGIC, 101, struct MDP_COLOR_CAP)
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#define DISP_IOCTL_PQ_GET_MDP_TDSHP_REG \
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_IOR(DISP_IOCTL_MAGIC, 102, struct MDP_TDSHP_REG)
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/*secure video path implementation: the handle value*/
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#define DISP_IOCTL_SET_TPLAY_HANDLE \
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_IOW(DISP_IOCTL_MAGIC, 200, unsigned int)
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int disp_get_ovl_bandwidth(unsigned long long in_fps,
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unsigned long long out_fps,
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unsigned long long *bandwidth);
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int disp_get_rdma_bandwidth(unsigned long long out_fps,
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unsigned long long *bandwidth);
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#endif
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