459 lines
10 KiB
C
459 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DDP_REG_DBI_H_
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#define _DDP_REG_DBI_H_
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/* field definition */
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/* ------------------------------------------------------------- */
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struct DBI_REG_STATUS {
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unsigned RUN:1;
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unsigned rsv_1:1;
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unsigned WAIT_HTT:1;
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unsigned WAIT_SYNC:1;
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unsigned BUSY:1;
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unsigned rsv_5:27;
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};
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struct DBI_REG_INTERRUPT {
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unsigned COMPLETED:1;
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unsigned rsv_1:1;
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unsigned HTT:1;
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unsigned SYNC:1;
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unsigned TE:1;
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unsigned TIMEOUT:1;
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unsigned rsv_6:26;
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};
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struct DBI_REG_START {
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unsigned RESET:1;
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unsigned rsv_1:14;
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unsigned START:1;
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unsigned rsv_16:16;
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};
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struct DBI_SIF_PIX_CON_REG {
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unsigned SIF0_2PIN_SIZE:3;
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unsigned rsv_3:1;
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unsigned SIF0_PIX_2PIN:1;
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unsigned SIF0_PARA_2PIN:1;
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unsigned SIF0_SINGLE_A0:1;
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unsigned SIF0_CS_STAY_LOW:1;
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unsigned SIF1_2PIN_SIZE:3;
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unsigned rsv_11:1;
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unsigned SIF1_PIX_2PIN:1;
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unsigned SIF1_PARA_2PIN:1;
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unsigned SIF1_SINGLE_A0:1;
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unsigned SIF1_CS_STAY_LOW:1;
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unsigned rsv_16:16;
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};
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struct DBI_SIF_TIMING_REG {
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unsigned WR_2ND:4;
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unsigned WR_1ST:4;
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unsigned RD_2ND:4;
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unsigned RD_1ST:4;
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unsigned CSH:4;
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unsigned CSS:4;
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unsigned rsv_24:8;
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};
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struct DBI_SCNF_REG {
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unsigned SIZE_0:3;
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unsigned THREE_WIRE_0:1;
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unsigned SDI_0:1;
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unsigned FIRST_POL_0:1;
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unsigned SCK_DEF_0:1;
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unsigned DIV2_0:1;
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unsigned SIZE_1:3;
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unsigned THREE_WIRE_1:1;
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unsigned SDI_1:1;
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unsigned FIRST_POL_1:1;
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unsigned SCK_DEF_1:1;
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unsigned DIV2_1:1;
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unsigned rsv_16:8;
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unsigned HW_CS:1;
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unsigned VDO_MODE:1;
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unsigned CMD_LOCK:1;
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unsigned VDO_AUTO:1;
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unsigned SYNC_ALIGN:1;
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unsigned DDR_EN_CONFIG:1;
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unsigned rsv_30:2;
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};
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struct DBI_REG_PCNF {
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unsigned WST:6;
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unsigned rsv_6:2;
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unsigned C2WS:4;
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unsigned C2WH:4;
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unsigned RLT:6;
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unsigned rsv_22:2;
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unsigned C2RS:4;
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unsigned C2RH:4;
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};
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struct DBI_REG_PCNFDW {
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unsigned PCNF0_DW:3;
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unsigned rsv_3:1;
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unsigned PCNF1_DW:3;
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unsigned rsv_7:1;
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unsigned PCNF2_DW:3;
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unsigned rsv_11:5;
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unsigned PCNF0_CHW:4;
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unsigned PCNF1_CHW:4;
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unsigned PCNF2_CHW:4;
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unsigned rsv_28:4;
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};
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struct DBI_TECON_REG {
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unsigned ENABLE:1;
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unsigned EDGE_SEL:1;
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unsigned MODE:1;
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unsigned TE_REPEAT:1;
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unsigned rsv_4:11;
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unsigned SW_TE:1;
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unsigned rsv_16:16;
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};
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struct DBI_ROI_SIZE_REG {
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unsigned WIDTH:11;
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unsigned rsv_11:5;
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unsigned HEIGHT:11;
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unsigned rsv_27:5;
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};
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struct DBI_ROI_CADD_REG {
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unsigned rsv_0:4;
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unsigned addr:4;
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unsigned rsv_8:24;
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};
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struct DBI_ROI_DADD_REG {
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unsigned rsv_0:4;
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unsigned addr:4;
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unsigned rsv_8:24;
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};
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struct DBI_ROICON_REG {
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unsigned RGB_ORDER:1;
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unsigned SIGNIFICANCE:1;
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unsigned PADDING:1;
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unsigned DATA_FMT:3;
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unsigned IF_SIZE:2;
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unsigned rsv_8:16;
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unsigned SEND_RES_MODE:1;
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unsigned IF_24:1;
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unsigned rsv_26:6;
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};
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struct DBI_REG_SMICON {
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unsigned MAX_BURST:3;
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unsigned rsv_3:1;
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unsigned THROTTLE_EN:1;
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unsigned rsv_5:11;
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unsigned THROTTLE_PERIOD:16;
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};
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struct DBI_REG_DITHER_CON {
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unsigned DB_B:2;
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unsigned rsv_2:2;
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unsigned DB_G:2;
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unsigned rsv_6:2;
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unsigned DB_R:2;
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unsigned rsv_10:2;
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unsigned LFSR_B_SEED:4;
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unsigned LFSR_G_SEED:4;
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unsigned LFSR_R_SEED:4;
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unsigned rsv_24:8;
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};
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struct DBI_REG_SCNF_CS {
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unsigned CS0:1;
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unsigned CS1:1;
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unsigned CS2:1;
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unsigned rsv_3:29;
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};
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struct DBI_REG_CALC_HTT {
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unsigned TIME_OUT:12;
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unsigned rsv_12:4;
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unsigned COUNT:12;
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unsigned rsv_28:4;
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};
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struct DBI_REG_SYNC_LCM_SIZE {
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unsigned HTT:10;
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unsigned rsv_10:6;
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unsigned VTT:12;
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unsigned rsv_28:4;
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};
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struct DBI_REG_SYNC_CNT {
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unsigned WAITLINE:12;
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unsigned rsv_12:4;
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unsigned SCANLINE:12;
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unsigned rsv_28:4;
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};
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struct DBI_STALL_CG_CON {
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unsigned GEN_CG:1;
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unsigned DBI_SCK_CG:1;
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unsigned DBIP_PCK_CG:1;
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unsigned CHKSUM_CG:1;
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unsigned MAINCON_CG:1;
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unsigned SYNC_CG:1;
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unsigned SYNC_TE_CG:1;
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unsigned SRCMUX_CG:1;
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unsigned DITHER_CG:1;
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unsigned SOF_MASK_CG:1;
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unsigned rsv_10:22;
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};
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struct DBI_REG_CONSUME_RATE {
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unsigned CONSUME_PXLSRW:10;
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unsigned rsv_10:22;
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};
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struct DBI_REG_DBI_ULTRA_TH {
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unsigned DBI_TH_LOW:16;
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unsigned DBI_TH_HIGH:16;
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};
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struct DBI_REG_DBI_DB {
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unsigned XOFF:11;
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unsigned rsv_11:5;
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unsigned YOFF:11;
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unsigned rsv_27:5;
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};
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struct DBI_REG_DBIS_CHKSUM {
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unsigned DBIS_CHEKSUM:24;
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unsigned rsv_24:7;
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unsigned CHK_ENABLE:1;
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};
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struct DBI_REG_DBIP_CHKSUM {
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unsigned DBIP_CHEKSUM:24;
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unsigned rsv_24:8;
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};
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struct DBI_REG_INT_PATTERN {
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unsigned PAT_EN:1;
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unsigned MASK_B:1;
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unsigned MASK_G:1;
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unsigned MASK_R:1;
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unsigned PAT_SEL:3;
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unsigned rsv_7:1;
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unsigned B_MAN:8;
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unsigned G_MAN:8;
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unsigned R_MAN:8;
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};
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struct DBI_REG_PRDY_PROT {
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unsigned TIMEOUT_VAL:16;
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unsigned TIMEOUT_EN:1;
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unsigned rsv_17:15;
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};
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struct DBI_REG_STR_BYTE_CON {
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unsigned SIF0_DATA_SIZE:3;
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unsigned rsv_3:3;
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unsigned SIF0_BYTE_SWITCH:1;
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unsigned SIF0_BYTE_MODE:1;
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unsigned SIF1_DATA_SIZE:3;
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unsigned rsv_11:3;
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unsigned SIF1_BYTE_SWITCH:1;
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unsigned SIF1_BYTE_MODE:1;
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unsigned rsv_16:15;
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unsigned SW_RST_EVEN:1;
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};
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struct DBI_REG_WR_STR_BYTE {
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unsigned SIF0_BYTE:8;
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unsigned SIF1_BYTE:8;
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unsigned SIF0_BYTE2:8;
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unsigned SIF1_BYT2:8;
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};
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struct DBI_REG_RD_STR_BYTE {
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unsigned SIF0_RD_BYTE:8;
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unsigned SIF1_RD_BYTE:8;
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unsigned rsv_16:16;
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};
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struct DBI_REG_VDO_SYNC_CON0 {
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unsigned CYCLE_PER_PIX:8;
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unsigned rsv_8:8;
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unsigned VBP_PIX_NUM:8;
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unsigned VBP_LN_NUM:8;
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};
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struct DBI_REG_VDO_SYNC_CON1 {
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unsigned HFP_PIX_NUM:8;
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unsigned HFP_LN_NUM:8;
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unsigned HBP_PIX_NUM:8;
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unsigned HBP_LN_NUM:8;
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};
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struct DBI_REG_VDO_HEADER {
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unsigned VDO_LN_STR_HDR:16;
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unsigned VDO_FR_STR_HDR:16;
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};
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struct DBI_REG_PAD_SEL {
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unsigned LSDI_SEL:3;
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unsigned rsv_3:13;
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unsigned LSDA_SEL:3;
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unsigned rsv_19:13;
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};
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struct DBI_REG_PAD_DELAY_SEL {
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unsigned GP0_DELAY:2;
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unsigned GP1_DELAY:2;
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unsigned GP2_DELAY:2;
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unsigned GP3_DELAY:2;
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unsigned rsv_8:24;
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};
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struct DBI_REG_PAD_CON {
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unsigned SW_CON:1;
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unsigned SW_SEL:1;
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unsigned rsv_2:30;
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};
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struct DBI_REG_DITHER0 {
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unsigned START:1;
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unsigned rsv_1:3;
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unsigned OUT_SEL:1;
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unsigned rsv_5:3;
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unsigned FRAME_DONE:8;
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unsigned CRC_CEN:1;
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unsigned rsv_17:3;
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unsigned CRC_START:1;
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unsigned rsv_21:3;
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unsigned CRC_CLR:1;
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unsigned rsv_25:7;
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};
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struct DBI_REG_DITHER5 {
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unsigned W_DEMO:16;
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unsigned rsv_16:16;
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};
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struct DBI_REG_GMC_ULTRA_TH {
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unsigned GMC_TH_LOW:16;
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unsigned GMC_TH_HIGH:16;
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};
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struct DBI_REGS {
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struct DBI_REG_STATUS DBI_STA; /* 3000 */
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struct DBI_REG_INTERRUPT INT_ENABLE; /* 3004 */
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struct DBI_REG_INTERRUPT INT_STATUS; /* 3008 */
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struct DBI_REG_START DBI_START; /* 300C */
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UINT32 RESET; /* 3010 */
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UINT32 rsv_3014; /* 3014 */
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struct DBI_SIF_PIX_CON_REG DBI_SIF_PIX_CON; /* 3018 */
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struct DBI_SIF_TIMING_REG SIF_TIMING[2]; /* 301C..3020 */
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UINT32 rsv_3024; /* 3024 */
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struct DBI_SCNF_REG DBI_SCNF; /* 3028 */
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struct DBI_REG_SCNF_CS SCNF_CS; /* 302C */
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struct DBI_REG_PCNF PARALLEL_CFG[3]; /* 3030..3038 */
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struct DBI_REG_PCNFDW PARALLEL_DW; /* 303C */
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struct DBI_TECON_REG DBI_TECON; /* 3040 */
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struct DBI_REG_CALC_HTT CALC_HTT; /* 3044 */
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struct DBI_REG_SYNC_LCM_SIZE SYNC_LCM_SIZE; /* 3048 */
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struct DBI_REG_SYNC_CNT SYNC_CNT; /* 304C */
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UINT32 rsv_0054[2]; /* 3050 3054 */
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UINT32 DBI_PCFG; /* 3058 */
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UINT32 rsv_005C; /* 305C */
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struct DBI_ROICON_REG DBI_ROICON; /* 3060 */
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struct DBI_ROI_CADD_REG DBI_ROI_CADD; /* 3064 */
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struct DBI_ROI_DADD_REG DBI_ROI_DADD; /* 3068 */
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struct DBI_ROI_SIZE_REG DBI_ROI_SIZE; /* 306C */
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struct DBI_STALL_CG_CON STALL_CG_CON; /* 3070 */
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UINT32 rsv_3074[3]; /* 3074..307C */
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struct DBI_REG_DITHER_CON DITHER_CON; /* 3080 */
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UINT32 DITHER_CFG; /* 3084 */
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UINT32 FRAME_DONE; /* 3088 */
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UINT32 rsv_308C; /* 308C */
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UINT32 ULTRA_CON; /* 3090 */
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struct DBI_REG_CONSUME_RATE CONSUME_RATE; /* 3094 */
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struct DBI_REG_DBI_ULTRA_TH DBI_ULTRA_TH; /* 3098 */
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UINT32 rsv_309C[3]; /* 309C,A0,A4 */
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struct DBI_REG_DBI_DB DBI_DB; /* 30A8 */
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UINT32 rsv_30AC[13]; /* 30AC..30DC */
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struct DBI_REG_DBIS_CHKSUM DBIS_CHKSUM; /* 30E0 */
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struct DBI_REG_DBIP_CHKSUM DBIP_CHKSUM; /* 30E4 */
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struct DBI_REG_INT_PATTERN INT_PATTERN; /* 30E8 */
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UINT32 rsv_30EC[93]; /* 30EC~325C */
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struct DBI_REG_PRDY_PROT PRDY_PROT; /* 3260 */
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UINT32 rsv_3264[3]; /* 3264~326C */
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struct DBI_REG_STR_BYTE_CON STR_BYTE_CON; /* 3270 */
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UINT32 rsv_3274; /* 3274 */
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struct DBI_REG_WR_STR_BYTE WR_STR_BYTE; /* 3278 */
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struct DBI_REG_RD_STR_BYTE RD_STR_BYTE; /* 327C */
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UINT32 rsv_3280[4]; /* 3280~328C */
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struct DBI_REG_VDO_SYNC_CON0 VDO_SYNC_CON0; /* 3290 */
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struct DBI_REG_VDO_SYNC_CON1 VDO_SYNC_CON1; /* 3294 */
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UINT32 FR_DURATION; /* 3298 */
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struct DBI_REG_VDO_HEADER VDO_HEADER; /* 329C */
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UINT32 rsv_32a0[24]; /* 32a0~32FC */
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struct DBI_REG_PAD_SEL PAD_SEL; /* 3300 */
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struct DBI_REG_PAD_DELAY_SEL PAD_DELAY_SEL; /* 3304 */
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UINT32 rsv_3308[2]; /* 3308,330C */
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struct DBI_REG_PAD_CON PAD_CON; /* 3310 */
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UINT32 rsv_3314[699]; /* 3314~,3DFC */
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struct DBI_REG_DITHER0 DITHER0; /* 3E00 */
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UINT32 rsv_3E04[4]; /* 3E04 ~3E10 */
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struct DBI_REG_DITHER5 DITHER5; /* 3E14 */
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UINT32 DITHER6; /* 3E18 */
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UINT32 DITHER7; /* 3E1C */
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UINT32 DITHER8; /* 3E20 */
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UINT32 DITHER9; /* 3E24 */
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UINT32 DITHER10; /* 3E28 */
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UINT32 DITHE11; /* 3E2C */
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UINT32 DITHER12; /* 3E30 */
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UINT32 DITHER13; /* 3E34 */
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UINT32 DITHER14; /* 3E38 */
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UINT32 DITHE15; /* 3E3C */
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UINT32 DITHER16; /* 3E40 */
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UINT32 DITHER17; /* 3E44 */
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UINT32 rsv_3E48[46]; /* 3E48 ~3EFC */
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UINT32 DBI_PCMD0; /* 3F00 */
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UINT32 rsv_3F04[3]; /* 3F04 3F0C */
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UINT32 DBI_PDAT0; /* 3F10 */
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UINT32 rsv_3F14[3]; /* 3F14 3F1C */
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UINT32 DBI_PCMD1; /* 3F20 */
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UINT32 rsv_3F24[3]; /* 3F24 3F2C */
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UINT32 DBI_PDAT1; /* 3F30 */
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UINT32 rsv_3F34[3]; /* 3F34 3F3C */
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UINT32 DBI_PCMD2; /* 3F40 */
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UINT32 rsv_3F44[3]; /* 3F44 3F4C */
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UINT32 DBI_PDAT2; /* 3F50 */
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UINT32 rsv_3F54[11]; /* 3F54 3F7C */
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UINT32 DBI_SCMD0; /* 3F80 */
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UINT32 rsv_3F84; /* 3F84 */
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UINT32 DBI_SPE_SCMD0; /* 3F88 */
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UINT32 rsv_3F8C; /* 3F8C */
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UINT32 DBI_SDAT0; /* 3F90 */
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UINT32 rsv_3F94; /* 3F94 */
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UINT32 DBI_SPE_SDAT0; /* 3F98 */
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UINT32 rsv_3F9C; /* 3F9C */
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UINT32 DBI_SCMD1; /* 3FA0 */
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UINT32 rsv_3FA4; /* 3FA4 */
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UINT32 DBI_SPE_SCMD1; /* 3FA8 */
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UINT32 rsv_3FAC; /* 3FAC */
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UINT32 DBI_SDAT1; /* 3FB0 */
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UINT32 rsv_3FB4; /* 3FB4 */
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UINT32 DBI_SPE_SDAT1; /* 3FB8 */
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};
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#endif /* _DDP_REG_DBI_H_ */
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