688 lines
16 KiB
C
688 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/types.h>
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#include <linux/io.h>
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/* #include "mt-plat/sync_write.h" */
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#include "ddp_reg.h"
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#include "ddp_info.h"
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#include "ddp_log.h"
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#include "primary_display.h"
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#include "ddp_clkmgr.h"
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#ifdef CONFIG_MTK_SMI_EXT
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#include "smi_public.h"
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#endif
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#define DRV_Reg32(addr) INREG32(addr)
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#define clk_readl(addr) DRV_Reg32(addr)
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#define clk_writel(addr, val) writel(val, addr)
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#define clk_setl(addr, val) writel(clk_readl(addr) | (val), addr)
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#define clk_clrl(addr, val) writel(clk_readl(addr) & ~(val), addr)
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/**
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* display clk table
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* -- by chip
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* struct clk *pclk;
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* const char *clk_name;
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* int refcnt;
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* unsigned int belong_to: bit 0: main display, bit 1: externel display
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* enum DISP_MODULE_ENUM module_id;
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*/
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static struct ddp_clk ddp_clks[MAX_DISP_CLK_CNT] = {
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/* top clk */
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[CLK_MM_MTCMOS] = {
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NULL, "CLK_MM_MTCMOS", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_SMI_COMMON] = {
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NULL, "CLK_SMI_COMMON", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_SMI_LARB0] = {
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NULL, "CLK_SMI_LARB0", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_SMI_LARB1] = {
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NULL, "CLK_SMI_LARB1", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_GALS_COMM0] = {
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NULL, "CLK_GALS_COMM0", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_GALS_COMM1] = {
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NULL, "CLK_GALS_COMM1", 0, (0), DISP_MODULE_UNKNOWN},
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/* module clk */
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[CLK_DISP_OVL0] = {
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NULL, "CLK_DISP_OVL0", 0, (1), DISP_MODULE_OVL0},
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[CLK_DISP_OVL0_2L] = {
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NULL, "CLK_DISP_OVL0_2L", 0, (1), DISP_MODULE_OVL0_2L},
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[CLK_DISP_OVL1_2L] = {
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NULL, "CLK_DISP_OVL1_2L", 0, (1<<1|1<<2), DISP_MODULE_OVL1_2L},
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[CLK_DISP_RDMA0] = {
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NULL, "CLK_DISP_RDMA0", 0, (1), DISP_MODULE_RDMA0},
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[CLK_DISP_RDMA1] = {
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NULL, "CLK_DISP_RDMA1", 0, (1<<1), DISP_MODULE_RDMA1},
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[CLK_DISP_WDMA0] = {
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NULL, "CLK_DISP_WDMA0", 0, (1|1<<2), DISP_MODULE_WDMA0},
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[CLK_DISP_COLOR0] = {
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NULL, "CLK_DISP_COLOR0", 0, (1), DISP_MODULE_COLOR0},
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[CLK_DISP_CCORR0] = {
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NULL, "CLK_DISP_CCORR0", 0, (1), DISP_MODULE_CCORR0},
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[CLK_DISP_AAL0] = {
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NULL, "CLK_DISP_AAL0", 0, (1), DISP_MODULE_AAL0},
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[CLK_DISP_GAMMA0] = {
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NULL, "CLK_DISP_GAMMA0", 0, (1), DISP_MODULE_GAMMA0},
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[CLK_DISP_DITHER0] = {
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NULL, "CLK_DISP_DITHER0", 0, (1), DISP_MODULE_DITHER0},
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[CLK_DSI0_MM_CK] = {
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NULL, "CLK_DSI0_MM_CK", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_DSI0_IF_CK] = {
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NULL, "CLK_DSI0_IF_CK", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_DPI_MM_CK] = {
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NULL, "CLK_DPI_MM_CK", 0, (1<<1), DISP_MODULE_UNKNOWN},
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[CLK_DPI_IF_CK] = {
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NULL, "CLK_DPI_IF_CK", 0, (1<<1), DISP_MODULE_UNKNOWN},
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[CLK_MM_26M] = {
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NULL, "CLK_MM_26M", 0, (1), DISP_MODULE_UNKNOWN},
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[CLK_DISP_RSZ] = {
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NULL, "CLK_DISP_RSZ", 0, (1), DISP_MODULE_RSZ0},
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[CLK_MUX_MM] = {
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NULL, "CLK_MUX_MM", 0, (1), DISP_MODULE_UNKNOWN},
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[CLK_MUX_DISP_PWM] = {
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NULL, "CLK_MUX_DISP_PWM", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_DISP_PWM] = {
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NULL, "CLK_DISP_PWM", 0, (1), DISP_MODULE_PWM0},
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[CLK_26M] = {
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NULL, "CLK_26M", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_DISP_POSTMASK] = {
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NULL, "CLK_DISP_POSTMASK", 0, (1), DISP_MODULE_POSTMASK},
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[CLK_DISP_OVL_FBDC] = {
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NULL, "CLK_DISP_OVL_FBDC", 0, (1), DISP_MODULE_UNKNOWN},
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/* DPI */
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[CLK_UNIVPLL_D3_D2] = {
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NULL, "CLK_UNIVPLL_D3_D2", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_UNIVPLL_D3_D4] = {
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NULL, "CLK_UNIVPLL_D3_D4", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_OSC_D2] = {
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NULL, "CLK_OSC_D2", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_OSC_D4] = {
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NULL, "CLK_OSC_D4", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_OSC_D16] = {
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NULL, "CLK_OSC_D16", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_MUX_DPI0] = {
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NULL, "CLK_MUX_DPI0", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_TVDPLL_D2] = {
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NULL, "CLK_TVDPLL_D2", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_TVDPLL_D4] = {
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NULL, "CLK_TVDPLL_D4", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_TVDPLL_D8] = {
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NULL, "CLK_TVDPLL_D8", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_TVDPLL_D16] = {
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NULL, "CLK_TVDPLL_D16", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_TVDPLL_CK] = {
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NULL, "CLK_TVDPLL_CK", 0, (0), DISP_MODULE_UNKNOWN},
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[CLK_MIPID0_26M] = {
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NULL, "CLK_MIPID0_26M", 0, (0), DISP_MODULE_UNKNOWN},
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};
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static void __iomem *ddp_apmixed_base;
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static unsigned int parsed_apmixed;
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static int apmixed_refcnt;
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const char *ddp_get_clk_name(unsigned int n)
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{
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if (n >= MAX_DISP_CLK_CNT) {
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DDP_PR_ERR("DISPSYS CLK id=%d is more than MAX_DISP_CLK_CNT\n",
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n);
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return NULL;
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}
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return ddp_clks[n].clk_name;
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}
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int ddp_clk_set_handle(struct clk *pclk, unsigned int n)
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{
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int ret = 0;
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if (n >= MAX_DISP_CLK_CNT) {
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DDP_PR_ERR("DISPSYS CLK id=%d is more than MAX_DISP_CLK_CNT\n",
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n);
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return -1;
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}
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ddp_clks[n].pclk = pclk;
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DDPMSG("ddp_clk[%d] %p\n", n, ddp_clks[n].pclk);
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return ret;
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}
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int ddp_clk_check(void)
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{
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int i;
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int ret = 0;
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for (i = 0; i < MAX_DISP_CLK_CNT; i++) {
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if (ddp_clks[i].refcnt != 0)
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ret++;
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DDPDBG("%s: %s is %s refcnt=%d\n",
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__func__, ddp_clks[i].clk_name,
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ddp_clks[i].refcnt == 0 ? "off" : "on",
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ddp_clks[i].refcnt);
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}
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DDPDBG("%s: mipitx pll clk is %s refcnt=%d\n",
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__func__, apmixed_refcnt == 0 ? "off" : "on", apmixed_refcnt);
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return ret;
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}
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int ddp_clk_prepare_enable(enum DDP_CLK_ID id)
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{
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int ret = 0;
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DDPDBG("%s, clkid = %d\n", __func__, id);
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if (disp_helper_get_stage() != DISP_HELPER_STAGE_NORMAL)
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return ret;
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if (id >= MAX_DISP_CLK_CNT) {
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DDP_PR_ERR("DISPSYS CLK id=%d is more than MAX_DISP_CLK_CNT\n",
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id);
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return -1;
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}
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if (ddp_clks[id].pclk == NULL) {
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DDP_PR_ERR("DISPSYS CLK %d NULL\n", id);
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return -1;
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}
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ret = clk_prepare_enable(ddp_clks[id].pclk);
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ddp_clks[id].refcnt++;
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if (ret)
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DDP_PR_ERR("DISPSYS CLK prepare failed: errno %d\n", ret);
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return ret;
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}
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int ddp_clk_disable_unprepare(enum DDP_CLK_ID id)
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{
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int ret = 0;
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DDPDBG("%s, clkid = %d\n", __func__, id);
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if (disp_helper_get_stage() != DISP_HELPER_STAGE_NORMAL)
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return ret;
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if (id >= MAX_DISP_CLK_CNT) {
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DDP_PR_ERR("DISPSYS CLK id=%d is more than MAX_DISP_CLK_CNT\n",
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id);
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return -1;
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}
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if (ddp_clks[id].pclk == NULL) {
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DDP_PR_ERR("DISPSYS CLK %d NULL\n", id);
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return -1;
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}
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clk_disable_unprepare(ddp_clks[id].pclk);
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ddp_clks[id].refcnt--;
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return ret;
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}
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int ddp_clk_set_parent(enum DDP_CLK_ID id, enum DDP_CLK_ID parent)
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{
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if (id >= MAX_DISP_CLK_CNT) {
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DDP_PR_ERR("DISPSYS CLK id=%d >= MAX_DISP_CLK_CNT\n",
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id);
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return -1;
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}
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if (parent >= MAX_DISP_CLK_CNT) {
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DDP_PR_ERR("DISPSYS CLK parent=%d >= MAX_DISP_CLK_CNT\n",
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parent);
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return -1;
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}
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if ((ddp_clks[id].pclk == NULL) || (ddp_clks[parent].pclk == NULL)) {
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DDP_PR_ERR("DISPSYS CLK %d or parent %d NULL\n", id, parent);
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return -1;
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}
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return clk_set_parent(ddp_clks[id].pclk, ddp_clks[parent].pclk);
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}
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static int __ddp_set_mipi26m(int idx, int en)
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{
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if (idx != 0)
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DDPMSG("%s: not support DSI%d for mt3967\n", __func__, idx);
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if (en) {
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ddp_clk_prepare_enable(CLK_MIPID0_26M);
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apmixed_refcnt++;
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} else {
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ddp_clk_disable_unprepare(CLK_MIPID0_26M);
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apmixed_refcnt--;
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}
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return 0;
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}
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int ddp_clk_set_mipi26m(enum DISP_MODULE_ENUM module, int en)
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{
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int ret = 0;
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if (disp_helper_get_stage() != DISP_HELPER_STAGE_NORMAL)
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return ret;
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ret = ddp_parse_apmixed_base();
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if (ret)
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return -1;
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if (module == DISP_MODULE_DSI0 || module == DISP_MODULE_DSIDUAL)
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__ddp_set_mipi26m(0, en);
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if (module == DISP_MODULE_DSI1 || module == DISP_MODULE_DSIDUAL)
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__ddp_set_mipi26m(1, en);
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DDPMSG("%s en=%d, val=0x%x\n", __func__, en,
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clk_readl(APMIXEDSYS_PLL_BASE + APMIXED_PLL_CON0));
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return ret;
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}
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int ddp_parse_apmixed_base(void)
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{
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int ret = 0;
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struct device_node *node;
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if (parsed_apmixed)
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return ret;
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node = of_find_compatible_node(NULL, NULL, "mediatek,mt6779-apmixed");
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if (!node) {
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DDP_PR_ERR("[DDP_APMIXED] DISP find apmixed node failed\n");
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return -1;
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}
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ddp_apmixed_base = of_iomap(node, 0);
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if (!ddp_apmixed_base) {
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DDP_PR_ERR("[DDP_APMIXED] DISP apmixed base failed\n");
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return -1;
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}
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parsed_apmixed = 1;
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return ret;
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}
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static unsigned int _is_main_module(struct ddp_clk *pclk)
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{
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return (pclk->belong_to & 0x1);
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}
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static unsigned int _is_ext_module(struct ddp_clk *pclk)
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{
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return (pclk->belong_to & 0x2);
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}
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static unsigned int _is_ovl2mem_module(struct ddp_clk *pclk)
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{
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return (pclk->belong_to & 0x4);
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}
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void ddp_clk_top_clk_switch(bool on)
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{
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if (on) {
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ddp_clk_prepare_enable(CLK_MM_MTCMOS);
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#ifdef CONFIG_MTK_SMI_EXT
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smi_bus_prepare_enable(SMI_LARB0, "DISP");
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smi_bus_prepare_enable(SMI_LARB1, "DISP");
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#else
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ddp_clk_prepare_enable(CLK_GALS_COMM0);
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ddp_clk_prepare_enable(CLK_GALS_COMM1);
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ddp_clk_prepare_enable(CLK_SMI_COMMON);
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ddp_clk_prepare_enable(CLK_SMI_LARB0);
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ddp_clk_prepare_enable(CLK_SMI_LARB1);
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#endif
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ddp_clk_prepare_enable(CLK_MM_26M);
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} else {
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ddp_clk_disable_unprepare(CLK_MM_26M);
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#ifdef CONFIG_MTK_SMI_EXT
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smi_bus_disable_unprepare(SMI_LARB0, "DISP");
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smi_bus_disable_unprepare(SMI_LARB1, "DISP");
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#else
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ddp_clk_disable_unprepare(CLK_SMI_LARB0);
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ddp_clk_disable_unprepare(CLK_SMI_LARB1);
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ddp_clk_disable_unprepare(CLK_SMI_COMMON);
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ddp_clk_disable_unprepare(CLK_GALS_COMM1);
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ddp_clk_disable_unprepare(CLK_GALS_COMM0);
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#endif
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ddp_clk_disable_unprepare(CLK_MM_MTCMOS);
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}
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}
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/**
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* ddp_main_modules_clk_on
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*
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* success: ret = 0
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* error: ret = -1
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*/
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int ddp_main_modules_clk_on(void)
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{
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unsigned int i = 0;
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int ret = 0;
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enum DISP_MODULE_ENUM m;
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struct DDP_MODULE_DRIVER *m_drv;
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DISPFUNC();
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/* --TOP CLK-- */
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ddp_clk_top_clk_switch(true);
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/* --MODULE CLK-- */
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for (i = 0; i < MAX_DISP_CLK_CNT; i++) {
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if (!_is_main_module(&ddp_clks[i]))
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continue;
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m = ddp_clks[i].module_id;
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m_drv = ddp_get_module_driver(m);
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if (m != DISP_MODULE_UNKNOWN && m_drv) {
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/* module driver power on */
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if (m_drv->power_on && m_drv->power_off) {
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m_drv->power_on(m, NULL);
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} else {
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DDP_PR_ERR("[%s]%s no power on(off) function\n",
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__func__, ddp_get_module_name(m));
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ret = -1;
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}
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}
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}
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/* DISP_DSI */
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m = _get_dst_module_by_lcm(primary_get_lcm());
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if (m == DISP_MODULE_UNKNOWN)
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ret = -1;
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else if (is_ddp_module(m) &&
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ddp_get_module_driver(m)->power_on)
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ddp_get_module_driver(m)->power_on(m, NULL);
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pr_info("CG0 0x%x, CG1 0x%x\n",
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clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON0),
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clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON1));
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return ret;
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}
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int ddp_ext_modules_clk_on(void)
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{
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unsigned int i = 0;
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int ret = 0;
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enum DISP_MODULE_ENUM m;
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struct DDP_MODULE_DRIVER *m_drv;
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DISPFUNC();
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/* --TOP CLK-- */
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ddp_clk_top_clk_switch(true);
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/* --MODULE CLK-- */
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for (i = 0; i < MAX_DISP_CLK_CNT; i++) {
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if (!_is_ext_module(&ddp_clks[i]))
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continue;
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m = ddp_clks[i].module_id;
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m_drv = ddp_get_module_driver(m);
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if (m != DISP_MODULE_UNKNOWN && m_drv) {
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/* module driver power on */
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if (m_drv->power_on && m_drv->power_off) {
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m_drv->power_on(m, NULL);
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} else {
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DDP_PR_ERR("[%s]%s no power on(off) function\n",
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__func__, ddp_get_module_name(m));
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ret = -1;
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}
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}
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}
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pr_info("CG0 0x%x, CG1 0x%x\n",
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clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON0),
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clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON1));
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return ret;
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}
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int ddp_ovl2mem_modules_clk_on(void)
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{
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unsigned int i = 0;
|
|
int ret = 0;
|
|
enum DISP_MODULE_ENUM m;
|
|
struct DDP_MODULE_DRIVER *m_drv;
|
|
|
|
DISPFUNC();
|
|
/* --TOP CLK-- */
|
|
ddp_clk_top_clk_switch(true);
|
|
|
|
/* --MODULE CLK-- */
|
|
for (i = 0; i < MAX_DISP_CLK_CNT; i++) {
|
|
if (!_is_ovl2mem_module(&ddp_clks[i]))
|
|
continue;
|
|
|
|
m = ddp_clks[i].module_id;
|
|
m_drv = ddp_get_module_driver(m);
|
|
if (m != DISP_MODULE_UNKNOWN && m_drv) {
|
|
/* module driver power on */
|
|
if (m_drv->power_on && m_drv->power_off) {
|
|
m_drv->power_on(m, NULL);
|
|
} else {
|
|
DDP_PR_ERR("[%s]%s no power on(off) function\n",
|
|
__func__, ddp_get_module_name(m));
|
|
ret = -1;
|
|
}
|
|
}
|
|
}
|
|
|
|
pr_info("CG0 0x%x, CG1 0x%x\n",
|
|
clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON0),
|
|
clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON1));
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ddp_main_modules_clk_on
|
|
*
|
|
* success: ret = 0
|
|
* error: ret = -1
|
|
*/
|
|
int ddp_main_modules_clk_off(void)
|
|
{
|
|
unsigned int i = 0;
|
|
int ret = 0;
|
|
enum DISP_MODULE_ENUM m;
|
|
struct DDP_MODULE_DRIVER *m_drv;
|
|
|
|
DISPFUNC();
|
|
/* --MODULE CLK-- */
|
|
for (i = 0; i < MAX_DISP_CLK_CNT; i++) {
|
|
if (!_is_main_module(&ddp_clks[i]))
|
|
continue;
|
|
|
|
m = ddp_clks[i].module_id;
|
|
if (m != DISP_MODULE_UNKNOWN && ddp_get_module_driver(m)) {
|
|
/* module driver power off */
|
|
m_drv = ddp_get_module_driver(m);
|
|
if (m_drv->power_on && m_drv->power_off) {
|
|
pr_info("%s power_off\n",
|
|
ddp_get_module_name(m));
|
|
m_drv->power_off(m, NULL);
|
|
} else {
|
|
DDP_PR_ERR("[%s]%s no power on(off) function\n",
|
|
__func__, ddp_get_module_name(m));
|
|
ret = -1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* DISP_DSI */
|
|
m = _get_dst_module_by_lcm(primary_get_lcm());
|
|
if (m == DISP_MODULE_UNKNOWN)
|
|
ret = -1;
|
|
else
|
|
ddp_get_module_driver(m)->power_off(m, NULL);
|
|
|
|
/* --TOP CLK-- */
|
|
ddp_clk_top_clk_switch(false);
|
|
|
|
pr_info("CG0 0x%x, CG1 0x%x\n",
|
|
clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON0),
|
|
clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON1));
|
|
return ret;
|
|
}
|
|
|
|
int ddp_ext_modules_clk_off(void)
|
|
{
|
|
unsigned int i = 0;
|
|
int ret = 0;
|
|
enum DISP_MODULE_ENUM m;
|
|
struct DDP_MODULE_DRIVER *m_drv;
|
|
|
|
DISPFUNC();
|
|
/* --MODULE CLK-- */
|
|
for (i = 0; i < MAX_DISP_CLK_CNT; i++) {
|
|
if (!_is_ext_module(&ddp_clks[i]))
|
|
continue;
|
|
|
|
m = ddp_clks[i].module_id;
|
|
if (m != DISP_MODULE_UNKNOWN && ddp_get_module_driver(m)) {
|
|
/* module driver power off */
|
|
m_drv = ddp_get_module_driver(m);
|
|
if (m_drv->power_on && m_drv->power_off) {
|
|
pr_info("%s power_off\n",
|
|
ddp_get_module_name(m));
|
|
m_drv->power_off(m, NULL);
|
|
} else {
|
|
DDP_PR_ERR("[%s]%s no power on(off) function\n",
|
|
__func__, ddp_get_module_name(m));
|
|
ret = -1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* --TOP CLK-- */
|
|
ddp_clk_top_clk_switch(false);
|
|
|
|
pr_info("CG0 0x%x, CG1 0x%x\n",
|
|
clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON0),
|
|
clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON1));
|
|
return ret;
|
|
}
|
|
|
|
int ddp_ovl2mem_modules_clk_off(void)
|
|
{
|
|
unsigned int i = 0;
|
|
int ret = 0;
|
|
enum DISP_MODULE_ENUM m;
|
|
struct DDP_MODULE_DRIVER *m_drv;
|
|
|
|
DISPFUNC();
|
|
/* --MODULE CLK-- */
|
|
for (i = 0; i < MAX_DISP_CLK_CNT; i++) {
|
|
if (!_is_ovl2mem_module(&ddp_clks[i]))
|
|
continue;
|
|
|
|
m = ddp_clks[i].module_id;
|
|
if (m != DISP_MODULE_UNKNOWN && ddp_get_module_driver(m)) {
|
|
m_drv = ddp_get_module_driver(m);
|
|
/* module driver power off */
|
|
if (m_drv->power_on && m_drv->power_off) {
|
|
pr_info("%s power_off\n",
|
|
ddp_get_module_name(m));
|
|
m_drv->power_off(m, NULL);
|
|
} else {
|
|
DDP_PR_ERR("[%s]%s no power on(off) function\n",
|
|
__func__, ddp_get_module_name(m));
|
|
ret = -1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* --TOP CLK-- */
|
|
ddp_clk_top_clk_switch(false);
|
|
|
|
pr_info("CG0 0x%x, CG1 0x%x\n",
|
|
clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON0),
|
|
clk_readl(DISP_REG_CONFIG_MMSYS_CG_CON1));
|
|
return ret;
|
|
}
|
|
|
|
int ddp_module_clk_enable(enum DISP_MODULE_TYPE_ENUM module_t)
|
|
{
|
|
int ret = 0;
|
|
unsigned int i = 0;
|
|
unsigned int j = 0;
|
|
unsigned int number = 0;
|
|
enum DISP_MODULE_ENUM module_id = DISP_MODULE_UNKNOWN;
|
|
|
|
number = ddp_get_module_num_by_t(module_t);
|
|
pr_info("[%s] module type = %d, module num on this type = %d\n",
|
|
__func__, module_t, number);
|
|
for (i = 0; i < number; i++) {
|
|
module_id = ddp_get_module_id_by_idx(module_t, i);
|
|
for (j = 0; j < MAX_DISP_CLK_CNT; j++) {
|
|
if (ddp_clks[j].module_id == module_id)
|
|
ddp_clk_prepare_enable(j);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int ddp_module_clk_disable(enum DISP_MODULE_TYPE_ENUM module_t)
|
|
{
|
|
int ret = 0;
|
|
unsigned int i = 0;
|
|
unsigned int j = 0;
|
|
unsigned int number = 0;
|
|
enum DISP_MODULE_ENUM module_id = DISP_MODULE_UNKNOWN;
|
|
|
|
number = ddp_get_module_num_by_t(module_t);
|
|
pr_info("[%s] module type = %d, module num on this type = %d\n",
|
|
__func__, module_t, number);
|
|
for (i = 0; i < number; i++) {
|
|
module_id = ddp_get_module_id_by_idx(module_t, i);
|
|
for (j = 0; j < MAX_DISP_CLK_CNT; j++) {
|
|
if (ddp_clks[j].module_id == module_id)
|
|
ddp_clk_disable_unprepare(j);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
enum DDP_CLK_ID ddp_get_module_clk_id(enum DISP_MODULE_ENUM module_id)
|
|
{
|
|
unsigned int i = 0;
|
|
|
|
for (i = 0; i < MAX_DISP_CLK_CNT; i++) {
|
|
if (ddp_clks[i].module_id == module_id)
|
|
return i;
|
|
}
|
|
|
|
return MAX_DISP_CLK_CNT;
|
|
}
|
|
|
|
int ddp_clk_enable_by_module(enum DISP_MODULE_ENUM module)
|
|
{
|
|
int ret = 0;
|
|
enum DDP_CLK_ID id = MAX_DISP_CLK_CNT;
|
|
|
|
id = ddp_get_module_clk_id(module);
|
|
ret = ddp_clk_prepare_enable(id);
|
|
if (ret)
|
|
DDP_PR_ERR("invalid module id=%d\n", module);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int ddp_clk_disable_by_module(enum DISP_MODULE_ENUM module)
|
|
{
|
|
int ret = 0;
|
|
enum DDP_CLK_ID id = MAX_DISP_CLK_CNT;
|
|
|
|
id = ddp_get_module_clk_id(module);
|
|
ret = ddp_clk_disable_unprepare(id);
|
|
if (ret)
|
|
DDP_PR_ERR("invalid module id=%d\n", module);
|
|
|
|
return ret;
|
|
}
|