545 lines
10 KiB
C
545 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#define LOG_TAG "INFO"
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#include "ddp_info.h"
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#include "ddp_debug.h"
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#include "ddp_log.h"
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#define DDP_MODULE_REG_RANGE (0x1000)
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static const char reg_magic[] = "no_regs_info";
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/**
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* {
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* module_id,
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* module_type,
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* module_name,
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* can_connect,
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* module_driver,
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*
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* {
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* reg_dt_name,
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* reg_pa_check,
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* reg_irq_check,
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* irq_max_bit,
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* reg_va,
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* reg_irq
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* }
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* },
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*/
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struct ddp_module ddp_modules[DISP_MODULE_NUM] = {
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[DISP_MODULE_OVL0] = {
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DISP_MODULE_OVL0,
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DISP_T_OVL,
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"ovl0",
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1,
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&ddp_driver_ovl,
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{"mediatek,mt6779-disp_ovl0", 0x14008000, 281, 14, 0, 0, 0}
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},
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[DISP_MODULE_OVL0_2L] = {
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DISP_MODULE_OVL0_2L,
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DISP_T_OVL,
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"ovl0_2l",
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1,
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&ddp_driver_ovl,
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{"mediatek,mt6779-disp_ovl0_2l", 0x14009000, 282, 14, 0, 0, 0}
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},
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[DISP_MODULE_OVL1_2L] = {
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DISP_MODULE_OVL1_2L,
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DISP_T_OVL,
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"ovl1_2l",
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1,
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&ddp_driver_ovl,
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{"mediatek,mt6779-disp_ovl1_2l", 0x1400a000, 283, 14, 0, 0, 0}
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},
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[DISP_MODULE_RDMA0] = {
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DISP_MODULE_RDMA0,
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DISP_T_RDMA,
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"rdma0",
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1,
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&ddp_driver_rdma,
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{"mediatek,mt6779-disp_rdma0", 0x1400b000, 284, 7, 0, 0, 0}
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},
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[DISP_MODULE_RDMA1] = {
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DISP_MODULE_RDMA1,
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DISP_T_RDMA,
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"rdma1",
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1,
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&ddp_driver_rdma,
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{"mediatek,mt6779-disp_rdma1", 0x1400c000, 285, 7, 0, 0, 0}
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},
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[DISP_MODULE_RDMA_VIRTUAL0] = {
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DISP_MODULE_RDMA_VIRTUAL0,
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DISP_T_UNKNOWN,
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"rdma_virtual0",
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1,
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NULL,
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{reg_magic,}
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},
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[DISP_MODULE_WDMA0] = {
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DISP_MODULE_WDMA0,
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DISP_T_WDMA,
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"wdma0",
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1,
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&ddp_driver_wdma,
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{"mediatek,mt6779-disp_wdma0", 0x1400d000, 286, 1, 0, 0, 0}
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},
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[DISP_MODULE_WDMA_VIRTUAL0] = {
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DISP_MODULE_WDMA_VIRTUAL0,
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DISP_T_UNKNOWN,
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"wdma_virtual0",
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1,
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NULL,
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{reg_magic,}
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},
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[DISP_MODULE_WDMA_VIRTUAL1] = {
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DISP_MODULE_WDMA_VIRTUAL1,
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DISP_T_UNKNOWN,
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"wdma_virtual1",
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1,
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NULL,
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{reg_magic,}
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},
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[DISP_MODULE_COLOR0] = {
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DISP_MODULE_COLOR0,
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DISP_T_COLOR,
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"color0",
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1,
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&ddp_driver_color,
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{"mediatek,mt6779-disp_color0", 0x1400e000, 287, 0, 0, 0, 0}
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},
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[DISP_MODULE_CCORR0] = {
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DISP_MODULE_CCORR0,
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DISP_T_CCORR,
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"ccorr0",
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1,
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&ddp_driver_ccorr,
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{"mediatek,mt6779-disp_ccorr0", 0x1400f000, 288, 1, 0, 0, 0}
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},
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[DISP_MODULE_AAL0] = {
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DISP_MODULE_AAL0,
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DISP_T_AAL,
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"aal0",
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1,
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&ddp_driver_aal,
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{"mediatek,mt6779-disp_aal0", 0x14010000, 289, 1, 0, 0, 0}
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},
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[DISP_MODULE_GAMMA0] = {
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DISP_MODULE_GAMMA0,
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DISP_T_GAMMA,
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"gamma0",
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1,
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&ddp_driver_gamma,
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{"mediatek,mt6779-disp_gamma0", 0x14011000, 290, 0, 0, 0, 0}
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},
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[DISP_MODULE_DITHER0] = {
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DISP_MODULE_DITHER0,
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DISP_T_DITHER,
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"dither0",
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1,
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&ddp_driver_dither,
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{"mediatek,mt6779-disp_dither0", 0x14012000, 291, 0, 0, 0, 0}
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},
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[DISP_MODULE_DSI0] = {
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DISP_MODULE_DSI0,
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DISP_T_DSI,
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"dsi0",
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1,
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&ddp_driver_dsi0,
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{"mediatek,mt6779-dsi0", 0x14014000, 292, 15, 0, 0, 0}
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},
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[DISP_MODULE_DSI1] = {
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DISP_MODULE_DSI1,
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DISP_T_DSI,
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"dsi1",
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0,
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NULL,
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{reg_magic,}
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},
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[DISP_MODULE_DSIDUAL] = {
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DISP_MODULE_DSIDUAL,
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DISP_T_DSI,
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"dsidual",
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0,
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NULL,
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{reg_magic,}
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},
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[DISP_MODULE_PWM0] = {
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DISP_MODULE_PWM0,
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DISP_T_PWM,
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"pwm0",
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0,
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&ddp_driver_pwm,
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{"mediatek,mt6779-disp_pwm0", 0x1100e000, 183, 0, 0, 0, 0}
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},
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[DISP_MODULE_CONFIG] = {
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DISP_MODULE_CONFIG,
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DISP_T_UNKNOWN,
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"config",
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0,
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NULL,
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{"mediatek,mt6779-mmsys", 0x14000000, 0, 0, 0, 0, 0}
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},
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[DISP_MODULE_MUTEX] = {
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DISP_MODULE_MUTEX,
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DISP_T_UNKNOWN,
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"mutex",
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0,
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NULL,
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{"mediatek,mt6779-mm_mutex", 0x14016000, 273, 21, 0, 0, 0}
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},
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[DISP_MODULE_SMI_COMMON] = {
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DISP_MODULE_SMI_COMMON,
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DISP_T_UNKNOWN,
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"smi-common",
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0,
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NULL,
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{"mediatek,mt6779-smi-common", 0x14019000, 0, 0, 0, 0, 0}
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},
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[DISP_MODULE_SMI_LARB0] = {
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DISP_MODULE_SMI_LARB0,
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DISP_T_UNKNOWN,
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"smi-larb0",
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0,
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NULL,
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{"mediatek,mt6779-smi-larb", 0x14017000, 296, 0, 0, 0, 0}
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},
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[DISP_MODULE_SMI_LARB1] = {
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DISP_MODULE_SMI_LARB1,
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DISP_T_UNKNOWN,
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"smi-larb1",
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0,
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NULL,
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{"mediatek,mt6779-smi-larb", 0x14018000, 294, 0, 0, 0, 1}
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},
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[DISP_MODULE_MIPI0] = {
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DISP_MODULE_MIPI0,
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DISP_T_UNKNOWN,
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"mipi0",
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0,
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NULL,
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{"mediatek,mt6779-mipi_tx0", 0x11e50000, 0, 0, 0, 0, 0}
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},
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[DISP_MODULE_MIPI1] = {
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DISP_MODULE_MIPI1,
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DISP_T_UNKNOWN,
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"mipi1",
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0,
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NULL,
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{reg_magic,}
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},
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[DISP_MODULE_RSZ0] = {
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DISP_MODULE_RSZ0,
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DISP_T_RSZ,
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"rsz0",
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1,
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&ddp_driver_rsz,
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{"mediatek,mt6779-disp_rsz0", 0x1401a000, 297, 0, 0, 0, 0}
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},
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[DISP_MODULE_DPI] = {
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DISP_MODULE_DPI,
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DISP_T_DPI,
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"dpi",
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1,
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NULL,
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{"mediatek,mt6779-dpi0", 0x14015000, 293, 3, 0, 0, 0}
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},
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[DISP_MODULE_DPI_VIRTUAL] = {
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DISP_MODULE_DPI_VIRTUAL,
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DISP_T_UNKNOWN,
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"dpi_virtual",
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1,
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NULL,
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{reg_magic,}
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},
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[DISP_MODULE_POSTMASK] = {
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DISP_MODULE_POSTMASK,
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DISP_T_POSTMASK,
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"postmask",
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1,
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&ddp_driver_postmask,
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{"mediatek,mt6779-disp_postmask0", 0x14021000, 300, 13, 0, 0, 0}
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},
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[DISP_MODULE_UNKNOWN] = {
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DISP_MODULE_UNKNOWN,
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DISP_T_UNKNOWN,
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"unknown",
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0,
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NULL,
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{reg_magic,}
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},
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};
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unsigned int is_ddp_module(enum DISP_MODULE_ENUM module)
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{
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if (module >= 0 && module < DISP_MODULE_NUM)
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return 1;
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return 0;
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}
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unsigned int is_ddp_module_has_reg_info(enum DISP_MODULE_ENUM module)
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{
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if (!is_ddp_module(module))
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return 0;
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if (strcmp(ddp_modules[module].reg_info.reg_dt_name, reg_magic))
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return 1;
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return 0;
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}
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const char *ddp_get_module_name(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module(module))
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return ddp_modules[module].module_name;
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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return "unknown-module";
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}
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unsigned int _can_connect(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module(module))
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return ddp_modules[module].can_connect;
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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struct DDP_MODULE_DRIVER *ddp_get_module_driver(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module(module))
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return ddp_modules[module].module_driver;
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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const char *ddp_get_module_dtname(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module(module))
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return ddp_modules[module].reg_info.reg_dt_name;
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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return "unknown";
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}
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unsigned int ddp_get_module_checkirq(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
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return ddp_modules[module].reg_info.reg_irq_check;
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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unsigned long ddp_get_module_pa(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
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return ddp_modules[module].reg_info.reg_pa_check;
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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unsigned int ddp_get_module_max_irq_bit(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
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return ddp_modules[module].reg_info.irq_max_bit;
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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unsigned int ddp_is_irq_enable(enum DISP_MODULE_ENUM module)
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{
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#if (defined(CONFIG_TEE) || \
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defined(CONFIG_TRUSTONIC_TEE_SUPPORT)) && \
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defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
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if (module == DISP_MODULE_WDMA0)
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return 0;
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#endif
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if (ddp_get_module_max_irq_bit(module))
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return 1;
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return 0;
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}
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void ddp_module_irq_disable(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module)) {
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ddp_modules[module].reg_info.irq_max_bit = 0;
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return;
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}
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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}
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void ddp_set_module_va(enum DISP_MODULE_ENUM module, unsigned long va)
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{
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if (is_ddp_module_has_reg_info(module)) {
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ddp_modules[module].reg_info.reg_va = va;
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return;
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}
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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}
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unsigned long ddp_get_module_va(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
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return ddp_modules[module].reg_info.reg_va;
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return 0;
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}
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void ddp_info_set_module_irq(enum DISP_MODULE_ENUM module, unsigned int irq)
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{
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if (is_ddp_module_has_reg_info(module)) {
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ddp_modules[module].reg_info.reg_irq = irq;
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return;
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}
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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}
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unsigned int ddp_get_module_irq(enum DISP_MODULE_ENUM module)
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{
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if (is_ddp_module_has_reg_info(module))
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return ddp_modules[module].reg_info.reg_irq;
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DDPMSG("%s: invalid module id=%d\n", __func__, module);
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return 0;
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}
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unsigned int is_reg_addr_valid(unsigned int isVa, unsigned long addr)
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{
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unsigned int i = 0;
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for (i = 0; i < DISP_MODULE_NUM; i++) {
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if ((isVa == 1) && (addr >= ddp_get_module_va(i)) &&
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(addr < ddp_get_module_va(i) + DDP_MODULE_REG_RANGE))
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break;
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if ((isVa == 0) && (addr >= ddp_get_module_pa(i)) &&
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(addr < ddp_get_module_pa(i) + DDP_MODULE_REG_RANGE))
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break;
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}
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if (i < DISP_MODULE_NUM) {
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DDPMSG("addr valid, isVa=0x%x, addr=0x%08lx, module=%s!\n",
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isVa, addr, ddp_get_module_name(i));
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return i;
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}
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DDP_PR_ERR("%s: fail, isVa=0x%x, addr=0x%08lx!\n",
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__func__, isVa, addr);
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return 0;
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}
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unsigned int ddp_get_module_num_by_t(enum DISP_MODULE_TYPE_ENUM module_t)
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{
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int i;
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int cnt = 0;
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for (i = 0; i < DISP_MODULE_NUM; i++) {
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if (ddp_modules[i].module_type == module_t)
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cnt++;
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}
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return cnt;
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}
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enum DISP_MODULE_ENUM
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ddp_get_module_id_by_idx(enum DISP_MODULE_TYPE_ENUM module_t, unsigned int idx)
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{
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int i;
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int index = 0;
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for (i = 0; i < DISP_MODULE_NUM; i++) {
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if (ddp_modules[i].module_type == module_t)
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index++;
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if (index == (idx + 1))
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return i;
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}
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return DISP_MODULE_UNKNOWN;
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}
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const char *ddp_get_ioctl_name(enum DDP_IOCTL_NAME ioctl)
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{
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switch (ioctl) {
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case DDP_SWITCH_DSI_MODE:
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return "DDP_SWITCH_DSI_MODE";
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case DDP_STOP_VIDEO_MODE:
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return "DDP_STOP_VIDEO_MODE";
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case DDP_BACK_LIGHT:
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return "DDP_BACK_LIGHT";
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case DDP_SWITCH_LCM_MODE:
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return "DDP_SWITCH_LCM_MODE";
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case DDP_DPI_FACTORY_TEST:
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return "DDP_DPI_FACTORY_TEST";
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case DDP_DSI_IDLE_CLK_CLOSED:
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return "DDP_DSI_IDLE_CLK_CLOSED";
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case DDP_DSI_IDLE_CLK_OPEN:
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return "DDP_DSI_IDLE_CLK_OPEN";
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case DDP_DSI_PORCH_CHANGE:
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return "DDP_DSI_PORCH_CHANGE";
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case DDP_PHY_CLK_CHANGE:
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return "DDP_PHY_CLK_CHANGE";
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case DDP_ENTER_ULPS:
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return "DDP_ENTER_ULPS";
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case DDP_EXIT_ULPS:
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return "DDP_EXIT_ULPS";
|
|
case DDP_RDMA_GOLDEN_SETTING:
|
|
return "DDP_RDMA_GOLDEN_SETTING";
|
|
case DDP_OVL_GOLDEN_SETTING:
|
|
return "DDP_OVL_GOLDEN_SETTING";
|
|
case DDP_PARTIAL_UPDATE:
|
|
return "DDP_PARTIAL_UPDATE";
|
|
case DDP_UPDATE_PLL_CLK_ONLY:
|
|
return "DDP_UPDATE_PLL_CLK_ONLY";
|
|
case DDP_DSI_SW_INIT:
|
|
return "DDP_DSI_SW_INIT";
|
|
case DDP_DSI_MIPI_POWER_ON:
|
|
return "DDP_DSI_MIPI_POWER_ON";
|
|
default:
|
|
break;
|
|
}
|
|
return "unknown-ioctl";
|
|
}
|