398 lines
13 KiB
C
398 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#define LOG_TAG "POSTMASK"
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#include "ddp_log.h"
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#include "ddp_clkmgr.h"
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#include <linux/delay.h>
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#include "ddp_info.h"
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#include "ddp_hal.h"
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#include "ddp_reg.h"
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#include "ddp_postmask.h"
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#include "lcm_drv.h"
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#include "disp_helper.h"
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#define POSTMASK_MASK_MAX_NUM 96
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#define POSTMASK_GRAD_MAX_NUM 192
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#define POSTMASK_DRAM_MODE
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static unsigned int postmask_bg_color = 0xff000000;
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static unsigned int postmask_mask_color = 0xff000000;
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unsigned long postmask_base_addr(enum DISP_MODULE_ENUM module)
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{
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switch (module) {
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case DISP_MODULE_POSTMASK:
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return DISPSYS_POSTMASK_BASE;
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default:
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DDP_PR_ERR("invalid postmask module=%d\n", module);
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return -1;
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}
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return 0;
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}
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int postmask_dump_reg(enum DISP_MODULE_ENUM module)
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{
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unsigned long baddr = postmask_base_addr(module);
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DDPDUMP("== DISP %s REGS ==\n", ddp_get_module_name(module));
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DDPDUMP("(0x0)0x%08x 0x%08x 0x%08x 0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_EN + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_RESET + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_INTEN + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_INTSTA + baddr));
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DDPDUMP("(0x20)0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_CFG + baddr));
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DDPDUMP("(0x30)0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_SIZE + baddr));
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DDPDUMP("(0x40)0x%08x 0x%08x 0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_SRAM_CFG + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_MASK_SHIFT + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_GRAD_SHIFT + baddr));
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DDPDUMP("(0x50)0x%08x 0x%08x 0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_BLEND_CFG + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_ROI_BGCLR + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_MASK_CLR + baddr));
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DDPDUMP("(0xA0)0x%08x 0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_STATUS + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_INPUT_COUNT + baddr));
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DDPDUMP("(0xB0)0x%08x 0x%08x 0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_DEBUG_0 + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_DEBUG_1 + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_DEBUG_2 + baddr));
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DDPDUMP("(0x100)0x%08x 0x%08x 0x%08x 0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_MEM_ADDR + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_MEM_LENGTH + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_RDMA_FIFO_CTRL + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_MEM_GMC_SETTING2 + baddr));
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DDPDUMP("(0x110)0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_PAUSE_REGION + baddr));
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DDPDUMP("(0x130)0x%08x 0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_RDMA_GREQ_NUM + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_RDMA_GREQ_URG_NUM + baddr));
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DDPDUMP("(0x140)0x%08x 0x%08x 0x%08x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_RDMA_ULTRA_SRC + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_RDMA_BUF_LOW_TH + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_RDMA_BUF_HIGH_TH + baddr));
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return 0;
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}
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int postmask_dump_analysis(enum DISP_MODULE_ENUM module)
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{
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unsigned long baddr = postmask_base_addr(module);
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DDPDUMP("== DISP %s ANALYSIS ==\n", ddp_get_module_name(module));
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DDPDUMP("en=%d,cfg=0x%x,size=(%dx%d)\n",
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DISP_REG_GET(DISP_REG_POSTMASK_EN + baddr) & 0x1,
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DISP_REG_GET(DISP_REG_POSTMASK_CFG + baddr),
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(DISP_REG_GET(DISP_REG_POSTMASK_SIZE + baddr) >> 16) & 0x1fff,
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DISP_REG_GET(DISP_REG_POSTMASK_SIZE + baddr) & 0x1fff);
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DDPDUMP("blend_cfg=0x%x,bg=0x%x,mask=0x%x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_BLEND_CFG + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_ROI_BGCLR + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_MASK_CLR + baddr));
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DDPDUMP("fifo_cfg=%d,gmc=0x%x,threshold=(0x%x,0x%x)\n",
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DISP_REG_GET(DISP_REG_POSTMASK_RDMA_FIFO_CTRL + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_MEM_GMC_SETTING2 + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_RDMA_BUF_LOW_TH + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_RDMA_BUF_HIGH_TH + baddr));
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DDPDUMP("mem_addr=0x%x,length=0x%x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_MEM_ADDR + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_MEM_LENGTH + baddr));
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DDPDUMP("status=0x%x,cur_pos=0x%x\n",
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DISP_REG_GET(DISP_REG_POSTMASK_STATUS + baddr),
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DISP_REG_GET(DISP_REG_POSTMASK_INPUT_COUNT + baddr));
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return 0;
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}
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static int postmask_dump(enum DISP_MODULE_ENUM module, int level)
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{
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postmask_dump_analysis(module);
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postmask_dump_reg(module);
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return 0;
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}
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static int postmask_clock_on(enum DISP_MODULE_ENUM module, void *handle)
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{
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ddp_clk_enable_by_module(module);
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DDPMSG("%s CG:%d(0x%x)\n", __func__,
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(DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON1) >> 14) & 0x1,
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DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON1));
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return 0;
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}
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static int postmask_clock_off(enum DISP_MODULE_ENUM module, void *handle)
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{
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ddp_clk_disable_by_module(module);
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DDPMSG("%s CG:%d(0x%x)\n", __func__,
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(DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON1) >> 14) & 0x1,
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DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON1));
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return 0;
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}
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static int postmask_init(enum DISP_MODULE_ENUM module, void *handle)
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{
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return postmask_clock_on(module, handle);
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}
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static int postmask_deinit(enum DISP_MODULE_ENUM module, void *handle)
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{
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return postmask_clock_off(module, handle);
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}
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int postmask_start(enum DISP_MODULE_ENUM module, void *handle)
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{
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unsigned long base_addr = postmask_base_addr(module);
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DISP_REG_SET_FIELD(handle, EN_FLD_POSTMASK_EN,
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base_addr + DISP_REG_POSTMASK_EN, 1);
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DISP_REG_SET(handle, base_addr + DISP_REG_POSTMASK_INTEN,
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REG_FLD_VAL(PM_INTEN_FLD_PM_IF_FME_END_INTEN, 1) |
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REG_FLD_VAL(PM_INTEN_FLD_PM_FME_CPL_INTEN, 1) |
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REG_FLD_VAL(PM_INTEN_FLD_PM_START_INTEN, 1) |
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REG_FLD_VAL(PM_INTEN_FLD_PM_ABNORMAL_SOF_INTEN, 1) |
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REG_FLD_VAL(PM_INTEN_FLD_RDMA_FME_UND_INTEN, 1) |
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REG_FLD_VAL(PM_INTEN_FLD_RDMA_EOF_ABNORMAL_INTEN, 1));
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DDPMSG("%s en:%d(0x%x)\n", __func__,
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DISP_REG_GET(base_addr + DISP_REG_POSTMASK_EN) & 0x1,
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DISP_REG_GET(base_addr + DISP_REG_POSTMASK_EN));
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return 0;
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}
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int postmask_stop(enum DISP_MODULE_ENUM module, void *handle)
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{
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unsigned long base_addr = postmask_base_addr(module);
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DISP_REG_SET(handle, base_addr + DISP_REG_POSTMASK_INTEN, 0);
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DISP_REG_SET_FIELD(handle, EN_FLD_POSTMASK_EN,
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base_addr + DISP_REG_POSTMASK_EN, 0);
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DISP_REG_SET(handle, base_addr + DISP_REG_POSTMASK_INTSTA, 0);
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DDPMSG("%s en:%d(0x%x)\n", __func__,
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DISP_REG_GET(base_addr + DISP_REG_POSTMASK_EN) & 0x1,
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DISP_REG_GET(base_addr + DISP_REG_POSTMASK_EN));
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return 0;
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}
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static int postmask_config(enum DISP_MODULE_ENUM module,
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struct disp_ddp_path_config *pConfig,
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void *handle)
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{
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unsigned long base_addr = postmask_base_addr(module);
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unsigned int value = 0;
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#ifdef CONFIG_MTK_ROUND_CORNER_SUPPORT
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#ifndef POSTMASK_DRAM_MODE
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unsigned int i = 0;
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unsigned int num = 0;
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#endif
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#endif
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unsigned int rc_mode =
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disp_helper_get_option(DISP_OPT_ROUND_CORNER_MODE);
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struct LCM_PARAMS *lcm_param = &(pConfig->dispif_config);
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if (!pConfig->dst_dirty)
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return 0;
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DDPMSG("%s size:(%d,%d), mode:%d, pattern:(%d,%d), mem:(0x%p,%d)\n",
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__func__, pConfig->dst_w, pConfig->dst_h,
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disp_helper_get_option(DISP_OPT_ROUND_CORNER_MODE),
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lcm_param->corner_pattern_height,
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lcm_param->corner_pattern_height_bot,
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lcm_param->corner_pattern_lt_addr,
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lcm_param->corner_pattern_tp_size);
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value = (REG_FLD_VAL((PM_BLEND_CFG_FLD_A_EN), 1) |
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REG_FLD_VAL((PM_BLEND_CFG_FLD_PARGB_BLD), 0) |
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REG_FLD_VAL((PM_BLEND_CFG_FLD_CONST_BLD), 0));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_BLEND_CFG +
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base_addr, value);
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DISP_REG_SET(handle, DISP_REG_POSTMASK_ROI_BGCLR +
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base_addr, postmask_bg_color);
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DISP_REG_SET(handle, DISP_REG_POSTMASK_MASK_CLR +
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base_addr, postmask_mask_color);
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value = (REG_FLD_VAL((PM_SIZE_FLD_HSIZE), pConfig->dst_w) |
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REG_FLD_VAL((PM_SIZE_FLD_VSIZE), pConfig->dst_h));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_SIZE + base_addr, value);
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if (lcm_param->round_corner_en == 1) {
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if (rc_mode != DISP_HELPER_HW_RC) {
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DDP_PR_ERR("unsupport round corner mode:%d\n", rc_mode);
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return -1;
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}
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#ifdef CONFIG_MTK_ROUND_CORNER_SUPPORT
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value = (REG_FLD_VAL((PM_PAUSE_REGION_FLD_RDMA_PAUSE_START),
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lcm_param->corner_pattern_height) |
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REG_FLD_VAL((PM_PAUSE_REGION_FLD_RDMA_PAUSE_END),
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pConfig->dst_h -
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lcm_param->corner_pattern_height_bot));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_PAUSE_REGION +
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base_addr, value);
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value = (REG_FLD_VAL((PM_MEM_GMC_FLD_ISSUE_REQ_TH), 15) |
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REG_FLD_VAL((PM_MEM_GMC_FLD_ISSUE_REQ_TH_URG), 15) |
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REG_FLD_VAL((PM_MEM_GMC_FLD_REQ_TH_PREULTRA), 0) |
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REG_FLD_VAL((PM_MEM_GMC_FLD_REQ_TH_ULTRA), 1) |
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REG_FLD_VAL((PM_MEM_GMC_FLD_FORCE_REQ_TH), 0));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_MEM_GMC_SETTING2 +
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base_addr, value);
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value = (REG_FLD_VAL((PM_GREQ_FLD_GREQ_NUM), 1) |
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REG_FLD_VAL((PM_GREQ_FLD_GREQ_URG_NUM), 7) |
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REG_FLD_VAL((PM_GREQ_FLD_GREQ_NUM_SHT_VAL), 1) |
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REG_FLD_VAL((PM_GREQ_FLD_GREQ_NUM_SHT), 0) |
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REG_FLD_VAL((PM_GREQ_FLD_OSTD_GREQ_NUM), 0xFF) |
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REG_FLD_VAL((PM_GREQ_FLD_GREQ_DIS_CNT), 1) |
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REG_FLD_VAL((PM_GREQ_FLD_GREQ_STOP_EN), 0) |
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REG_FLD_VAL((PM_GREQ_FLD_GRP_END_STOP), 1) |
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REG_FLD_VAL((PM_GREQ_FLD_GRP_BRK_STOP), 1) |
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REG_FLD_VAL((PM_GREQ_FLD_IOBUF_FLUSH_PREULTRA), 1) |
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REG_FLD_VAL((PM_GREQ_FLD_IOBUF_FLUSH_ULTRA), 1));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_RDMA_GREQ_NUM +
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base_addr, value);
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value = (REG_FLD_VAL((PM_GREQ_URG_FLD_ARB_GREQ_URG_TH), 0) |
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REG_FLD_VAL((PM_GREQ_URG_FLD_ARB_URG_BIAS), 0));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_RDMA_GREQ_URG_NUM +
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base_addr, value);
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value = (REG_FLD_VAL((PM_ULTRA_FLD_PREULTRA_BUF_SRC), 0) |
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REG_FLD_VAL((PM_ULTRA_FLD_PREULTRA_SMI_SRC), 1) |
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REG_FLD_VAL((PM_ULTRA_FLD_PREULTRA_ROI_END_SRC), 0) |
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REG_FLD_VAL((PM_ULTRA_FLD_PREULTRA_RDMA_SRC), 0) |
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REG_FLD_VAL((PM_ULTRA_FLD_ULTRA_BUF_SRC), 0) |
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REG_FLD_VAL((PM_ULTRA_FLD_ULTRA_SMI_SRC), 1) |
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REG_FLD_VAL((PM_ULTRA_FLD_ULTRA_ROI_END_SRC), 0) |
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REG_FLD_VAL((PM_ULTRA_FLD_ULTRA_RDMA_SRC), 0));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_RDMA_ULTRA_SRC +
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base_addr, value);
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value = (REG_FLD_VAL((PM_TH_FLD_RDMA_ULTRA_LOW_TH), 0xFFF) |
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REG_FLD_VAL((PM_TH_FLD_RDMA_PREULTRA_LOW_TH), 0xFFF));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_RDMA_BUF_LOW_TH +
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base_addr, value);
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value = (REG_FLD_VAL((PM_TH_FLD_RDMA_PREULTRA_HIGH_TH), 0xFFF) |
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REG_FLD_VAL((PM_TH_FLD_RDMA_PREULTRA_HIGH_DIS), 0));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_RDMA_BUF_HIGH_TH +
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base_addr, value);
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#ifdef POSTMASK_DRAM_MODE
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value = (REG_FLD_VAL((PM_CFG_FLD_RELAY_MODE), 0) |
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REG_FLD_VAL((PM_CFG_FLD_DRAM_MODE), 1) |
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REG_FLD_VAL((PM_CFG_FLD_BGCLR_IN_SEL), 1) |
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REG_FLD_VAL((PM_CFG_FLD_GCLAST_EN), 1) |
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REG_FLD_VAL((PM_CFG_FLD_STALL_CG_ON), 1));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_CFG + base_addr, value);
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DISP_REG_SET(handle, DISP_REG_POSTMASK_MEM_ADDR +
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base_addr,
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top_mva);
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DISP_REG_SET(handle, DISP_REG_POSTMASK_MEM_LENGTH +
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base_addr,
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lcm_param->corner_pattern_tp_size);
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#else
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value = (REG_FLD_VAL((PM_CFG_FLD_RELAY_MODE), 0) |
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REG_FLD_VAL((PM_CFG_FLD_DRAM_MODE), 0) |
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REG_FLD_VAL((PM_CFG_FLD_BGCLR_IN_SEL), 1) |
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REG_FLD_VAL((PM_CFG_FLD_GCLAST_EN), 1) |
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REG_FLD_VAL((PM_CFG_FLD_STALL_CG_ON), 1));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_CFG + base_addr, value);
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value = (REG_FLD_VAL((PM_SRAM_CFG_FLD_MASK_NUM_SW_SET),
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lcm_param->corner_pattern_height) |
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REG_FLD_VAL((PM_SRAM_CFG_FLD_MASK_L_TOP_EN), 1) |
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REG_FLD_VAL((PM_SRAM_CFG_FLD_MASK_L_BOTTOM_EN), 1) |
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REG_FLD_VAL((PM_SRAM_CFG_FLD_MASK_R_TOP_EN), 1) |
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REG_FLD_VAL((PM_SRAM_CFG_FLD_MASK_R_BOTTOM_EN), 1));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_SRAM_CFG +
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base_addr, value);
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num = POSTMASK_MASK_MAX_NUM;
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for (i = 0; i < num; i++) {
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DISP_REG_SET(handle, DISP_REG_POSTMASK_NUM(i) +
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base_addr, 0x1F001F00);
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}
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num = POSTMASK_GRAD_MAX_NUM;
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for (i = 0; i < num; i++) {
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DISP_REG_SET(handle, DISP_REG_POSTMASK_GRAD_VAL(i) +
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base_addr, 0x0);
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}
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#endif
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#endif
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} else {
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/*enable BYPASS postmask*/
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value = (REG_FLD_VAL((PM_CFG_FLD_RELAY_MODE), 1) |
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REG_FLD_VAL((PM_CFG_FLD_DRAM_MODE), 1) |
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REG_FLD_VAL((PM_CFG_FLD_BGCLR_IN_SEL), 1) |
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REG_FLD_VAL((PM_CFG_FLD_GCLAST_EN), 1) |
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REG_FLD_VAL((PM_CFG_FLD_STALL_CG_ON), 1));
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DISP_REG_SET(handle, DISP_REG_POSTMASK_CFG + base_addr, value);
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}
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return 0;
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}
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int postmask_reset(enum DISP_MODULE_ENUM module, void *handle)
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{
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unsigned long base_addr = postmask_base_addr(module);
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DISP_REG_SET_FIELD(handle, RESET_FLD_POSTMASK_RESET,
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base_addr + DISP_REG_POSTMASK_RESET, 1);
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DISP_REG_SET_FIELD(handle, RESET_FLD_POSTMASK_RESET,
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base_addr + DISP_REG_POSTMASK_RESET, 0);
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DDPMSG("%s done\n", __func__);
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return 0;
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}
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int postmask_bypass(enum DISP_MODULE_ENUM module, int bypass)
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{
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unsigned long base_addr = postmask_base_addr(module);
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DISP_REG_SET_FIELD(NULL, PM_CFG_FLD_RELAY_MODE,
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base_addr + DISP_REG_POSTMASK_CFG, 1);
|
|
DDPMSG("%s done\n", __func__);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct DDP_MODULE_DRIVER ddp_driver_postmask = {
|
|
.init = postmask_init,
|
|
.deinit = postmask_deinit,
|
|
.config = postmask_config,
|
|
.start = postmask_start,
|
|
.trigger = NULL,
|
|
.stop = postmask_stop,
|
|
.reset = postmask_reset,
|
|
.power_on = postmask_clock_on,
|
|
.power_off = postmask_clock_off,
|
|
.is_idle = NULL,
|
|
.is_busy = NULL,
|
|
.dump_info = postmask_dump,
|
|
.bypass = postmask_bypass,
|
|
.build_cmdq = NULL,
|
|
.set_lcm_utils = NULL,
|
|
};
|