200 lines
9.4 KiB
C
200 lines
9.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Joey Pan <joey.pan@mediatek.com>
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*/
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#ifndef _DDP_REG_MMSYS_H_
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#define _DDP_REG_MMSYS_H_
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/* field definition */
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/* ------------------------------------------------------------- */
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/* Config */
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#define MMCON(offset) (DISPSYS_CONFIG_BASE + (offset))
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#define DISP_REG_CONFIG_MMSYS_INTEN MMCON(0x0)
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#define DISP_REG_CONFIG_MMSYS_INTSTA MMCON(0x4)
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#define DISP_REG_CONFIG_MFG_APB_TX_CON MMCON(0xc)
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#define DISP_REG_CONFIG_MMSYS_HRT_WEIGHTING_0 MMCON(0x030)
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#define DISP_REG_CONFIG_MMSYS_HRT_WEIGHTING_1 MMCON(0x034)
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#define DISP_REG_CONFIG_MMSYS_HRT_WEIGHTING_2 MMCON(0x038)
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#define DISP_REG_CONFIG_MMSYS_HRT_WEIGHTING_3 MMCON(0x03c)
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#define DISP_REG_CONFIG_MMSYS_HRT_WEIGHTING_4 MMCON(0x040)
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#define DISP_REG_CONFIG_MMSYS_HRT_WEIGHTING_5 MMCON(0x044)
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#define DISP_REG_CONFIG_MMSYS_HRT_WEIGHTING_CTRL MMCON(0x048)
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#define DISP_REG_CONFIG_MMSYS_HRT_TRIGGER_TIME MMCON(0x04c)
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#define DISP_REG_CONFIG_MMSYS_MOUT_RST MMCON(0x050)
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#define DISP_REG_CONFIG_MMSYS_MISC MMCON(0x0F0)
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#define FLD_SHARE_WROT_SEL REG_FLD_MSB_LSB(6, 6)
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#define FLD_OVL0_ULTRA_SEL REG_FLD_MSB_LSB(19, 16)
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#define FLD_OVL0_2L_ULTRA_SEL REG_FLD_MSB_LSB(23, 20)
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#define FLD_OVL1_2L_ULTRA_SEL REG_FLD_MSB_LSB(27, 24)
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#define DISP_REG_CONFIG_MMSYS_SMI_LARB_SEL MMCON(0x0F4)
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#define DISP_REG_CONFIG_MMSYS_SODI_REQ_MASK MMCON(0x0F8)
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#define FLD_HRT_URGENT_CTRL REG_FLD_MSB_LSB(7, 0)
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#define FLD_SODI_REQ_MASKEN REG_FLD_MSB_LSB(11, 8)
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#define FLD_SODI_REQ_MASKEN_CG_RDMA0 REG_FLD_MSB_LSB(9, 9)
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#define FLD_SODI_REQ_MASKEN_CG_RDMA1 REG_FLD_MSB_LSB(11, 11)
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#define FLD_SODI_REQ_MASKVAL REG_FLD_MSB_LSB(15, 12)
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#define FLD_DVFS_HALT_MASK REG_FLD_MSB_LSB(20, 16)
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#define FLD_DVFS_HALT_MASK_RDMA0 REG_FLD_MSB_LSB(16, 16)
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#define FLD_DVFS_HALT_MASK_RDMA1 REG_FLD_MSB_LSB(17, 17)
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#define FLD_DVFS_HALT_MASK_WDMA REG_FLD_MSB_LSB(18, 18)
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#define FLD_DRS_HALT_MASK REG_FLD_MSB_LSB(27, 24)
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#define DISP_REG_CONFIG_MMSYS_CG_CON0 MMCON(0x100)
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#define DISP_REG_CONFIG_MMSYS_CG_SET0 MMCON(0x104)
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#define DISP_REG_CONFIG_MMSYS_CG_CLR0 MMCON(0x108)
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#define DISP_REG_CONFIG_MMSYS_CG_CON1 MMCON(0x110)
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#define DISP_REG_CONFIG_MMSYS_CG_SET1 MMCON(0x114)
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#define DISP_REG_CONFIG_MMSYS_CG_CLR1 MMCON(0x118)
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#define DISP_REG_CONFIG_MMSYS_HW_DCM_DIS0 MMCON(0x120)
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#define DISP_REG_CONFIG_MMSYS_HW_DCM_DIS_SET0 MMCON(0x124)
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#define DISP_REG_CONFIG_MMSYS_HW_DCM_DIS_CLR0 MMCON(0x128)
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#define DISP_REG_CONFIG_MMSYS_HW_DCM_DIS1 MMCON(0x130)
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#define DISP_REG_CONFIG_MMSYS_HW_DCM_DIS_SET1 MMCON(0x134)
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#define DISP_REG_CONFIG_MMSYS_HW_DCM_DIS_CLR1 MMCON(0x138)
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#define DISP_REG_CONFIG_MMSYS_SW0_RST_B MMCON(0x140)
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#define DISP_REG_CONFIG_MMSYS_SW1_RST_B MMCON(0x144)
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#define DISP_REG_CONFIG_MMSYS_LCM_RST_B MMCON(0x150)
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#define DISP_REG_CONFIG_SMI_N21MUX_CFG_WR MMCON(0x168)
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#define DISP_REG_CONFIG_SMI_N21MUX_CFG_RD MMCON(0x16c)
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#define DISP_REG_CONFIG_ELA2GMC_BASE_ADDR MMCON(0x170)
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#define DISP_REG_CONFIG_ELA2GMC_BASE_ADDR_END MMCON(0x174)
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#define DISP_REG_CONFIG_ELA2GMC_FINAL_ADDR MMCON(0x178)
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#define DISP_REG_CONFIG_ELA2GMC_STATUS MMCON(0x17c)
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#define DISP_REG_CONFIG_LARB6_AXI_ASIF_CFG_WD MMCON(0x180)
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#define DISP_REG_CONFIG_LARB6_AXI_ASIF_CFG_RD MMCON(0x184)
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#define DISP_REG_CONFIG_PROC_TRACK_EMI_BUSY_CON MMCON(0x190)
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#define DISP_REG_CONFIG_DISP_FAKE_ENG_EN MMCON(0x200)
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#define DISP_REG_CONFIG_DISP_FAKE_ENG_RST MMCON(0x204)
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#define DISP_REG_CONFIG_DISP_FAKE_ENG_CON0 MMCON(0x208)
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#define DISP_REG_CONFIG_DISP_FAKE_ENG_CON1 MMCON(0x20c)
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#define DISP_REG_CONFIG_DISP_FAKE_ENG_RD_ADDR MMCON(0x210)
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#define DISP_REG_CONFIG_DISP_FAKE_ENG_WR_ADDR MMCON(0x214)
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#define DISP_REG_CONFIG_DISP_FAKE_ENG_STATE MMCON(0x218)
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#define DISP_REG_CONFIG_DISP_FAKE2_ENG_EN MMCON(0x220)
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#define DISP_REG_CONFIG_DISP_FAKE2_ENG_RST MMCON(0x224)
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#define DISP_REG_CONFIG_DISP_FAKE2_ENG_CON0 MMCON(0x228)
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#define DISP_REG_CONFIG_DISP_FAKE2_ENG_CON1 MMCON(0x22c)
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#define DISP_REG_CONFIG_DISP_FAKE2_ENG_RD_ADDR MMCON(0x230)
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#define DISP_REG_CONFIG_DISP_FAKE2_ENG_WR_ADDR MMCON(0x234)
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#define DISP_REG_CONFIG_DISP_FAKE2_ENG_STATE MMCON(0x238)
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#define DISP_REG_CONFIG_MMSYS_MBIST_CON MMCON(0x800)
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#define DISP_REG_CONFIG_MMSYS_MBIST_DONE0 MMCON(0x804)
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#define DISP_REG_CONFIG_MMSYS_MBIST_DONE1 MMCON(0x808)
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#define DISP_REG_CONFIG_MMSYS_MBIST_HOLDB MMCON(0x80c)
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#define DISP_REG_CONFIG_MMSYS_MBIST_MODE0 MMCON(0x810)
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#define DISP_REG_CONFIG_MMSYS_MBIST_MODE1 MMCON(0x814)
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#define DISP_REG_CONFIG_MMSYS_MBIST_MODE2 MMCON(0x818)
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#define DISP_REG_CONFIG_MMSYS_MBIST_MODE3 MMCON(0x81c)
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#define DISP_REG_CONFIG_MMSYS_MBIST_FAIL0 MMCON(0x820)
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#define DISP_REG_CONFIG_MMSYS_MBIST_FAIL1 MMCON(0x824)
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#define DISP_REG_CONFIG_MMSYS_MBIST_FAIL2 MMCON(0x828)
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#define DISP_REG_CONFIG_MMSYS_MBIST_FAIL3 MMCON(0x82c)
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#define DISP_REG_CONFIG_MMSYS_MBIST_DEBUG MMCON(0x830)
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#define DISP_REG_CONFIG_MMSYS_MBIST_DIAG_SCANOUT MMCON(0x834)
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#define DISP_REG_CONFIG_MMSYS_MBIST_PRE_FUSE MMCON(0x838)
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#define DISP_REG_CONFIG_MMSYS_MBIST_BSEL0 MMCON(0x83c)
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#define DISP_REG_CONFIG_MMSYS_MBIST_HDEN MMCON(0x844)
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#define DISP_REG_CONFIG_MDP_RDMA0_MEM_DELSEL_0 MMCON(0x848)
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#define DISP_REG_CONFIG_MDP_RDMA0_MEM_DELSEL_1 MMCON(0x84c)
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#define DISP_REG_CONFIG_MDP_RDMA1_MEM_DELSEL MMCON(0x850)
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#define DISP_REG_CONFIG_MDP_RSZ_MEM_DELSEL_0 MMCON(0x854)
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#define DISP_REG_CONFIG_MDP_RSZ_MEM_DELSEL_1 MMCON(0x858)
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#define DISP_REG_CONFIG_MDP_RSZ_MEM_DELSEL_2 MMCON(0x85c)
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#define DISP_REG_CONFIG_MDP_TDSHP_MEM_DELSEL MMCON(0x860)
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#define DISP_REG_CONFIG_MDP_WROT_MEM_DELSEL_0 MMCON(0x864)
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#define DISP_REG_CONFIG_MDP_WROT_MEM_DELSEL_1 MMCON(0x868)
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#define DISP_REG_CONFIG_DISP_OVL0_MEM_DELSEL_0 MMCON(0x86c)
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#define DISP_REG_CONFIG_DISP_OVL0_MEM_DELSEL_1 MMCON(0x870)
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#define DISP_REG_CONFIG_DISP_OVL0_2L_MEM_DELSEL MMCON(0x874)
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#define DISP_REG_CONFIG_DISP_OVL1_2L_MEM_DELSEL MMCON(0x878)
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#define DISP_REG_CONFIG_DISP_RDMA_MEM_DELSEL MMCON(0x87c)
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#define DISP_REG_CONFIG_DISP_RDMA_UFO_MEM_DELSEL MMCON(0x880)
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#define DISP_REG_CONFIG_DISP_GAMMA_MEM_DELSEL MMCON(0x884)
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#define DISP_REG_CONFIG_DISP_DSI_MEM_DELSEL MMCON(0x888)
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#define DISP_REG_CONFIG_DISP_AAL_MEM_DELSEL MMCON(0x88c)
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#define DISP_REG_CONFIG_MDP_AAL_MEM_DELSEL MMCON(0x890)
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#define DISP_REG_CONFIG_DISP_RSZ_MEM_DELSEL MMCON(0x894)
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#define DISP_REG_CONFIG_DISP_WDMA_MEM_DELSEL MMCON(0x898)
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#define DISP_REG_CONFIG_MMSYS_DEBUG_OUT_SEL MMCON(0x89c)
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#define DISP_REG_CONFIG_MMSYS_MBIST_RP_RST_B MMCON(0x8a0)
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#define DISP_REG_CONFIG_MMSYS_MBIST_RP_FAIL0 MMCON(0x8a4)
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#define DISP_REG_CONFIG_MMSYS_MBIST_RP_FAIL1 MMCON(0x8a8)
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#define DISP_REG_CONFIG_MMSYS_MBIST_RP_FAIL2 MMCON(0x8ac)
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#define DISP_REG_CONFIG_MMSYS_MBIST_RP_OK0 MMCON(0x8b0)
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#define DISP_REG_CONFIG_MMSYS_MBIST_RP_OK1 MMCON(0x8b4)
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#define DISP_REG_CONFIG_MMSYS_MBIST_RP_OK2 MMCON(0x8b8)
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#define DISP_REG_CONFIG_MMSYS_DUMMY0 MMCON(0x8bc)
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#define DISP_REG_CONFIG_MMSYS_DUMMY1 MMCON(0x8c0)
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#define DISP_REG_CONFIG_MMSYS_DUMMY2 MMCON(0x8c4)
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#define DISP_REG_CONFIG_MMSYS_DUMMY3 MMCON(0x8c8)
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#define DISP_REG_CONFIG_DISP_DL_VALID_0 MMCON(0x8cc)
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#define DISP_REG_CONFIG_DISP_DL_VALID_1 MMCON(0x8d0)
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#define DISP_REG_CONFIG_DISP_DL_VALID_2 MMCON(0x8d4)
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#define DISP_REG_CONFIG_DISP_DL_VALID_3 MMCON(0x8d8)
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#define DISP_REG_CONFIG_DISP_DL_VALID_4 MMCON(0x8dc)
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#define DISP_REG_CONFIG_DISP_DL_READY_0 MMCON(0x8e0)
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#define DISP_REG_CONFIG_DISP_DL_READY_1 MMCON(0x8e4)
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#define DISP_REG_CONFIG_DISP_DL_READY_2 MMCON(0x8e8)
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#define DISP_REG_CONFIG_DISP_DL_READY_3 MMCON(0x8ec)
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#define DISP_REG_CONFIG_DISP_DL_READY_4 MMCON(0x8f0)
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#define DISP_REG_CONFIG_SMI_LARB_GREQ MMCON(0x8f4)
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#define DISP_REG_CONFIG_DISP_MOUT_MASK_0 MMCON(0x8f8)
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#define DISP_REG_CONFIG_DISP_MOUT_MASK_1 MMCON(0x8fc)
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#define DISP_REG_CONFIG_DISP_MOUT_MASK_2 MMCON(0x900)
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#define DISP_REG_CONFIG_POWER_READ MMCON(0x904)
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#define DISP_REG_CONFIG_HRT_WEIGHT_READ MMCON(0x908)
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#define DISP_REG_CONFIG_MMSYS_DBPI_SEL MMCON(0x964)
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#define DISP_REG_CONFIG_DISP_RDMA_VDE_SEL MMCON(0x968)
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#define DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN MMCON(0xf00)
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#define DISP_REG_CONFIG_DISP_OVL0_2L_MOUT_EN MMCON(0xf04)
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#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN MMCON(0xf08)
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#define DISP_REG_CONFIG_DISP_OVL1_2L_MOUT_EN MMCON(0xf0c)
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#define DISP_REG_CONFIG_DISP_RSZ_MOUT_EN MMCON(0xf10)
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#define DISP_REG_CONFIG_DISP_OVL0_WCG_MOUT_EN MMCON(0xf34)
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#define DISP_REG_CONFIG_DISP_OVL0_2L_WCG_MOUT_EN MMCON(0xf38)
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#define DISP_REG_CONFIG_DISP_OVL1_2L_WCG_MOUT_EN MMCON(0xf3C)
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#define DISP_REG_CONFIG_DISP_RDMA0_RSZ_IN_SOUT_SEL_IN MMCON(0xf40)
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#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN MMCON(0xf44)
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#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL_IN MMCON(0xf48)
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#define DISP_REG_CONFIG_DISP_TO_WROT_SOUT_SEL MMCON(0xf4C)
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#define DISP_REG_CONFIG_DISP_COLOR_OUT_SEL_IN MMCON(0xf68)
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#define DISP_REG_CONFIG_DISP_OVL0_2L_SEL_IN MMCON(0xf6C)
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#define DISP_REG_CONFIG_DISP_OVL0_SEL_IN MMCON(0xf70)
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#define DISP_REG_CONFIG_DISP_PATH0_SEL_IN MMCON(0xf74)
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#define DISP_REG_CONFIG_DISP_RDMA0_RSZ_OUT_SEL_IN MMCON(0xf78)
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#define DISP_REG_CONFIG_DISP_RSZ_SEL_IN MMCON(0xf7C)
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#define DISP_REG_CONFIG_DISP_WDMA0_PRE_SEL_IN MMCON(0xf80)
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#define DISP_REG_CONFIG_DISP_WDMA0_SEL_IN MMCON(0xf84)
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#define DISP_REG_CONFIG_DPI0_SEL_IN MMCON(0xf88)
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#define DISP_REG_CONFIG_DSI0_SEL_IN MMCON(0xf8C)
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#define DISP_REG_CONFIG_OVL_TO_R2Y_SEL_IN MMCON(0xfBC)
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#define DISP_REG_CONFIG_OVL_TO_WDMA_SEL_IN MMCON(0xfC0)
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#define DISP_REG_CONFIG_OVL_TO_WROT_SEL_IN MMCON(0xfC4)
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#define DISP_REG_CONFIG_DISP_OVL0_WCG_SEL_IN MMCON(0xfC8)
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#define DISP_REG_CONFIG_DISP_OVL0_2L_WCG_SEL_IN MMCON(0xfCC)
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#define DISP_REG_CONFIG_DISP_OVL1_2L_WCG_SEL_IN MMCON(0xfD0)
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/* field definition */
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/* ------------------------------------------------------------- */
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#endif /* _DDP_REG_MMSYS_H_ */
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