106 lines
4.6 KiB
C
106 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DDP_REG_MUTEX_H_
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#define _DDP_REG_MUTEX_H_
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#define DISP_OVL_SEPARATE_MUTEX_ID (DISP_MUTEX_DDP_LAST + 1)
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#define DISP_REG_CONFIG_MUTEX_INTEN (DISPSYS_MUTEX_BASE + 0x000)
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#define DISP_REG_CONFIG_MUTEX_INTSTA (DISPSYS_MUTEX_BASE + 0x004)
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#define DISP_REG_CONFIG_MUTEX_CFG (DISPSYS_MUTEX_BASE + 0x008)
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#define DISP_REG_CONFIG_MUTEX0_EN (DISPSYS_MUTEX_BASE + 0x020)
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#define EN_FLD_MUTEX0_EN REG_FLD(1, 0)
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#define DISP_REG_CONFIG_MUTEX0_RST (DISPSYS_MUTEX_BASE + 0x028)
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#define RST_FLD_MUTEX0_RST REG_FLD(1, 0)
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#define DISP_REG_CONFIG_MUTEX0_SOF (DISPSYS_MUTEX_BASE + 0x02C)
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#define SOF_FLD_MUTEX0_SOF REG_FLD(3, 0)
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#define SOF_FLD_MUTEX0_SOF_TIMING REG_FLD(2, 3)
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#define SOF_FLD_MUTEX0_SOF_WAIT REG_FLD(1, 5)
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#define SOF_FLD_MUTEX0_EOF REG_FLD(3, 6)
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#define SOF_FLD_MUTEX0_FOF_TIMING REG_FLD(2, 9)
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#define SOF_FLD_MUTEX0_EOF_WAIT REG_FLD(1, 11)
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#define DISP_REG_CONFIG_MUTEX0_MOD0 (DISPSYS_MUTEX_BASE + 0x030)
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#define DISP_REG_CONFIG_MUTEX1_EN (DISPSYS_MUTEX_BASE + 0x040)
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#define DISP_REG_CONFIG_MUTEX1_RST (DISPSYS_MUTEX_BASE + 0x048)
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#define DISP_REG_CONFIG_MUTEX1_SOF (DISPSYS_MUTEX_BASE + 0x04C)
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#define DISP_REG_CONFIG_MUTEX1_MOD0 (DISPSYS_MUTEX_BASE + 0x050)
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#define DISP_REG_CONFIG_MUTEX2_EN (DISPSYS_MUTEX_BASE + 0x060)
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#define DISP_REG_CONFIG_MUTEX2_RST (DISPSYS_MUTEX_BASE + 0x068)
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#define DISP_REG_CONFIG_MUTEX2_SOF (DISPSYS_MUTEX_BASE + 0x06C)
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#define DISP_REG_CONFIG_MUTEX2_MOD0 (DISPSYS_MUTEX_BASE + 0x070)
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#define DISP_REG_CONFIG_MUTEX3_EN (DISPSYS_MUTEX_BASE + 0x080)
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#define DISP_REG_CONFIG_MUTEX3_RST (DISPSYS_MUTEX_BASE + 0x088)
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#define DISP_REG_CONFIG_MUTEX3_SOF (DISPSYS_MUTEX_BASE + 0x08C)
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#define DISP_REG_CONFIG_MUTEX3_MOD0 (DISPSYS_MUTEX_BASE + 0x090)
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#define DISP_REG_CONFIG_MUTEX4_EN (DISPSYS_MUTEX_BASE + 0x0A0)
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#define DISP_REG_CONFIG_MUTEX4_RST (DISPSYS_MUTEX_BASE + 0x0A8)
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#define DISP_REG_CONFIG_MUTEX4_SOF (DISPSYS_MUTEX_BASE + 0x0AC)
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#define DISP_REG_CONFIG_MUTEX4_MOD0 (DISPSYS_MUTEX_BASE + 0x0B0)
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#define DISP_REG_CONFIG_MUTEX5_EN (DISPSYS_MUTEX_BASE + 0x0C0)
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#define DISP_REG_CONFIG_MUTEX5_RST (DISPSYS_MUTEX_BASE + 0x0C8)
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#define DISP_REG_CONFIG_MUTEX5_SOF (DISPSYS_MUTEX_BASE + 0x0CC)
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#define DISP_REG_CONFIG_MUTEX5_MOD0 (DISPSYS_MUTEX_BASE + 0x0D0)
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#define DISP_REG_CONFIG_MUTEX6_EN (DISPSYS_MUTEX_BASE + 0x0E0)
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#define DISP_REG_CONFIG_MUTEX6_RST (DISPSYS_MUTEX_BASE + 0x0E8)
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#define DISP_REG_CONFIG_MUTEX6_SOF (DISPSYS_MUTEX_BASE + 0x0EC)
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#define DISP_REG_CONFIG_MUTEX6_MOD0 (DISPSYS_MUTEX_BASE + 0x0F0)
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#define DISP_REG_CONFIG_MUTEX7_EN (DISPSYS_MUTEX_BASE + 0x100)
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#define DISP_REG_CONFIG_MUTEX7_RST (DISPSYS_MUTEX_BASE + 0x108)
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#define DISP_REG_CONFIG_MUTEX7_SOF (DISPSYS_MUTEX_BASE + 0x10C)
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#define DISP_REG_CONFIG_MUTEX7_MOD0 (DISPSYS_MUTEX_BASE + 0x110)
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#define DISP_REG_CONFIG_MUTEX8_EN (DISPSYS_MUTEX_BASE + 0x120)
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#define DISP_REG_CONFIG_MUTEX8_RST (DISPSYS_MUTEX_BASE + 0x128)
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#define DISP_REG_CONFIG_MUTEX8_SOF (DISPSYS_MUTEX_BASE + 0x12C)
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#define DISP_REG_CONFIG_MUTEX8_MOD0 (DISPSYS_MUTEX_BASE + 0x130)
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#define DISP_REG_CONFIG_MUTEX9_EN (DISPSYS_MUTEX_BASE + 0x140)
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#define DISP_REG_CONFIG_MUTEX9_RST (DISPSYS_MUTEX_BASE + 0x148)
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#define DISP_REG_CONFIG_MUTEX9_SOF (DISPSYS_MUTEX_BASE + 0x14C)
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#define DISP_REG_CONFIG_MUTEX9_MOD0 (DISPSYS_MUTEX_BASE + 0x150)
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#define DISP_REG_CONFIG_MUTEX10_EN (DISPSYS_MUTEX_BASE + 0x160)
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#define DISP_REG_CONFIG_MUTEX10_RST (DISPSYS_MUTEX_BASE + 0x168)
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#define DISP_REG_CONFIG_MUTEX10_SOF (DISPSYS_MUTEX_BASE + 0x16C)
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#define DISP_REG_CONFIG_MUTEX10_MOD0 (DISPSYS_MUTEX_BASE + 0x170)
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#define DISP_REG_CONFIG_MUTEX11_EN (DISPSYS_MUTEX_BASE + 0x180)
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#define DISP_REG_CONFIG_MUTEX11_RST (DISPSYS_MUTEX_BASE + 0x188)
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#define DISP_REG_CONFIG_MUTEX11_SOF (DISPSYS_MUTEX_BASE + 0x18C)
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#define DISP_REG_CONFIG_MUTEX11_MOD0 (DISPSYS_MUTEX_BASE + 0x190)
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#define DISP_REG_CONFIG_DEBUG_OUT_SEL (DISPSYS_MUTEX_BASE + 0x30C)
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#define DEBUG_OUT_SEL_FLD_DEBUG_OUT_SEL REG_FLD(2, 0)
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#define DISP_REG_CONFIG_MUTEX_EN(n) (DISP_REG_CONFIG_MUTEX0_EN + (0x20 * (n)))
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#define DISP_REG_CONFIG_MUTEX_RST(n) (DISP_REG_CONFIG_MUTEX0_RST + (0x20 * (n)))
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#define DISP_REG_CONFIG_MUTEX_SOF(n) (DISP_REG_CONFIG_MUTEX0_SOF + (0x20 * (n)))
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#define DISP_REG_CONFIG_MUTEX_MOD0(n) \
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(DISP_REG_CONFIG_MUTEX0_MOD0 + (0x20 * (n)))
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/* for CONFIG_MUTEX_SOF, MUTEX_SOF[2..0] */
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#define SOF_VAL_MUTEX0_SOF_SINGLE_MODE (0)
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#define SOF_VAL_MUTEX0_SOF_FROM_DSI0 (1)
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#define SOF_VAL_MUTEX0_SOF_FROM_DPI (2)
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/* for CONFIG_MUTEX_SOF, MUTEX_EOF[8..6] */
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#define SOF_VAL_MUTEX0_EOF_DISABLE (0)
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#define SOF_VAL_MUTEX0_EOF_FROM_DSI0 (1)
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#define SOF_VAL_MUTEX0_EOF_FROM_DPI (2)
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#endif /* _DDP_REG_MUTEX_H_ */
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