594 lines
15 KiB
C
594 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include "ddp_hal.h"
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#include "ddp_reg.h"
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#include "disp_pm_qos.h"
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#include <linux/pm_qos.h>
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#include "helio-dvfsrc-opp-mt6785.h"
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#include "layering_rule.h"
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#include "mmprofile.h"
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#include "mmprofile_function.h"
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#include "disp_drv_log.h"
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#include "disp_drv_platform.h"
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#ifdef MTK_FB_MMDVFS_SUPPORT
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#include "mmdvfs_pmqos.h"
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#include "mt6785/smi_port.h"
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#endif
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#include "cmdq_def.h"
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#include "cmdq_record.h"
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#include "cmdq_reg.h"
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#include "cmdq_core.h"
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#define OCCUPIED_BW_RATIO 1330
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#ifdef MTK_FB_MMDVFS_SUPPORT
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static struct plist_head bw_request_list; /* all module list */
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static struct mm_qos_request ovl0_request;
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static struct mm_qos_request ovl0_fbdc_request;
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static struct mm_qos_request ovl0_2l_request;
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static struct mm_qos_request ovl0_2l_fbdc_request;
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static struct mm_qos_request rdma0_request;
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static struct mm_qos_request wdma0_request;
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static struct mtk_pm_qos_request ddr_opp_request;
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static struct mtk_pm_qos_request mm_freq_request;
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#ifdef CONFIG_MTK_MT6382_BDG
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static struct mtk_pm_qos_request vcore_request;
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#endif
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static struct plist_head hrt_request_list;
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static struct mm_qos_request ovl0_hrt_request;
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static struct mm_qos_request ovl0_2l_hrt_request;
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static struct mm_qos_request rdma0_hrt_request;
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static struct mm_qos_request wdma0_hrt_request;
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static struct mm_qos_request hrt_bw_request;
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#endif
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cmdqBackupSlotHandle dispsys_slot;
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static unsigned int has_hrt_bw;
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#ifdef MTK_FB_MMDVFS_SUPPORT
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static enum ddr_opp __remap_to_opp(enum HRT_LEVEL hrt)
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{
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enum ddr_opp opp = MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE;
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switch (hrt) {
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case HRT_LEVEL_LEVEL0:
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opp = DDR_OPP_4; /* LP4-1200 */
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break;
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case HRT_LEVEL_LEVEL1:
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opp = DDR_OPP_2; /* LP4-2100 */
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break;
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case HRT_LEVEL_LEVEL2:
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opp = DDR_OPP_1; /* LP4-2800 */
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break;
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case HRT_LEVEL_LEVEL3:
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opp = DDR_OPP_0; /* LP4-3200 */
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break;
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case HRT_LEVEL_DEFAULT:
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opp = MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE;
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break;
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default:
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DISP_PR_ERR("%s:unknown hrt level:%d\n", __func__, hrt);
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break;
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}
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return opp;
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}
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static int __init_cmdq_slots(cmdqBackupSlotHandle *pSlot,
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int count, int init_val)
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{
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int i;
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cmdqBackupAllocateSlot(pSlot, count);
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for (i = 0; i < count; i++)
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cmdqBackupWriteSlot(*pSlot, i, init_val);
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return 0;
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}
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#endif
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static int __get_cmdq_slots(cmdqBackupSlotHandle Slot,
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unsigned int slot_index, unsigned int *value)
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{
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int ret;
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ret = cmdqBackupReadSlot(Slot, slot_index, value);
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/* cmdq get slot fail */
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if (ret)
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DISP_PR_ERR("DISP CMDQ get slot failed:%d\n", ret);
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return ret;
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}
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void disp_pm_qos_init(void)
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{
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#ifdef MTK_FB_MMDVFS_SUPPORT
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unsigned long long bandwidth;
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/* initialize display slot */
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__init_cmdq_slots(&(dispsys_slot), DISP_SLOT_NUM, 0);
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/* Initialize owner list */
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plist_head_init(&bw_request_list);
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mm_qos_add_request(&bw_request_list, &ovl0_request,
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SMI_DISP_OVL0);
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mm_qos_add_request(&bw_request_list, &ovl0_fbdc_request,
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SMI_DISP_OVL0);
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mm_qos_add_request(&bw_request_list, &ovl0_2l_request,
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SMI_DISP_OVL0_2L);
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mm_qos_add_request(&bw_request_list, &ovl0_2l_fbdc_request,
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SMI_DISP_OVL0_2L);
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mm_qos_add_request(&bw_request_list, &rdma0_request,
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SMI_DISP_RDMA0);
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mm_qos_add_request(&bw_request_list, &wdma0_request,
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SMI_DISP_WDMA0);
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mtk_pm_qos_add_request(&ddr_opp_request, MTK_PM_QOS_DDR_OPP,
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MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE);
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mtk_pm_qos_add_request(&mm_freq_request, PM_QOS_DISP_FREQ,
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PM_QOS_MM_FREQ_DEFAULT_VALUE);
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#ifdef CONFIG_MTK_MT6382_BDG
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mtk_pm_qos_add_request(&vcore_request, MTK_PM_QOS_VCORE_OPP, //add for mipi clk 1.7GHz //
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VCORE_OPP_1);
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#endif
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plist_head_init(&hrt_request_list);
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mm_qos_add_request(&hrt_request_list, &ovl0_hrt_request,
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SMI_DISP_OVL0);
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mm_qos_add_request(&hrt_request_list, &ovl0_2l_hrt_request,
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SMI_DISP_OVL0_2L);
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mm_qos_add_request(&hrt_request_list, &rdma0_hrt_request,
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SMI_DISP_RDMA0);
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mm_qos_add_request(&hrt_request_list, &wdma0_hrt_request,
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SMI_DISP_WDMA0);
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mm_qos_add_request(&hrt_request_list, &hrt_bw_request,
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get_virtual_port(VIRTUAL_DISP));
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disp_pm_qos_set_default_bw(&bandwidth);
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disp_pm_qos_set_default_hrt();
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#endif
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}
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void disp_pm_qos_deinit(void)
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{
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#ifdef MTK_FB_MMDVFS_SUPPORT
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mm_qos_remove_all_request(&bw_request_list);
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mtk_pm_qos_remove_request(&ddr_opp_request);
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mtk_pm_qos_remove_request(&mm_freq_request);
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#ifdef CONFIG_MTK_MT6382_BDG
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mtk_pm_qos_remove_request(&vcore_request);
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#endif
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#endif
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}
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int disp_pm_qos_request_dvfs(enum HRT_LEVEL hrt)
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{
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#ifdef MTK_FB_MMDVFS_SUPPORT
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enum ddr_opp opp = MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE;
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opp = __remap_to_opp(hrt);
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mmprofile_log_ex(ddp_mmp_get_events()->dvfs, MMPROFILE_FLAG_START,
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hrt, opp);
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mtk_pm_qos_update_request(&ddr_opp_request, opp);
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mmprofile_log_ex(ddp_mmp_get_events()->dvfs, MMPROFILE_FLAG_END, 0, 0);
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#endif
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return 0;
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}
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static int __set_hrt_bw(enum DISP_MODULE_ENUM module,
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unsigned int bandwidth)
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{
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#ifdef MTK_FB_MMDVFS_SUPPORT
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struct mm_qos_request *request;
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switch (module) {
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case DISP_MODULE_OVL0:
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request = &ovl0_hrt_request;
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break;
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case DISP_MODULE_OVL0_2L:
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request = &ovl0_2l_hrt_request;
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break;
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case DISP_MODULE_RDMA0:
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request = &rdma0_hrt_request;
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break;
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case DISP_MODULE_WDMA0:
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request = &wdma0_hrt_request;
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break;
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default:
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DISP_PR_ERR("unsupport module id %s(%d)\n",
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ddp_get_module_name(module), module);
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return -1;
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}
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mm_qos_set_hrt_request(request, bandwidth);
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#endif
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return 0;
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}
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static int __set_bw(enum DISP_MODULE_ENUM module,
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unsigned int bandwidth)
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{
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#ifdef MTK_FB_MMDVFS_SUPPORT
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struct mm_qos_request *request;
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switch (module) {
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case DISP_MODULE_OVL0:
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request = &ovl0_request;
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break;
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case DISP_MODULE_OVL0_2L:
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request = &ovl0_2l_request;
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break;
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case DISP_MODULE_RDMA0:
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request = &rdma0_request;
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break;
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case DISP_MODULE_WDMA0:
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request = &wdma0_request;
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break;
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default:
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DISP_PR_ERR("unsupport module id %s(%d)\n",
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ddp_get_module_name(module), module);
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return -1;
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}
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bandwidth = bandwidth * OCCUPIED_BW_RATIO / 1000;
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mm_qos_set_bw_request(request, bandwidth, BW_COMP_NONE);
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#endif
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mmprofile_log_ex(ddp_mmp_get_events()->primary_pm_qos,
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MMPROFILE_FLAG_PULSE,
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module, bandwidth);
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return 0;
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}
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static int __set_fbdc_bw(enum DISP_MODULE_ENUM module,
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unsigned int bandwidth)
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{
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#ifdef MTK_FB_MMDVFS_SUPPORT
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struct mm_qos_request *request;
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switch (module) {
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case DISP_MODULE_OVL0:
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request = &ovl0_fbdc_request;
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break;
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case DISP_MODULE_OVL0_2L:
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request = &ovl0_2l_fbdc_request;
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break;
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default:
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DISP_PR_ERR("unsupport module id %s(%d)\n",
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ddp_get_module_name(module), module);
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return -1;
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}
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bandwidth = bandwidth * OCCUPIED_BW_RATIO / 1000;
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mm_qos_set_bw_request(request, bandwidth, BW_COMP_DEFAULT);
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#endif
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mmprofile_log_ex(ddp_mmp_get_events()->primary_pm_qos,
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MMPROFILE_FLAG_PULSE,
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module, bandwidth);
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return 0;
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}
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int disp_pm_qos_update_bw(unsigned long long bandwidth)
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{
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mmprofile_log_ex(ddp_mmp_get_events()->primary_pm_qos,
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MMPROFILE_FLAG_START,
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!primary_display_is_decouple_mode(), bandwidth);
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#ifdef MTK_FB_MMDVFS_SUPPORT
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mm_qos_update_all_request(&bw_request_list);
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#endif
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mmprofile_log_ex(ddp_mmp_get_events()->primary_pm_qos,
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MMPROFILE_FLAG_END,
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!primary_display_is_decouple_mode(), bandwidth);
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return 0;
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}
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int disp_pm_qos_update_hrt(unsigned long long bandwidth)
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{
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mmprofile_log_ex(ddp_mmp_get_events()->primary_hrt_bw,
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MMPROFILE_FLAG_START,
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!primary_display_is_decouple_mode(), bandwidth);
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#ifdef MTK_FB_MMDVFS_SUPPORT
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mm_qos_update_all_request(&hrt_request_list);
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#endif
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mmprofile_log_ex(ddp_mmp_get_events()->primary_hrt_bw,
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MMPROFILE_FLAG_END,
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!primary_display_is_decouple_mode(), bandwidth);
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return 0;
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}
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unsigned int get_has_hrt_bw(void)
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{
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return has_hrt_bw;
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}
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int disp_pm_qos_update_mmclk(int mm_freq)
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{
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enum vcore_opp vcore_value = VCORE_OPP_0;
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#if 0
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mmprofile_log_ex(ddp_mmp_get_events()->primary_pm_qos,
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MMPROFILE_FLAG_START,
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!primary_display_is_decouple_mode(), vcore_value);
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#endif
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#ifdef MTK_FB_MMDVFS_SUPPORT
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if (mm_freq < 559)
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vcore_value = VCORE_OPP_1;
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DISPMSG("%s, force set mmclk=%d, vcore=%s\n",
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__func__, mm_freq, vcore_value == VCORE_OPP_0 ? "0.825v" : "0.725v");
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mtk_pm_qos_update_request(&mm_freq_request, mm_freq);
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#ifdef CONFIG_MTK_MT6382_BDG
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mtk_pm_qos_update_request(&vcore_request, vcore_value);
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#endif
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#endif
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#if 0
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mmprofile_log_ex(ddp_mmp_get_events()->primary_pm_qos,
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MMPROFILE_FLAG_END,
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!primary_display_is_decouple_mode(), 0);
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#endif
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return 0;
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}
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int prim_disp_request_hrt_bw(int overlap_num,
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enum DDP_SCENARIO_ENUM scenario, const char *caller,
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unsigned int active_cfg)
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{
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unsigned long long bw_base;
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unsigned int tmp;
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unsigned int wdma_bw;
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/* overlap_num in PAN_DISP ioctl or Assert layer is 0 */
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if (overlap_num == HRT_BW_BYPASS)
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return 0;
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else if (overlap_num == HRT_BW_UNREQ) {
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overlap_num = 0;
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has_hrt_bw = 0;
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} else
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has_hrt_bw = 1;
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bw_base = layering_get_frame_bw(active_cfg);
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bw_base /= 2;
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tmp = bw_base * overlap_num;
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wdma_bw = bw_base * 2;
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switch (scenario) {
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case DDP_SCENARIO_PRIMARY_DISP:
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__set_hrt_bw(DISP_MODULE_OVL0, tmp);
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__set_hrt_bw(DISP_MODULE_OVL0_2L, tmp);
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__set_hrt_bw(DISP_MODULE_WDMA0, 0);
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__set_hrt_bw(DISP_MODULE_RDMA0, 0);
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break;
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case DDP_SCENARIO_PRIMARY_RDMA0_COLOR0_DISP:
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__set_hrt_bw(DISP_MODULE_OVL0, 0);
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__set_hrt_bw(DISP_MODULE_OVL0_2L, 0);
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__set_hrt_bw(DISP_MODULE_WDMA0, 0);
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__set_hrt_bw(DISP_MODULE_RDMA0, tmp);
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break;
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case DDP_SCENARIO_PRIMARY_ALL:
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__set_hrt_bw(DISP_MODULE_OVL0, tmp);
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__set_hrt_bw(DISP_MODULE_OVL0_2L, tmp);
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__set_hrt_bw(DISP_MODULE_WDMA0, wdma_bw);
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__set_hrt_bw(DISP_MODULE_RDMA0, wdma_bw);
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break;
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default:
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DISPINFO("invalid HRT scenario %s\n",
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ddp_get_scenario_name(scenario));
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}
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#ifdef MTK_FB_MMDVFS_SUPPORT
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mm_qos_set_hrt_request(&hrt_bw_request, tmp);
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DISPINFO("%s report HRT BW %u MB overlap %d, %llu/s, scen:%u\n",
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caller, tmp, overlap_num, bw_base, scenario);
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mmprofile_log_ex(ddp_mmp_get_events()->primary_hrt_bw,
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MMPROFILE_FLAG_PULSE,
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overlap_num, tmp);
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mm_qos_update_all_request(&hrt_request_list);
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#endif
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return 0;
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}
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int disp_pm_qos_set_default_bw(unsigned long long *bandwidth)
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{
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__set_bw(DISP_MODULE_OVL0, 0);
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__set_fbdc_bw(DISP_MODULE_OVL0, 0);
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__set_bw(DISP_MODULE_OVL0_2L, 0);
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__set_fbdc_bw(DISP_MODULE_OVL0_2L, 0);
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__set_bw(DISP_MODULE_WDMA0, 0);
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__set_bw(DISP_MODULE_RDMA0, 0);
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*bandwidth = 0;
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return 0;
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}
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int disp_pm_qos_set_default_hrt(void)
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{
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__set_hrt_bw(DISP_MODULE_OVL0, 0);
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__set_hrt_bw(DISP_MODULE_OVL0_2L, 0);
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__set_hrt_bw(DISP_MODULE_WDMA0, 0);
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__set_hrt_bw(DISP_MODULE_RDMA0, 0);
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#ifdef MTK_FB_MMDVFS_SUPPORT
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mm_qos_set_hrt_request(&hrt_bw_request, 0);
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#endif
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return 0;
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}
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int disp_pm_qos_set_ovl_bw(unsigned long long in_fps,
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unsigned long long out_fps, unsigned long long *bandwidth)
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{
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int ret = 0;
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unsigned int is_dc;
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unsigned int ovl0_bw, ovl0_2l_bw, rdma0_bw, wdma0_bw;
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unsigned int ovl0_fbdc_bw, ovl0_2l_fbdc_bw;
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unsigned int ovl0_lstf_bw, ovl0_2l_lstf_bw;
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DISPINFO("%s,fps:[in-%llu,out-%llu]\n",
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__func__, in_fps, out_fps);
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ret |= __get_cmdq_slots(DISPSYS_SLOT_BASE,
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DISP_SLOT_IS_DC, &is_dc);
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ret |= __get_cmdq_slots(DISPSYS_SLOT_BASE,
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DISP_SLOT_OVL0_BW, &ovl0_bw);
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ret |= __get_cmdq_slots(DISPSYS_SLOT_BASE,
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DISP_SLOT_OVL0_FBDC_BW, &ovl0_fbdc_bw);
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ret |= __get_cmdq_slots(DISPSYS_SLOT_BASE,
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DISP_SLOT_OVL0_2L_BW, &ovl0_2l_bw);
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ret |= __get_cmdq_slots(DISPSYS_SLOT_BASE,
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DISP_SLOT_OVL0_2L_FBDC_BW, &ovl0_2l_fbdc_bw);
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ret |= __get_cmdq_slots(DISPSYS_SLOT_BASE,
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DISP_SLOT_RDMA0_BW, &rdma0_bw);
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ret |= __get_cmdq_slots(DISPSYS_SLOT_BASE,
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DISP_SLOT_WDMA0_BW, &wdma0_bw);
|
|
|
|
/*read back ovl last frame bw*/
|
|
__get_cmdq_slots(DISPSYS_SLOT_BASE,
|
|
DISP_SLOT_OVL0_LASTF_BW, &ovl0_lstf_bw);
|
|
__get_cmdq_slots(DISPSYS_SLOT_BASE,
|
|
DISP_SLOT_OVL0_2L_LASTF_BW, &ovl0_2l_lstf_bw);
|
|
|
|
/*bw req is in unit of 16bytes, transfer to bytes*/
|
|
ovl0_lstf_bw = ovl0_lstf_bw << 4;
|
|
ovl0_2l_lstf_bw = ovl0_2l_lstf_bw << 4;
|
|
|
|
DISPDBG(
|
|
"%s ovl0 last bw:%d, ovl0_2l last bw:%d",
|
|
__func__, ovl0_lstf_bw, ovl0_2l_lstf_bw);
|
|
|
|
/* cmdq get slot fail */
|
|
if (ret) {
|
|
DISP_PR_ERR("DISP CMDQ get slot failed:%d\n", ret);
|
|
disp_pm_qos_set_default_bw(bandwidth);
|
|
} else {
|
|
if (is_dc)
|
|
*bandwidth = ((((unsigned long long)ovl0_bw +
|
|
(unsigned long long)ovl0_fbdc_bw +
|
|
(unsigned long long)ovl0_2l_bw +
|
|
(unsigned long long)ovl0_2l_fbdc_bw +
|
|
(unsigned long long)wdma0_bw) * in_fps) +
|
|
((unsigned long long)rdma0_bw * out_fps))*
|
|
OCCUPIED_BW_RATIO;
|
|
else
|
|
*bandwidth = ((unsigned long long)ovl0_bw +
|
|
(unsigned long long)ovl0_fbdc_bw +
|
|
(unsigned long long)ovl0_2l_bw +
|
|
(unsigned long long)ovl0_2l_fbdc_bw) * out_fps *
|
|
OCCUPIED_BW_RATIO;
|
|
|
|
do_div(*bandwidth, 1000 * 1000);
|
|
|
|
/* Call __set_bw API to setup estimated data bw */
|
|
if (is_dc) {
|
|
ovl0_bw = ovl0_bw * in_fps / 1000;
|
|
ovl0_fbdc_bw = ovl0_fbdc_bw * in_fps / 1000;
|
|
ovl0_2l_bw = ovl0_2l_bw * in_fps / 1000;
|
|
ovl0_2l_fbdc_bw = ovl0_2l_fbdc_bw * in_fps / 1000;
|
|
wdma0_bw = wdma0_bw * in_fps / 1000;
|
|
rdma0_bw = rdma0_bw * out_fps / 1000;
|
|
|
|
__set_bw(DISP_MODULE_OVL0, ovl0_bw);
|
|
__set_fbdc_bw(DISP_MODULE_OVL0, ovl0_fbdc_bw);
|
|
__set_bw(DISP_MODULE_OVL0_2L, ovl0_2l_bw);
|
|
__set_fbdc_bw(DISP_MODULE_OVL0_2L, ovl0_2l_fbdc_bw);
|
|
__set_bw(DISP_MODULE_WDMA0, wdma0_bw);
|
|
__set_bw(DISP_MODULE_RDMA0, rdma0_bw);
|
|
} else {
|
|
ovl0_bw = ovl0_bw * out_fps / 1000;
|
|
ovl0_fbdc_bw = ovl0_fbdc_bw * out_fps / 1000;
|
|
ovl0_2l_bw = ovl0_2l_bw * out_fps / 1000;
|
|
ovl0_2l_fbdc_bw = ovl0_2l_fbdc_bw * out_fps / 1000;
|
|
wdma0_bw = 0;
|
|
rdma0_bw = 0;
|
|
|
|
__set_bw(DISP_MODULE_OVL0, ovl0_bw);
|
|
__set_fbdc_bw(DISP_MODULE_OVL0, ovl0_fbdc_bw);
|
|
__set_bw(DISP_MODULE_OVL0_2L, ovl0_2l_bw);
|
|
__set_fbdc_bw(DISP_MODULE_OVL0_2L, ovl0_2l_fbdc_bw);
|
|
__set_bw(DISP_MODULE_WDMA0, wdma0_bw);
|
|
__set_bw(DISP_MODULE_RDMA0, rdma0_bw);
|
|
}
|
|
|
|
if (is_dc) {
|
|
DISPDBG(
|
|
"%s ovl0:(%d,%d), ovl0_2l:(%d,%d), wdma0:%d, rdma0:%d ",
|
|
__func__,
|
|
ovl0_bw, ovl0_fbdc_bw,
|
|
ovl0_2l_bw, ovl0_2l_fbdc_bw,
|
|
wdma0_bw, rdma0_bw);
|
|
DISPDBG(
|
|
"in_fps:%llu, out_fps:%llu, bw:%llu\n",
|
|
in_fps, out_fps, *bandwidth);
|
|
} else
|
|
DISPDBG(
|
|
"%s ovl0:(%d,%d), ovl0_2l:(%d,%d), out_fps:%llu, bw:%llu\n",
|
|
__func__,
|
|
ovl0_bw, ovl0_fbdc_bw,
|
|
ovl0_2l_bw, ovl0_2l_fbdc_bw,
|
|
out_fps, *bandwidth);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int disp_pm_qos_set_rdma_bw(unsigned long long out_fps,
|
|
unsigned long long *bandwidth)
|
|
{
|
|
int ret = 0;
|
|
unsigned int rdma0_bw;
|
|
unsigned int ovl0_bw, ovl0_2l_bw, wdma0_bw;
|
|
unsigned int ovl0_fbdc_bw, ovl0_2l_fbdc_bw;
|
|
|
|
ret = __get_cmdq_slots(DISPSYS_SLOT_BASE,
|
|
DISP_SLOT_RDMA0_BW, &rdma0_bw);
|
|
|
|
/* cmdq get slot fail */
|
|
if (ret) {
|
|
DISP_PR_ERR("DISP CMDQ get slot failed:%d\n", ret);
|
|
disp_pm_qos_set_default_bw(bandwidth);
|
|
} else {
|
|
*bandwidth = (unsigned long long)rdma0_bw *
|
|
out_fps * OCCUPIED_BW_RATIO;
|
|
|
|
do_div(*bandwidth, 1000 * 1000);
|
|
|
|
/* Call __set_bw API to setup estimated data bw */
|
|
ovl0_bw = 0;
|
|
ovl0_fbdc_bw = 0;
|
|
ovl0_2l_bw = 0;
|
|
ovl0_2l_fbdc_bw = 0;
|
|
wdma0_bw = 0;
|
|
rdma0_bw = rdma0_bw * out_fps / 1000;
|
|
|
|
__set_bw(DISP_MODULE_OVL0, ovl0_bw);
|
|
__set_fbdc_bw(DISP_MODULE_OVL0, ovl0_fbdc_bw);
|
|
__set_bw(DISP_MODULE_OVL0_2L, ovl0_2l_bw);
|
|
__set_fbdc_bw(DISP_MODULE_OVL0_2L, ovl0_2l_fbdc_bw);
|
|
__set_bw(DISP_MODULE_WDMA0, wdma0_bw);
|
|
__set_bw(DISP_MODULE_RDMA0, rdma0_bw);
|
|
|
|
DISPDBG(
|
|
"%s rdma0:%d, out_fps:%llu, bw:%llu\n",
|
|
__func__, rdma0_bw, out_fps, *bandwidth);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|