557 lines
17 KiB
C
557 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _H_DDP_INFO
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#define _H_DDP_INFO
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#include <linux/types.h>
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#include <linux/wait.h>
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#include <disp_session.h>
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#include "ddp_hal.h"
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#include "lcm_drv.h"
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#include "ddp_ovl.h"
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#include "disp_event.h"
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#define _UFMT_ID_SHIFT 0
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#define _UFMT_ID_WIDTH 8
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#define _UFMT_RGBSWAP_SHIFT (_UFMT_ID_SHIFT+_UFMT_ID_WIDTH)
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#define _UFMT_RGBSWAP_WIDTH 1
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#define _UFMT_BYTESWAP_SHIFT (_UFMT_RGBSWAP_SHIFT+_UFMT_RGBSWAP_WIDTH)
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#define _UFMT_BYTESWAP_WIDTH 1
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#define _UFMT_FORMAT_SHIFT (_UFMT_BYTESWAP_SHIFT+_UFMT_BYTESWAP_WIDTH)
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#define _UFMT_FORMAT_WIDTH 5
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#define _UFMT_VDO_SHIFT (_UFMT_FORMAT_SHIFT+_UFMT_FORMAT_WIDTH)
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#define _UFMT_VDO_WIDTH 1
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#define _UFMT_BLOCK_SHIT (_UFMT_VDO_SHIFT+_UFMT_VDO_WIDTH)
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#define _UFMT_BLOCK_WIDTH 1
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#define _UFMT_bpp_SHIFT (_UFMT_BLOCK_SHIT+_UFMT_BLOCK_WIDTH)
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#define _UFMT_bpp_WIDTH 6
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#define _UFMT_RGB_SHIFT (_UFMT_bpp_SHIFT+_UFMT_bpp_WIDTH)
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#define _UFMT_RGB_WIDTH 1
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#define _MASK_SHIFT(val, width, shift) (((val)>>(shift)) & ((1<<(width))-1))
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#define MAKE_UNIFIED_COLOR_FMT(rgb, bpp, block, vdo, format, byteswap,\
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rgbswap, id) \
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( \
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((rgb) << _UFMT_RGB_SHIFT) | \
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((bpp) << _UFMT_bpp_SHIFT) | \
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((block) << _UFMT_BLOCK_SHIT) | \
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((vdo) << _UFMT_VDO_SHIFT) | \
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((format) << _UFMT_FORMAT_SHIFT) | \
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((byteswap) << _UFMT_BYTESWAP_SHIFT) | \
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((rgbswap) << _UFMT_RGBSWAP_SHIFT) | \
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((id) << _UFMT_ID_SHIFT))
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#define UFMT_GET_RGB(fmt) \
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_MASK_SHIFT(fmt, _UFMT_RGB_WIDTH, _UFMT_RGB_SHIFT)
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#define UFMT_GET_bpp(fmt) \
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_MASK_SHIFT(fmt, _UFMT_bpp_WIDTH, _UFMT_bpp_SHIFT)
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#define UFMT_GET_BLOCK(fmt) \
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_MASK_SHIFT(fmt, _UFMT_BLOCK_WIDTH, _UFMT_BLOCK_SHIT)
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#define UFMT_GET_VDO(fmt) \
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_MASK_SHIFT(fmt, _UFMT_VDO_WIDTH, _UFMT_VDO_SHIFT)
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#define UFMT_GET_FORMAT(fmt) \
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_MASK_SHIFT(fmt, _UFMT_FORMAT_WIDTH, _UFMT_FORMAT_SHIFT)
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#define UFMT_GET_BYTESWAP(fmt) \
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_MASK_SHIFT(fmt, _UFMT_BYTESWAP_WIDTH, _UFMT_BYTESWAP_SHIFT)
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#define UFMT_GET_RGBSWAP(fmt) \
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_MASK_SHIFT(fmt, _UFMT_RGBSWAP_WIDTH, _UFMT_RGBSWAP_SHIFT)
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#define UFMT_GET_ID(fmt) \
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_MASK_SHIFT(fmt, _UFMT_ID_WIDTH, _UFMT_ID_SHIFT)
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#define UFMT_GET_Bpp(fmt) \
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(UFMT_GET_bpp(fmt)/8)
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unsigned int ufmt_get_rgb(unsigned int fmt);
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unsigned int ufmt_get_bpp(unsigned int fmt);
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unsigned int ufmt_get_block(unsigned int fmt);
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unsigned int ufmt_get_vdo(unsigned int fmt);
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unsigned int ufmt_get_format(unsigned int fmt);
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unsigned int ufmt_get_byteswap(unsigned int fmt);
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unsigned int ufmt_get_rgbswap(unsigned int fmt);
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unsigned int ufmt_get_id(unsigned int fmt);
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unsigned int ufmt_get_Bpp(unsigned int fmt);
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unsigned int ufmt_is_old_fmt(unsigned int fmt);
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enum UNIFIED_COLOR_FMT {
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UFMT_UNKNOWN = 0,
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UFMT_Y8 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 7, 0, 0, 1),
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UFMT_RGBA4444 = MAKE_UNIFIED_COLOR_FMT(1, 16, 0, 0, 4, 0, 0, 2),
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UFMT_RGBA5551 = MAKE_UNIFIED_COLOR_FMT(1, 16, 0, 0, 0, 0, 0, 3),
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UFMT_RGB565 = MAKE_UNIFIED_COLOR_FMT(1, 16, 0, 0, 0, 0, 0, 4),
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UFMT_BGR565 = MAKE_UNIFIED_COLOR_FMT(1, 16, 0, 0, 0, 1, 0, 5),
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UFMT_RGB888 = MAKE_UNIFIED_COLOR_FMT(1, 24, 0, 0, 1, 1, 0, 6),
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UFMT_BGR888 = MAKE_UNIFIED_COLOR_FMT(1, 24, 0, 0, 1, 0, 0, 7),
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UFMT_RGBA8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 2, 1, 0, 8),
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UFMT_BGRA8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 2, 0, 0, 9),
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UFMT_ARGB8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 3, 1, 0, 10),
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UFMT_ABGR8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 3, 0, 0, 11),
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UFMT_RGBX8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 0, 0, 0, 12),
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UFMT_BGRX8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 0, 0, 0, 13),
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UFMT_XRGB8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 0, 0, 0, 14),
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UFMT_XBGR8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 0, 0, 0, 15),
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UFMT_AYUV = MAKE_UNIFIED_COLOR_FMT(0, 0, 0, 0, 0, 0, 0, 16),
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UFMT_YUV = MAKE_UNIFIED_COLOR_FMT(0, 0, 0, 0, 0, 0, 0, 17),
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UFMT_UYVY = MAKE_UNIFIED_COLOR_FMT(0, 16, 0, 0, 4, 0, 0, 18),
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UFMT_VYUY = MAKE_UNIFIED_COLOR_FMT(0, 16, 0, 0, 4, 1, 0, 19),
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UFMT_YUYV = MAKE_UNIFIED_COLOR_FMT(0, 16, 0, 0, 5, 0, 0, 20),
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UFMT_YVYU = MAKE_UNIFIED_COLOR_FMT(0, 16, 0, 0, 5, 1, 0, 21),
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UFMT_UYVY_BLK = MAKE_UNIFIED_COLOR_FMT(0, 16, 1, 0, 4, 0, 0, 22),
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UFMT_VYUY_BLK = MAKE_UNIFIED_COLOR_FMT(0, 16, 1, 0, 4, 1, 0, 23),
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UFMT_YUY2_BLK = MAKE_UNIFIED_COLOR_FMT(0, 16, 1, 0, 5, 0, 0, 24),
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UFMT_YVYU_BLK = MAKE_UNIFIED_COLOR_FMT(0, 16, 1, 0, 5, 1, 0, 25),
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UFMT_YV12 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 8, 1, 0, 26),
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UFMT_I420 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 8, 0, 0, 27),
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UFMT_YV16 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 9, 1, 0, 28),
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UFMT_I422 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 9, 0, 0, 29),
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UFMT_YV24 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 10, 1, 0, 30),
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UFMT_I444 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 10, 0, 0, 31),
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UFMT_NV12 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 12, 0, 0, 32),
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UFMT_NV21 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 12, 1, 0, 33),
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UFMT_NV12_BLK = MAKE_UNIFIED_COLOR_FMT(0, 8, 1, 0, 12, 0, 0, 34),
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UFMT_NV21_BLK = MAKE_UNIFIED_COLOR_FMT(0, 8, 1, 0, 12, 1, 0, 35),
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UFMT_NV12_BLK_FLD = MAKE_UNIFIED_COLOR_FMT(0, 8, 1, 1, 12, 0, 0, 36),
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UFMT_NV21_BLK_FLD = MAKE_UNIFIED_COLOR_FMT(0, 8, 1, 1, 12, 1, 0, 37),
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UFMT_NV16 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 13, 0, 0, 38),
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UFMT_NV61 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 13, 1, 0, 39),
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UFMT_NV24 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 14, 0, 0, 40),
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UFMT_NV42 = MAKE_UNIFIED_COLOR_FMT(0, 8, 0, 0, 14, 1, 0, 41),
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UFMT_PARGB8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 3, 1, 0, 42),
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UFMT_PABGR8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 3, 1, 1, 43),
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UFMT_PRGBA8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 3, 0, 1, 44),
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UFMT_PBGRA8888 = MAKE_UNIFIED_COLOR_FMT(1, 32, 0, 0, 3, 0, 0, 45),
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};
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char *unified_color_fmt_name(enum UNIFIED_COLOR_FMT fmt);
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enum UNIFIED_COLOR_FMT display_fmt_reg_to_unified_fmt(int fmt_reg_val,
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int byteswap, int rgbswap);
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int is_unified_color_fmt_supported(enum UNIFIED_COLOR_FMT ufmt);
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enum UNIFIED_COLOR_FMT disp_fmt_to_unified_fmt(enum DISP_FORMAT src_fmt);
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int ufmt_disable_X_channel(enum UNIFIED_COLOR_FMT src_fmt,
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enum UNIFIED_COLOR_FMT *dst_fmt, int *const_bld);
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int ufmt_disable_P(enum UNIFIED_COLOR_FMT src_fmt,
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enum UNIFIED_COLOR_FMT *dst_fmt);
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enum SBCH_BIT {
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UPDATE = 0,
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TRANS_EN = 1,
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CNST_EN = 2,
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BCH_BIT_NUM = 3
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};
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struct sbch {
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/* the number of ext layer on this phy */
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int ext_layer_num;/*ext:-1 phy:0~3*/
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unsigned long pre_addr;
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unsigned int dst_x;
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unsigned int dst_y;
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unsigned int dst_w;
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unsigned int dst_h;
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unsigned int height;
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unsigned int width;
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int phy_layer;
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int const_bld;
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enum UNIFIED_COLOR_FMT fmt;
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unsigned long long sbch_en_cnt;
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int full_trans_en;
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unsigned int layer_disable_by_partial_update;
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};
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struct disp_rect {
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int x;
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int y;
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int width;
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int height;
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};
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struct OVL_CONFIG_STRUCT {
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unsigned int ovl_index;
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unsigned int layer;
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unsigned int layer_en;
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unsigned int layer_disable_by_partial_update;
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enum OVL_LAYER_SOURCE source;
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enum UNIFIED_COLOR_FMT fmt;
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unsigned long addr;
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unsigned long real_addr;
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unsigned long vaddr;
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unsigned int src_x;
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unsigned int src_y;
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unsigned int src_w;
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unsigned int src_h;
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unsigned int src_pitch;
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unsigned int dst_x;
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unsigned int dst_y;
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unsigned int real_dst_x;
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unsigned int real_dst_y;
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unsigned int real_dst_w;
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unsigned int real_dst_h;
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unsigned int dst_w;
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unsigned int dst_h;
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unsigned int keyEn;
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unsigned int key;
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unsigned int aen;
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unsigned char alpha;
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unsigned int dim_color;
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unsigned int sur_aen;
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unsigned int src_alpha;
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unsigned int dst_alpha;
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unsigned int isTdshp;
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unsigned int isDirty;
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unsigned int buff_idx;
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unsigned int identity;
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unsigned int connected_type;
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enum DISP_BUFFER_TYPE security;
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unsigned int yuv_range;
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/* is this layer configured to OVL HW, for multiply OVL sync */
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int is_configured;
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int const_bld;
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int ext_sel_layer;
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int ext_layer;
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int phy_layer;
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};
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struct OVL_BASIC_STRUCT {
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unsigned int layer;
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unsigned int layer_en;
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enum UNIFIED_COLOR_FMT fmt;
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unsigned long addr;
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unsigned int src_w;
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unsigned int src_h;
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unsigned int src_pitch;
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unsigned int bpp;
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unsigned int gpu_mode;
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unsigned int adobe_mode;
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unsigned int ovl_gamma_out;
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unsigned int alpha;
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};
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enum RSZ_COLOR_FORMAT {
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ARGB8101010,
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RGB999,
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RGB888,
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UNKNOWN_RSZ_CFMT,
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};
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struct rsz_tile_params {
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u32 step;
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u32 int_offset;
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u32 sub_offset;
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u32 in_len;
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u32 out_len;
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};
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struct RSZ_CONFIG_STRUCT {
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struct rsz_tile_params tw[2];
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struct rsz_tile_params th;
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enum RSZ_COLOR_FORMAT fmt;
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u32 frm_in_w;
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u32 frm_in_h;
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u32 frm_out_w;
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u32 frm_out_h;
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u32 ratio;
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};
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struct RDMA_BASIC_STRUCT {
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unsigned long addr;
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unsigned int src_w;
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unsigned int src_h;
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unsigned int bpp;
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};
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struct rdma_bg_ctrl_t {
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unsigned int left;
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unsigned int right;
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unsigned int top;
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unsigned int bottom;
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};
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struct RDMA_CONFIG_STRUCT {
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unsigned int idx; /* instance index */
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enum UNIFIED_COLOR_FMT inputFormat;
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unsigned long address;
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unsigned int pitch;
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unsigned int width;
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unsigned int height;
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unsigned int dst_w;
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unsigned int dst_h;
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unsigned int dst_x;
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unsigned int dst_y;
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enum DISP_BUFFER_TYPE security;
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unsigned int yuv_range;
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struct rdma_bg_ctrl_t bg_ctrl;
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};
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struct WDMA_CONFIG_STRUCT {
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unsigned int idx; /* instance index */
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unsigned int srcWidth;
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unsigned int srcHeight; /* input */
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unsigned int clipX;
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unsigned int clipY;
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unsigned int clipWidth;
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unsigned int clipHeight; /* clip */
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enum UNIFIED_COLOR_FMT outputFormat;
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unsigned long dstAddress;
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unsigned int dstPitch; /* output */
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unsigned int useSpecifiedAlpha;
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unsigned char alpha;
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enum DISP_BUFFER_TYPE security;
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};
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struct golden_setting_context {
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unsigned int fifo_mode;
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unsigned int is_wrot_sram;
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unsigned int is_rsz_sram;
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unsigned int mmsys_clk;
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unsigned int hrt_num;
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unsigned int ext_hrt_num;
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unsigned int is_display_idle;
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unsigned int is_dc;
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unsigned int hrt_magicnum; /* by resolution */
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unsigned int ext_hrt_magicnum; /* by resolution */
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unsigned int dst_width;
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unsigned int dst_height;
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unsigned int ext_dst_width;
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unsigned int ext_dst_height;
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unsigned int fps;
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unsigned int is_one_layer;
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unsigned int rdma_width;
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unsigned int rdma_height;
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};
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struct disp_idlemgr_context {
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struct task_struct *primary_display_idlemgr_task;
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wait_queue_head_t idlemgr_wait_queue;
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unsigned long long idlemgr_last_kick_time;
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unsigned int enterulps;
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int session_mode_before_enter_idle;
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int is_primary_idle;
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int cur_lp_cust_mode;
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#if defined(CONFIG_MTK_DUAL_DISPLAY_SUPPORT) && \
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(CONFIG_MTK_DUAL_DISPLAY_SUPPORT == 2)
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struct task_struct *external_display_idlemgr_task;
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wait_queue_head_t ext_idlemgr_wait_queue;
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unsigned long long ext_idlemgr_last_kick_time;
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int is_external_idle;
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#endif
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};
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struct disp_ddp_path_config {
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/* for ovl */
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bool ovl_dirty;
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bool ovl_partial_dirty;
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bool rdma_dirty;
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bool wdma_dirty;
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bool dst_dirty;
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/*each bit represent one layer */
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int ovl_layer_dirty;
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/*each bit reprsent one layer, used for ovl engines */
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int ovl_layer_scanned;
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int overlap_layer_num;
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struct OVL_CONFIG_STRUCT ovl_config[TOTAL_REAL_OVL_LAYER_NUM];
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struct disp_rect ovl_partial_roi;
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struct RSZ_CONFIG_STRUCT rsz_config;
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struct RDMA_CONFIG_STRUCT rdma_config;
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struct WDMA_CONFIG_STRUCT wdma_config;
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struct LCM_PARAMS dispif_config;
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unsigned int lcm_bpp;
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unsigned int dst_w;
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unsigned int dst_h;
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struct disp_rect rsz_src_roi;
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struct disp_rect rsz_dst_roi;
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unsigned int fps;
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struct golden_setting_context *p_golden_setting_context;
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void *path_handle;
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bool rsz_enable;
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int hrt_path;
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int hrt_scale;
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int sbch_enable;
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int read_dum_reg[OVL_NUM];
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};
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struct rx_data {
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unsigned char byte0;
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unsigned char byte1;
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unsigned char byte2;
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unsigned char byte3;
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};
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struct ddp_lcm_read_cmd_table {
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unsigned char cmd[3];
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struct rx_data data[3];
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};
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struct ddp_lcm_write_cmd_table {
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unsigned char cmd;
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unsigned char count;
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unsigned char para_list[64];
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};
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/* dpmgr_ioctl cmd definition */
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enum DDP_IOCTL_NAME {
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/* DSI operation */
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DDP_SWITCH_DSI_MODE = 0,
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DDP_STOP_VIDEO_MODE = 1,
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DDP_BACK_LIGHT = 2,
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DDP_SWITCH_LCM_MODE = 3,
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DDP_DPI_FACTORY_TEST = 4,
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DDP_DSI_IDLE_CLK_CLOSED = 5,
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DDP_DSI_IDLE_CLK_OPEN = 6,
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DDP_DSI_PORCH_CHANGE = 7,
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DDP_PHY_CLK_CHANGE = 8,
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DDP_ENTER_ULPS = 9,
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DDP_EXIT_ULPS = 10,
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DDP_RDMA_GOLDEN_SETTING = 11,
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DDP_OVL_GOLDEN_SETTING,
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DDP_PARTIAL_UPDATE,
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DDP_UPDATE_PLL_CLK_ONLY,
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DDP_DPI_FACTORY_RESET,
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DDP_DSI_PORCH_ADDR,
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DDP_DSI_SW_INIT,
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DDP_DSI_MIPI_POWER_ON,
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DDP_OVL_MVA_REPLACEMENT,
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DDP_DSI_ENABLE_TE,
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|
};
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|
|
|
struct ddp_io_golden_setting_arg {
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enum dst_module_type dst_mod_type;
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int is_decouple_mode;
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unsigned int dst_w;
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|
unsigned int dst_h;
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|
};
|
|
|
|
struct ddp_fb_info {
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unsigned int fb_pa;
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unsigned int fb_mva;
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|
unsigned int fb_size;
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|
};
|
|
|
|
typedef int (*ddp_module_notify)(enum DISP_MODULE_ENUM, enum DISP_PATH_EVENT);
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|
|
|
struct DDP_MODULE_DRIVER {
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|
enum DISP_MODULE_ENUM module;
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|
int (*init)(enum DISP_MODULE_ENUM module, void *handle);
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int (*deinit)(enum DISP_MODULE_ENUM module, void *handle);
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|
int (*config)(enum DISP_MODULE_ENUM module,
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|
struct disp_ddp_path_config *config, void *handle);
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|
int (*start)(enum DISP_MODULE_ENUM module, void *handle);
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|
int (*trigger)(enum DISP_MODULE_ENUM module, void *handle);
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|
int (*stop)(enum DISP_MODULE_ENUM module, void *handle);
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|
int (*reset)(enum DISP_MODULE_ENUM module, void *handle);
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|
int (*power_on)(enum DISP_MODULE_ENUM module, void *handle);
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|
int (*power_off)(enum DISP_MODULE_ENUM module, void *handle);
|
|
int (*suspend)(enum DISP_MODULE_ENUM module, void *handle);
|
|
int (*resume)(enum DISP_MODULE_ENUM module, void *handle);
|
|
int (*is_idle)(enum DISP_MODULE_ENUM module);
|
|
int (*is_busy)(enum DISP_MODULE_ENUM module);
|
|
int (*dump_info)(enum DISP_MODULE_ENUM module, int level);
|
|
int (*bypass)(enum DISP_MODULE_ENUM module, int bypass);
|
|
int (*build_cmdq)(enum DISP_MODULE_ENUM module, void *cmdq_handle,
|
|
enum CMDQ_STATE state);
|
|
int (*set_lcm_utils)(enum DISP_MODULE_ENUM module,
|
|
struct LCM_DRIVER *lcm_drv);
|
|
int (*set_listener)(enum DISP_MODULE_ENUM module,
|
|
ddp_module_notify notify);
|
|
int (*cmd)(enum DISP_MODULE_ENUM module, unsigned int msg,
|
|
unsigned long arg, void *handle);
|
|
int (*ioctl)(enum DISP_MODULE_ENUM module, void *handle,
|
|
enum DDP_IOCTL_NAME ioctl_cmd, void *params);
|
|
int (*enable_irq)(enum DISP_MODULE_ENUM module, void *handle,
|
|
enum DDP_IRQ_LEVEL irq_level);
|
|
int (*connect)(enum DISP_MODULE_ENUM module,
|
|
enum DISP_MODULE_ENUM prev, enum DISP_MODULE_ENUM next,
|
|
int connect, void *handle);
|
|
int (*switch_to_nonsec)(enum DISP_MODULE_ENUM module, void *handle);
|
|
};
|
|
|
|
|
|
/* dsi */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_dsi0;
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_dsi1;
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_dsidual;
|
|
/* dpi */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_dpi;
|
|
|
|
/* ovl */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_ovl;
|
|
/* rdma */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_rdma;
|
|
/* wdma */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_wdma;
|
|
/* color */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_color;
|
|
/* aal */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_aal;
|
|
/* gamma */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_gamma;
|
|
/* dither */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_dither;
|
|
/* ccorr */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_ccorr;
|
|
/* split */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_split;
|
|
/* rsz */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_rsz;
|
|
/* postmask */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_postmask;
|
|
|
|
/* pwm */
|
|
extern struct DDP_MODULE_DRIVER ddp_driver_pwm;
|
|
|
|
struct ddp_reg {
|
|
const char *reg_dt_name;
|
|
unsigned long reg_pa_check;
|
|
unsigned int reg_irq_check;
|
|
unsigned int irq_max_bit;
|
|
|
|
/* get info for DT */
|
|
unsigned long reg_va;
|
|
unsigned int reg_irq;
|
|
};
|
|
|
|
struct ddp_module {
|
|
/* sw info */
|
|
enum DISP_MODULE_ENUM module_id;
|
|
enum DISP_MODULE_TYPE_ENUM module_type;
|
|
const char *module_name;
|
|
unsigned int can_connect; /* module can be connect if 1 */
|
|
struct DDP_MODULE_DRIVER *module_driver;
|
|
|
|
/* hw info */
|
|
struct ddp_reg reg_info;
|
|
};
|
|
|
|
unsigned int is_ddp_module(enum DISP_MODULE_ENUM module);
|
|
unsigned int is_ddp_module_has_reg_info(enum DISP_MODULE_ENUM module);
|
|
const char *ddp_get_module_name(enum DISP_MODULE_ENUM module);
|
|
unsigned int _can_connect(enum DISP_MODULE_ENUM module);
|
|
struct DDP_MODULE_DRIVER *ddp_get_module_driver(enum DISP_MODULE_ENUM module);
|
|
void ddp_set_module_driver(enum DISP_MODULE_ENUM module,
|
|
struct DDP_MODULE_DRIVER *drv);
|
|
const char *ddp_get_module_dtname(enum DISP_MODULE_ENUM module);
|
|
unsigned int ddp_get_module_checkirq(enum DISP_MODULE_ENUM module);
|
|
unsigned long ddp_get_module_pa(enum DISP_MODULE_ENUM module);
|
|
unsigned int ddp_get_module_max_irq_bit(enum DISP_MODULE_ENUM module);
|
|
unsigned int ddp_is_irq_enable(enum DISP_MODULE_ENUM module);
|
|
void ddp_module_irq_disable(enum DISP_MODULE_ENUM module);
|
|
void ddp_set_module_va(enum DISP_MODULE_ENUM module, unsigned long va);
|
|
void ddp_set_module_irq(enum DISP_MODULE_ENUM module, unsigned int irq);
|
|
unsigned long ddp_get_module_va(enum DISP_MODULE_ENUM module);
|
|
unsigned int ddp_get_module_irq(enum DISP_MODULE_ENUM module);
|
|
unsigned int is_reg_addr_valid(unsigned int isVa, unsigned long addr);
|
|
unsigned int ddp_get_module_num_by_t(enum DISP_MODULE_TYPE_ENUM module_t);
|
|
enum DISP_MODULE_ENUM ddp_get_module_id_by_idx(
|
|
enum DISP_MODULE_TYPE_ENUM module_t, unsigned int idx);
|
|
enum DISP_MODULE_ENUM disp_irq_to_module(unsigned int irq);
|
|
const char *ddp_get_ioctl_name(enum DDP_IOCTL_NAME ioctl);
|
|
extern int disp_late_bias_enable(void);
|
|
extern int display_bias_enable(void);
|
|
extern int display_bias_regulator_init(void);
|
|
|
|
#endif
|