500 lines
14 KiB
C
500 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#define LOG_TAG "RSZ"
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#include "ddp_info.h"
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#include "ddp_reg.h"
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#include "ddp_reg_rsz.h"
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#include "ddp_log.h"
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#include "disp_helper.h"
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#include "ddp_clkmgr.h"
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#include "ddp_hal.h"
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#include <linux/delay.h>
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#include "ddp_rsz.h"
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#include "primary_display.h"
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#include "disp_rect.h"
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#define UNIT 32768
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#define TILE_LOSS 4
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#define TILE_LOSS_LEFT 4
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#define TILE_LOSS_RIGHT 4
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int rsz_calc_tile_params(u32 frm_in_len, u32 frm_out_len,
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bool tile_mode, struct rsz_tile_params *t)
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{
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u32 tile_loss = 0;
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u32 step = 0;
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u32 init_phase = 0;
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u32 offset[2] = { 0 };
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u32 int_offset[2] = { 0 };
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u32 sub_offset[2] = { 0 };
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u32 tile_in_len[2] = { 0 };
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u32 tile_out_len = 0;
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if (tile_mode)
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tile_loss = TILE_LOSS;
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step = (UNIT * (frm_in_len - 1) + (frm_out_len - 2)) /
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(frm_out_len - 1);
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/* left half */
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offset[0] = (step * (frm_out_len - 1) - UNIT * (frm_in_len - 1)) / 2;
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init_phase = UNIT - offset[0];
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int_offset[0] = init_phase / UNIT;
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sub_offset[0] = init_phase - UNIT * int_offset[0];
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if (tile_mode) {
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tile_in_len[0] = frm_in_len / 2 + tile_loss;
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tile_out_len = frm_out_len / 2;
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} else {
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tile_in_len[0] = frm_in_len;
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tile_out_len = frm_out_len;
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}
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t[0].step = step;
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t[0].int_offset = int_offset[0];
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t[0].sub_offset = sub_offset[0];
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t[0].in_len = tile_in_len[0];
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t[0].out_len = tile_out_len;
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DDPDBG("%s:%s:step:%u,offset:%u.%u,len:%u->%u\n", __func__,
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tile_mode ? "dual" : "single", t[0].step, t[0].int_offset,
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t[0].sub_offset, t[0].in_len, t[0].out_len);
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if (!tile_mode)
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return 0;
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/* right half */
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offset[1] = (init_phase + frm_out_len / 2 * step) -
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(frm_in_len / 2 - tile_loss -
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(offset[0] ? 1 : 0) + 1) * UNIT + UNIT;
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int_offset[1] = offset[1] / UNIT;
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sub_offset[1] = offset[1] - UNIT * int_offset[1];
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tile_in_len[1] = frm_in_len / 2 + tile_loss + (offset[0] ? 1 : 0);
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if (int_offset[1] & 0x1) {
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int_offset[1]++;
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tile_in_len[1]++;
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DDPMSG("right tile int_offset: make odd to even\n");
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}
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t[1].step = step;
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t[1].int_offset = int_offset[1];
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t[1].sub_offset = sub_offset[1];
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t[1].in_len = tile_in_len[1];
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t[1].out_len = tile_out_len;
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DDPDBG("%s:%s:step:%u,offset:%u.%u,len:%u->%u\n", __func__,
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tile_mode ? "dual" : "single", t[1].step, t[1].int_offset,
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t[1].sub_offset, t[1].in_len, t[1].out_len);
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return 0;
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}
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static unsigned long rsz_base_addr(enum DISP_MODULE_ENUM module)
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{
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switch (module) {
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case DISP_MODULE_RSZ0:
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return DISPSYS_RSZ0_BASE;
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default:
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DDPERR("invalid rsz module:%s\n", ddp_get_module_name(module));
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break;
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}
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return 0;
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}
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static int rsz_clock_on(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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ddp_clk_prepare_enable(ddp_get_module_clk_id(module));
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return 0;
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}
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static int rsz_clock_off(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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ddp_clk_disable_unprepare(ddp_get_module_clk_id(module));
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return 0;
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}
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static int rsz_init(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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rsz_clock_on(module, qhandle);
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return 0;
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}
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static int rsz_deinit(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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rsz_clock_off(module, qhandle);
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return 0;
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}
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static int rsz_power_on(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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rsz_clock_on(module, qhandle);
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return 0;
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}
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static int rsz_power_off(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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rsz_clock_off(module, qhandle);
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return 0;
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}
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static int rsz_get_in_out_roi(struct disp_ddp_path_config *pconfig,
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u32 *in_w, u32 *in_h, u32 *out_w, u32 *out_h)
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{
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struct disp_rect rsz_src_roi = pconfig->rsz_src_roi;
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struct disp_rect rsz_dst_roi = pconfig->rsz_dst_roi;
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if (pconfig->rsz_enable) {
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*in_w = rsz_src_roi.width;
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*in_h = rsz_src_roi.height;
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*out_w = rsz_dst_roi.width;
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*out_h = rsz_dst_roi.height;
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}
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DDPDBG("[RPO] module=%s,in(w,h)=(%d,%d),out(w,h)=(%d,%d)\n",
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ddp_get_module_name(DISP_MODULE_RSZ0),
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*in_w, *in_h, *out_w, *out_h);
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return 0;
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}
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static int rsz_check_params(struct RSZ_CONFIG_STRUCT *rsz_config)
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{
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if ((rsz_config->frm_in_w != rsz_config->frm_out_w ||
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rsz_config->frm_in_h != rsz_config->frm_out_h) &&
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rsz_config->frm_in_w > RSZ_TILE_LENGTH) {
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DISPERR("%s:need rsz but input width(%u) > limit(%u)\n",
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__func__, rsz_config->frm_in_w, RSZ_TILE_LENGTH);
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return -EINVAL;
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}
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return 0;
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}
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static int disp_rsz_set_color_format(enum RSZ_COLOR_FORMAT fmt)
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{
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u32 reg_val = 0;
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switch (fmt) {
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case ARGB8101010:
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reg_val = REG_FLD_VAL(FLD_RSZ_POWER_SAVING, 0x0);
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reg_val |= REG_FLD_VAL(FLD_RSZ_RGB_BIT_MODE, 0x0);
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break;
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case RGB999:
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reg_val = REG_FLD_VAL(FLD_RSZ_POWER_SAVING, 0x1);
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reg_val |= REG_FLD_VAL(FLD_RSZ_RGB_BIT_MODE, 0x0);
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break;
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case RGB888:
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reg_val = REG_FLD_VAL(FLD_RSZ_POWER_SAVING, 0x1);
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reg_val |= REG_FLD_VAL(FLD_RSZ_RGB_BIT_MODE, 0x1);
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break;
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default:
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DDPMSG("unknown resize color format\n");
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break;
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}
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return reg_val;
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}
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static int rsz_config(enum DISP_MODULE_ENUM module,
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struct disp_ddp_path_config *pconfig, void *qhandle)
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{
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unsigned long rsz_base = rsz_base_addr(module);
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struct RSZ_CONFIG_STRUCT *rsz_config = &pconfig->rsz_config;
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u32 in_w = 0, in_h = 0, out_w = 0, out_h = 0;
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u32 reg_val = 0;
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u32 tile_idx = 0;
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u32 frm_in_w = pconfig->dst_w, frm_in_h = pconfig->dst_h;
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u32 frm_out_w = pconfig->dst_w, frm_out_h = pconfig->dst_h;
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/* platform dependent: color_fmt, tile_mode */
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enum RSZ_COLOR_FORMAT fmt = RGB888;
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bool tile_mode = false;
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if (!pconfig->ovl_dirty && !pconfig->dst_dirty)
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return 0;
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if (pconfig->dst_dirty) {
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rsz_config->frm_out_w = pconfig->dst_w;
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rsz_config->frm_out_h = pconfig->dst_h;
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}
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rsz_get_in_out_roi(pconfig, &frm_in_w, &frm_in_h,
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&frm_out_w, &frm_out_h);
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rsz_config->frm_in_w = frm_in_w;
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rsz_config->frm_in_h = frm_in_h;
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rsz_config->frm_out_w = frm_out_w;
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rsz_config->frm_out_h = frm_out_h;
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if (rsz_check_params(rsz_config)) {
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static bool dump;
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struct OVL_CONFIG_STRUCT *c = &pconfig->ovl_config[0];
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DISPERR("%s:L%d:en%d:(%u,%u,%ux%u)->(%u,%u,%ux%u)\n",
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__func__, c->layer, c->layer_en,
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c->src_x, c->src_y, c->src_w, c->src_h,
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c->dst_x, c->dst_y, c->dst_w, c->dst_h);
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if (!dump) {
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dump = true;
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primary_display_diagnose(__func__, __LINE__);
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disp_aee_print("need rsz but input w(%u) > (%u)\n",
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rsz_config->frm_in_w, RSZ_TILE_LENGTH);
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}
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return -EINVAL;
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}
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rsz_calc_tile_params(rsz_config->frm_in_w, rsz_config->frm_out_w,
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tile_mode, rsz_config->tw);
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rsz_calc_tile_params(rsz_config->frm_in_h, rsz_config->frm_out_h,
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tile_mode, &rsz_config->th);
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in_w = rsz_config->tw[tile_idx].in_len;
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in_h = rsz_config->th.in_len;
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out_w = rsz_config->tw[tile_idx].out_len;
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out_h = rsz_config->th.out_len;
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if (in_w > out_w || in_h > out_h) {
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DDPERR("DISP_RSZ only supports scaling-up,(%dx%d)->(%dx%d)\n",
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in_w, in_h, out_w, out_h);
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return -EINVAL;
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}
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reg_val = 0;
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reg_val |= REG_FLD_VAL(FLD_RSZ_HORIZONTAL_EN, (in_w != out_w));
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reg_val |= REG_FLD_VAL(FLD_RSZ_VERTICAL_EN, (in_h != out_h));
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reg_val |= REG_FLD_VAL(FLD_RSZ_HORIZONTAL_TABLE_SELECT,
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(fmt == ARGB8101010 ? 0x1 : 0x0));
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reg_val |= REG_FLD_VAL(FLD_RSZ_VERTICAL_TABLE_SELECT,
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(fmt == ARGB8101010 ? 0x1 : 0x0));
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DISP_REG_SET(qhandle, rsz_base + DISP_REG_RSZ_CONTROL_1, reg_val);
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DDPDBG("%s:CONTROL_1:0x%x\n", __func__, reg_val);
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reg_val = disp_rsz_set_color_format(fmt);
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DISP_REG_SET(qhandle, rsz_base + DISP_REG_RSZ_CONTROL_2, reg_val);
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DDPDBG("%s:CONTROL_2:0x%x\n", __func__, reg_val);
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DISP_REG_SET(qhandle, rsz_base + DISP_REG_RSZ_INPUT_IMAGE,
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in_h << 16 | in_w);
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DISP_REG_SET(qhandle, rsz_base + DISP_REG_RSZ_OUTPUT_IMAGE,
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out_h << 16 | out_w);
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DDPDBG("%s:%s:(%ux%u)->(%ux%u)\n",
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__func__, ddp_get_module_name(module), in_w, in_h, out_w, out_h);
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DISP_REG_SET(qhandle, rsz_base + DISP_REG_RSZ_HORIZONTAL_COEFF_STEP,
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rsz_config->tw[tile_idx].step);
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DISP_REG_SET(qhandle, rsz_base + DISP_REG_RSZ_VERTICAL_COEFF_STEP,
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rsz_config->th.step);
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DISP_REG_SET(qhandle,
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rsz_base + DISP_REG_RSZ_LUMA_HORIZONTAL_INTEGER_OFFSET,
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rsz_config->tw[tile_idx].int_offset);
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DISP_REG_SET(qhandle,
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rsz_base + DISP_REG_RSZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET,
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rsz_config->tw[tile_idx].sub_offset);
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DISP_REG_SET(qhandle,
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rsz_base + DISP_REG_RSZ_LUMA_VERTICAL_INTEGER_OFFSET,
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rsz_config->th.int_offset);
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DISP_REG_SET(qhandle,
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rsz_base + DISP_REG_RSZ_LUMA_VERTICAL_SUBPIXEL_OFFSET,
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rsz_config->th.sub_offset);
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return 0;
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}
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static int rsz_start(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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unsigned long rsz_base = rsz_base_addr(module);
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u32 reg_val = 0;
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if (disp_helper_get_option(DISP_OPT_SHADOW_REGISTER)) {
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reg_val = 0;
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if (disp_helper_get_option(DISP_OPT_SHADOW_MODE) == 0) {
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/* full shadow mode, read shadow reg */
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} else if (disp_helper_get_option(DISP_OPT_SHADOW_MODE) == 1) {
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/* force commit, read shadow reg */
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reg_val |= REG_FLD_VAL(FLD_RSZ_FORCE_COMMIT, 0x1);
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} else if (disp_helper_get_option(DISP_OPT_SHADOW_MODE) == 2) {
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/* bypass shadow, read shadow reg */
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reg_val |= REG_FLD_VAL(FLD_RSZ_BYPASS_SHADOW, 0x1);
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}
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reg_val |= REG_FLD_VAL(FLD_RSZ_READ_WRK_REG, 0x0);
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DISP_REG_SET(qhandle, rsz_base + DISP_REG_RSZ_SHADOW_CTRL,
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reg_val);
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}
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DISP_REG_SET_FIELD(qhandle, FLD_RSZ_EN,
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rsz_base + DISP_REG_RSZ_ENABLE, 0x1);
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DISP_REG_SET(qhandle, rsz_base + DISP_REG_RSZ_DEBUG_SEL, 0x3);
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return 0;
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}
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static int rsz_stop(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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unsigned long rsz_base = rsz_base_addr(module);
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DISP_REG_SET_FIELD(qhandle, FLD_RSZ_EN,
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rsz_base + DISP_REG_RSZ_ENABLE, 0x0);
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return 0;
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}
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static int rsz_reset(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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unsigned long rsz_base = rsz_base_addr(module);
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/* reset=1 -> wait 0.1 msec -> reset=0 */
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if (qhandle == NULL) {
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DISP_REG_SET_FIELD(NULL, FLD_RSZ_RST,
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rsz_base + DISP_REG_RSZ_ENABLE, 0x1);
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usleep_range(100, 200);
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DISP_REG_SET_FIELD(NULL, FLD_RSZ_RST,
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rsz_base + DISP_REG_RSZ_ENABLE, 0x0);
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} else {
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DDPDBG("DISP_RSZ does not support cmdq reset\n");
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}
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return 0;
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}
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static int rsz_suspend(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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rsz_clock_off(module, qhandle);
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return 0;
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}
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static int rsz_resume(enum DISP_MODULE_ENUM module, void *qhandle)
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{
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rsz_clock_on(module, qhandle);
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return 0;
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}
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void rsz_dump_analysis(enum DISP_MODULE_ENUM module)
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{
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unsigned long rsz_base = rsz_base_addr(module);
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u32 enable = 0;
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u32 con1 = 0;
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u32 con2 = 0;
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u32 int_flag = 0;
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u32 in_size = 0;
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u32 out_size = 0;
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u32 in_pos = 0;
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u32 shadow = 0;
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enable = DISP_REG_GET(rsz_base + DISP_REG_RSZ_ENABLE);
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con1 = DISP_REG_GET(rsz_base + DISP_REG_RSZ_CONTROL_1);
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con2 = DISP_REG_GET(rsz_base + DISP_REG_RSZ_CONTROL_2);
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int_flag = DISP_REG_GET(rsz_base + DISP_REG_RSZ_INT_FLAG);
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in_size = DISP_REG_GET(rsz_base + DISP_REG_RSZ_INPUT_IMAGE);
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out_size = DISP_REG_GET(rsz_base + DISP_REG_RSZ_OUTPUT_IMAGE);
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in_pos = DISP_REG_GET(rsz_base + DISP_REG_RSZ_DEBUG);
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shadow = DISP_REG_GET(rsz_base + DISP_REG_RSZ_SHADOW_CTRL);
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DDPDUMP("== DISP %s ANALYSIS ==\n", ddp_get_module_name(module));
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DISP_REG_SET(NULL, rsz_base + DISP_REG_RSZ_DEBUG_SEL, 0x3);
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DDPDUMP(
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"en:%d,rst:%d,h_en:%d,v_en:%d,h_table:%d,v_table:%d,dcm_dis:%d,int_en:%d,wclr_en:%d\n",
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REG_FLD_VAL_GET(FLD_RSZ_EN, enable),
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REG_FLD_VAL_GET(FLD_RSZ_RST, enable),
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REG_FLD_VAL_GET(FLD_RSZ_HORIZONTAL_EN, con1),
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REG_FLD_VAL_GET(FLD_RSZ_VERTICAL_EN, con1),
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REG_FLD_VAL_GET(FLD_RSZ_HORIZONTAL_TABLE_SELECT, con1),
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REG_FLD_VAL_GET(FLD_RSZ_VERTICAL_TABLE_SELECT, con1),
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REG_FLD_VAL_GET(FLD_RSZ_DCM_DIS, con1),
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REG_FLD_VAL_GET(FLD_RSZ_INTEN, con1),
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REG_FLD_VAL_GET(FLD_RSZ_INT_WCLR_EN, con1));
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DDPDUMP(
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"power_saving:%d,rgb_bit_mode:%d,frm_start:%d,frm_end:%d,size_err:%d,sof_rst:%d\n",
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REG_FLD_VAL_GET(FLD_RSZ_POWER_SAVING, con2),
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REG_FLD_VAL_GET(FLD_RSZ_RGB_BIT_MODE, con2),
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REG_FLD_VAL_GET(FLD_RSZ_FRAME_START, int_flag),
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REG_FLD_VAL_GET(FLD_RSZ_FRAME_END, int_flag),
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REG_FLD_VAL_GET(FLD_RSZ_SIZE_ERR, int_flag),
|
|
REG_FLD_VAL_GET(FLD_RSZ_SOF_RESET, int_flag));
|
|
DDPDUMP("in(%ux%u),out(%ux%u),h_step:%d,v_step:%d\n",
|
|
REG_FLD_VAL_GET(FLD_RSZ_INPUT_IMAGE_W, in_size),
|
|
REG_FLD_VAL_GET(FLD_RSZ_INPUT_IMAGE_H, in_size),
|
|
REG_FLD_VAL_GET(FLD_RSZ_OUTPUT_IMAGE_W, out_size),
|
|
REG_FLD_VAL_GET(FLD_RSZ_OUTPUT_IMAGE_H, out_size),
|
|
DISP_REG_GET(rsz_base + DISP_REG_RSZ_HORIZONTAL_COEFF_STEP),
|
|
DISP_REG_GET(rsz_base + DISP_REG_RSZ_VERTICAL_COEFF_STEP));
|
|
DDPDUMP("luma_h:%d.%d,luma_v:%d.%d\n",
|
|
DISP_REG_GET(rsz_base +
|
|
DISP_REG_RSZ_LUMA_HORIZONTAL_INTEGER_OFFSET),
|
|
DISP_REG_GET(rsz_base +
|
|
DISP_REG_RSZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET),
|
|
DISP_REG_GET(rsz_base +
|
|
DISP_REG_RSZ_LUMA_VERTICAL_INTEGER_OFFSET),
|
|
DISP_REG_GET(rsz_base +
|
|
DISP_REG_RSZ_LUMA_VERTICAL_SUBPIXEL_OFFSET));
|
|
DDPDUMP(
|
|
"dbg_sel:%d, in(%u,%u);shadow_ctrl:bypass:%d,force:%d,read_working:%d\n",
|
|
DISP_REG_GET(rsz_base + DISP_REG_RSZ_DEBUG_SEL),
|
|
in_pos & 0xFFFF, (in_pos >> 16) & 0xFFFF,
|
|
REG_FLD_VAL_GET(FLD_RSZ_BYPASS_SHADOW, shadow),
|
|
REG_FLD_VAL_GET(FLD_RSZ_FORCE_COMMIT, shadow),
|
|
REG_FLD_VAL_GET(FLD_RSZ_READ_WRK_REG, shadow));
|
|
}
|
|
|
|
void rsz_dump_reg(enum DISP_MODULE_ENUM module)
|
|
{
|
|
unsigned long rsz_base = rsz_base_addr(module);
|
|
int i = 0;
|
|
|
|
DDPDUMP("== DISP %s REGS ==\n", ddp_get_module_name(module));
|
|
for (i = 0; i < 3; i++) {
|
|
DDPDUMP("0x%03X: 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
|
i * 0x10, DISP_REG_GET(rsz_base + i * 0x10),
|
|
DISP_REG_GET(rsz_base + i * 0x10 + 0x4),
|
|
DISP_REG_GET(rsz_base + i * 0x10 + 0x8),
|
|
DISP_REG_GET(rsz_base + i * 0x10 + 0xC));
|
|
}
|
|
DDPDUMP("0x044: 0x%08x 0x%08x; 0x0F0: 0x%08x\n",
|
|
DISP_REG_GET(rsz_base + 0x44), DISP_REG_GET(rsz_base + 0x48),
|
|
DISP_REG_GET(rsz_base + 0xF0));
|
|
}
|
|
|
|
static int rsz_dump_info(enum DISP_MODULE_ENUM module, int level)
|
|
{
|
|
rsz_dump_analysis(module);
|
|
rsz_dump_reg(module);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rsz_bypass(enum DISP_MODULE_ENUM module, int bypass)
|
|
{
|
|
unsigned long rsz_base = rsz_base_addr(module);
|
|
|
|
if (bypass) {
|
|
/* use relay mode */
|
|
DISP_REG_SET_FIELD(NULL, FLD_RSZ_EN,
|
|
rsz_base + DISP_REG_RSZ_ENABLE, 0x1);
|
|
DISP_REG_SET_FIELD(NULL, FLD_RSZ_HORIZONTAL_EN,
|
|
rsz_base + DISP_REG_RSZ_CONTROL_1, 0x0);
|
|
DISP_REG_SET_FIELD(NULL, FLD_RSZ_VERTICAL_EN,
|
|
rsz_base + DISP_REG_RSZ_CONTROL_1, 0x0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct DDP_MODULE_DRIVER ddp_driver_rsz = {
|
|
.init = rsz_init,
|
|
.deinit = rsz_deinit,
|
|
.config = rsz_config,
|
|
.start = rsz_start,
|
|
.stop = rsz_stop,
|
|
.reset = rsz_reset,
|
|
.power_on = rsz_power_on,
|
|
.power_off = rsz_power_off,
|
|
.suspend = rsz_suspend,
|
|
.resume = rsz_resume,
|
|
.dump_info = rsz_dump_info,
|
|
.bypass = rsz_bypass,
|
|
};
|