623 lines
12 KiB
C
623 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifdef CONFIG_MTK_M4U
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#include <m4u.h>
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#else
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#define m4u_dump_reg_for_vpu_hang_issue(...)
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#endif
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/io.h>
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#include "vpu_reg.h"
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#include "vpu_cmn.h"
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#include "vpu_cfg.h"
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#include "vpu_dump.h"
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#include "vpu_hw.h"
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#include <plat_debug_api.h>
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#define INFRA_CFG 0x10001000
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#define SLEEP 0x10006000
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#define GALS 0x1020E000
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#define SMI_CMN0 0x10254000
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#define SMI_CMN1 0x10255000
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#define IPU_CONN 0x19000000
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#define IPU_VCORE 0x19020000
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static unsigned long m_infra_cfg;
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static unsigned long m_sleep;
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static unsigned long m_gals;
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static unsigned long m_smi_cmn0;
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static unsigned long m_smi_cmn1;
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static unsigned long m_ipu_conn;
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static unsigned long m_ipu_vcore;
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#define VPU_MEM_ALLOC (0xFFFFFFFF)
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struct vpu_iova {
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uint32_t addr; /* iova setting */
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uint32_t size;
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uint32_t bin; /* offset in binary */
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unsigned long va; /* mapped va */
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uint32_t iova; /* allocated iova */
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};
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static struct vpu_dmp *vd[MTK_VPU_CORE];
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static struct vpu_dmp *vpu_dmp_get(int c)
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{
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if (c < 0 || c >= MTK_VPU_CORE)
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return NULL;
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return vd[c];
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}
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static void vpu_dmp_set(int c, struct vpu_dmp *d)
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{
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if (c < 0 || c >= MTK_VPU_CORE)
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return;
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vd[c] = d;
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}
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static void vpu_dmp_seq_time(struct seq_file *s, uint64_t t)
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{
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uint32_t nsec;
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nsec = do_div(t, 1000000000);
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seq_printf(s, "%lu.%06lu", (unsigned long)t,
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(unsigned long)nsec/1000);
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}
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static int vpu_dmp_alloc(int c)
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{
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struct vpu_dmp *d;
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if (c < 0 || c >= MTK_VPU_CORE)
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return -EINVAL;
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d = vpu_dmp_get(c);
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if (d)
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goto out;
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d = kvmalloc(sizeof(struct vpu_dmp), GFP_KERNEL);
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if (!d)
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return -ENOMEM;
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out:
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memset(d, 0, sizeof(struct vpu_dmp));
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vpu_dmp_set(c, d);
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return 0;
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}
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/**
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* vpu_dmp_free_locked() - Free VPU register and memory dump
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* @vd: vpu device
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*
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* vd->lock must be locked before calling this function
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*/
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void vpu_dmp_free_locked(int c)
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{
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struct vpu_dmp *d;
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if (c < 0 || c >= MTK_VPU_CORE)
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return;
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pr_info("%s:\n", __func__);
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d = vpu_dmp_get(c);
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if (!d)
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return;
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kfree(d);
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vpu_dmp_set(c, NULL);
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}
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static void vpu_dmp_iova(void *dst, struct vpu_iova *i, size_t size)
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{
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unsigned long base = vpu_bin_base();
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if (!dst || !size || !base)
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return;
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size = min_t(size_t, size, i->size);
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if (i->bin == VPU_MEM_ALLOC) {
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if (!i->va)
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return;
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memcpy(dst, (void *)i->va, size);
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} else if (i->size) {
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if (!base)
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return;
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memcpy(dst, (void *)(base + i->bin), size);
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}
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}
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static inline
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unsigned long vpu_reg_base(int c)
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{
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return vpu_ctl_base(c) + CTRL_BASE_OFFSET;
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}
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static inline
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uint32_t vpu_reg_read(int c, int offset)
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{
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return ioread32((void *) (vpu_reg_base(c) + offset));
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}
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static void
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vpu_dmp_reg(int c, uint32_t *r, int offset, int max)
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{
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int i;
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for (i = 0; i < max; i++)
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r[i] = vpu_reg_read(c, offset + (i * 4));
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}
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static void vpu_dmp_reg_file(int c)
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{
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struct vpu_dmp *d = vpu_dmp_get(c);
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if (!d)
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return;
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#define dmp_reg(r) \
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{ d->r_##r = vpu_reg_read(c, r); }
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dmp_reg(CG_CON);
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dmp_reg(SW_RST);
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dmp_reg(DONE_ST);
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dmp_reg(CTRL);
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#undef dmp_reg
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vpu_dmp_reg(c, d->r_info, XTENSA_INFO00, VPU_DMP_REG_CNT_INFO);
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vpu_dmp_reg(c, d->r_dbg, DEBUG_INFO00, VPU_DMP_REG_CNT_DBG);
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}
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static void
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vpu_dmp_ctrl(void *dst, int c, unsigned long offset, size_t size)
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{
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unsigned long base = vpu_get_ctrl_base(c);
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if (!base)
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return;
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memcpy_fromio(dst, (void *)(base + offset), size);
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}
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static void
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vpu_dmp_io(void *dst, unsigned long base, size_t size)
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{
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if (!base)
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return;
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memcpy_fromio(dst, (void *)(base), size);
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}
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static bool vpu_dmp_is_alive(int c)
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{
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struct vpu_dmp *d;
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uint32_t pc;
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int i;
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d = vpu_dmp_get(c);
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if (!d)
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return false;
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pc = d->r_dbg[5];
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pr_info("%s: vpu%d: debug info05: %x\n", __func__, c, pc);
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if (!pc)
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return false;
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for (i = 0; i < VPU_DMP_REG_CNT_INFO; i++) {
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if (d->r_info[i])
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return true;
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}
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pr_info("%s: all info registers are zeros\n", __func__);
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return false;
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}
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/**
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* vpu_dmp_create_locked() - Create VPU register and memory dump
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* @vd: vpu device
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* @req: on-going vpu request, set NULL if not available
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*
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* vd->lock must be locked before calling this function
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*/
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struct vpu_dmp_cfg {
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unsigned long reg;
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unsigned long dmem;
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unsigned long imem;
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struct vpu_iova iova_reset;
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struct vpu_iova iova_main;
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struct vpu_iova iova_kernel;
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struct vpu_iova iova_iram;
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struct vpu_iova iova_work;
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};
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static struct vpu_dmp_cfg vdc[2] = {
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{
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.reg = CTRL_BASE_OFFSET,
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.dmem = 0x0,
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.imem = 0x40000,
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.iova_reset = {0x7da00000, 0x100000, 0x0, 0x0, 0x0},
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.iova_main = {0x7db00000, 0x300000, 0x100000, 0x0, 0x0},
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.iova_kernel = {0x7de00000, 0x500000, VPU_MEM_ALLOC, 0x0, 0x0},
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.iova_iram = {0x0, 0x30000, 0x2950000, 0x0, 0x0},
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.iova_work = {0x0, 0x12000, VPU_MEM_ALLOC, 0x0, 0x0},
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},
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{
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.reg = CTRL_BASE_OFFSET,
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.dmem = 0x0,
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.imem = 0x40000,
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.iova_reset = {0x7e300000, 0x100000, 0x400000, 0x0, 0x0},
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.iova_main = {0x7e400000, 0x300000, 0x500000, 0x0, 0x0},
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.iova_kernel = {0x7e700000, 0x500000, VPU_MEM_ALLOC, 0x0, 0x0},
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.iova_iram = {0x0, 0x30000, 0x2980000, 0x0, 0x0},
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.iova_work = {0x0, 0x12000, VPU_MEM_ALLOC, 0x0, 0x0},
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}
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};
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int vpu_dmp_create_locked(int c, struct vpu_request *req,
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const char *fmt, ...)
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{
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struct vpu_dmp *d;
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int ret = 0;
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va_list args;
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pr_info("%s: vpu%d\n", __func__, c);
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if (c < 0 || c >= MTK_VPU_CORE) {
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pr_info("%s: vpu%d: %d\n", __func__, c, MTK_VPU_CORE);
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ret = -EINVAL;
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goto out;
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}
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ret = vpu_dmp_alloc(c);
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if (ret) {
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pr_info("%s: vpu%d: vpu_dmp_alloc: %d\n", __func__, c, ret);
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goto out;
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}
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d = vpu_dmp_get(c);
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if (!d) {
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pr_info("%s: vpu%d: vpu_dmp_get: %d\n", __func__, c, d);
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goto out;
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}
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d->time = sched_clock();
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va_start(args, fmt);
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ret = vsnprintf(d->info, VPU_DMP_INFO_SZ, fmt, args);
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va_end(args);
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if (ret < 0)
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pr_info("%s: vsnprintf: %d\n", __func__, ret);
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#define VPU_DMP_STATE(a) \
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pr_info("%s: vpu%d: %s done. pc: 0x%x\n", \
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__func__, c, #a, vpu_reg_read(c, DEBUG_INFO05))
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#define VPU_DMP_IO(a) do { \
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vpu_dmp_io(d->m_##a, m_##a, VPU_DMP_SZ); \
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VPU_DMP_STATE(#a); \
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} while (0)
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VPU_DMP_IO(infra_cfg);
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VPU_DMP_IO(sleep);
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VPU_DMP_IO(gals);
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VPU_DMP_IO(smi_cmn0);
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VPU_DMP_IO(smi_cmn1);
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dump_emi_outstanding();
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VPU_DMP_STATE("emi");
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VPU_DMP_IO(ipu_conn);
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VPU_DMP_IO(ipu_vcore);
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#undef VPU_DMP_IO
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m4u_dump_reg_for_vpu_hang_issue();
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VPU_DMP_STATE("m4u");
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vpu_dmp_reg_file(c);
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VPU_DMP_STATE("vpu ctrl (partial)");
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if (req)
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memcpy(&d->req, req, sizeof(struct vpu_request));
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if (!vpu_dmp_is_alive(c))
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goto out;
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#define VPU_DMP_CTRL(a, A) do { \
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vpu_dmp_ctrl(d->m_##a, c, vdc[c].a, VPU_DMP_##A##_SZ); \
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VPU_DMP_STATE(#a); \
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} while (0)
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VPU_DMP_CTRL(reg, REG);
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if (vpu_dmp_is_alive(c)) {
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VPU_DMP_CTRL(dmem, DMEM);
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VPU_DMP_CTRL(imem, IMEM);
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}
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#undef VPU_DMP_CTRL
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#define VPU_DMP_IOVA(a, A) do { \
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vpu_dmp_iova(d->m_##a, &vdc[c].iova_##a, VPU_DMP_##A##_SZ); \
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VPU_DMP_STATE(#a); \
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} while (0)
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VPU_DMP_IOVA(reset, RESET);
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VPU_DMP_IOVA(main, MAIN);
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VPU_DMP_IOVA(kernel, KERNEL);
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VPU_DMP_IOVA(iram, IRAM);
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VPU_DMP_IOVA(work, WORK);
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#undef VPU_DMP_IOVA
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#undef VPU_DMP_STATE
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out:
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return ret;
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}
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static void
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vpu_dmp_seq_bar(struct seq_file *s, int c, const char *str)
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{
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seq_printf(s, "======== vpu%d: %s ========\n", c, str);
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}
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static void
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vpu_dmp_seq_mem(struct seq_file *s, int c,
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uint32_t iova, const char *str, void *buf, size_t len)
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{
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seq_printf(s, "======== vpu%d: %s@0x%x ========\n", c, str, iova);
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seq_hex_dump(s, str, DUMP_PREFIX_OFFSET, 32, 4, buf, len, false);
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}
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static void
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vpu_dmp_seq_iova(struct seq_file *s, int c,
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struct vpu_iova *i, const char *str, void *buf, size_t len)
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{
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uint32_t iova;
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if (i->iova)
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iova = i->iova; /* dynamic alloc */
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else if (i->size)
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iova = i->addr;
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else
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return;
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vpu_dmp_seq_mem(s, c, iova, str, buf, len);
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}
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static void
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vpu_dmp_seq_ctrl(struct seq_file *s, int c,
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unsigned long addr, const char *str, void *buf, size_t len)
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{
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uint32_t base;
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if (c == 0)
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base = 0x19100000;
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else if (c == 1)
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base = 0x19200000;
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else
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return;
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vpu_dmp_seq_mem(s, c, base + addr, str, buf, len);
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}
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static void
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vpu_dmp_seq_reg(struct seq_file *s, int c)
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{
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struct vpu_dmp *d = vpu_dmp_get(c);
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int i;
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if (!d)
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return;
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#define seq_reg(r) \
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seq_printf(s, #r ":\t0x%08x\n", d->r_##r)
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seq_reg(CG_CON);
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seq_reg(SW_RST);
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seq_reg(DONE_ST);
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seq_reg(CTRL);
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#undef seq_reg
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for (i = 0; i < VPU_DMP_REG_CNT_INFO; i++)
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seq_printf(s, "XTENSA_INFO%02d:\t0x%08x\n", i, d->r_info[i]);
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for (i = 0; i < VPU_DMP_REG_CNT_DBG; i++)
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seq_printf(s, "DEBUG_INFO%02d:\t0x%08x\n", i, d->r_dbg[i]);
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}
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static void vpu_dmp_seq_req(struct seq_file *s, int c)
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{
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struct vpu_dmp *d = vpu_dmp_get(c);
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struct vpu_request *req;
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struct vpu_buffer *b;
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struct vpu_plane *p;
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int buf_cnt;
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int plane_cnt;
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int i, j;
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if (!d)
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return;
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req = &d->req;
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if (!req->user_id) {
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seq_puts(s, "N/A\n");
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return;
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}
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buf_cnt = min_t(int, VPU_MAX_NUM_PORTS, req->buffer_count);
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seq_printf(s,
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"sett_ptr: 0x%llx, sett_length: %d, buf_cnt: %d\n",
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req->sett.sett_ptr,
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req->sett.sett_lens,
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req->buffer_count);
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for (i = 0; i < buf_cnt; i++) {
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b = &req->buffers[i];
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seq_printf(s,
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"buf%d: port:%d, %dx%d, format:%d, plane_cnt: %d\n",
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i,
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b->port_id,
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b->width, b->height,
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b->format,
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b->plane_count);
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plane_cnt = min_t(int, 3, b->plane_count);
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for (j = 0; j < plane_cnt; j++) {
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p = &b->planes[j];
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seq_printf(s,
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"buf%d.plane%d: ptr:0x%llx, length:%d, stride:%d\n",
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i, j,
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p->ptr,
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p->length,
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p->stride);
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}
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}
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}
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void vpu_dmp_seq_core(struct seq_file *s, int c_s)
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{
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unsigned int c = (unsigned int)c_s;
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struct vpu_dmp *d = vpu_dmp_get(c);
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if (!d)
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return;
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vpu_dmp_seq_bar(s, c, "device info");
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seq_printf(s, "exception reason: %s\n", d->info);
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seq_puts(s, "exception time: [");
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vpu_dmp_seq_time(s, d->time);
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seq_puts(s, "]\n");
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vpu_dmp_seq_bar(s, c, "request info");
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vpu_dmp_seq_req(s, c);
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vpu_dmp_seq_bar(s, c, "message");
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vpu_dump_mesg_seq(s, c);
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vpu_dmp_seq_bar(s, c, "register");
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vpu_dmp_seq_reg(s, c);
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#define VPU_SEQ_IO(a, A) \
|
|
vpu_dmp_seq_mem(s, c, A, #a" ", d->m_##a, VPU_DMP_SZ)
|
|
|
|
VPU_SEQ_IO(infra_cfg, INFRA_CFG);
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|
VPU_SEQ_IO(sleep, SLEEP);
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|
VPU_SEQ_IO(gals, GALS);
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|
VPU_SEQ_IO(smi_cmn0, SMI_CMN0);
|
|
VPU_SEQ_IO(smi_cmn1, SMI_CMN1);
|
|
VPU_SEQ_IO(ipu_conn, IPU_CONN);
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|
VPU_SEQ_IO(ipu_vcore, IPU_VCORE);
|
|
#undef VPU_SEQ_IO
|
|
|
|
#define VPU_SEQ_IOVA(a, A) \
|
|
vpu_dmp_seq_iova(s, c, &vdc[c].iova_##a, #a" ", \
|
|
d->m_##a, VPU_DMP_##A##_SZ)
|
|
|
|
VPU_SEQ_IOVA(reset, RESET);
|
|
VPU_SEQ_IOVA(main, MAIN);
|
|
VPU_SEQ_IOVA(kernel, KERNEL);
|
|
VPU_SEQ_IOVA(iram, IRAM);
|
|
VPU_SEQ_IOVA(work, WORK);
|
|
#undef VPU_SEQ_IOVA
|
|
|
|
#define VPU_SEQ_CTRL(a, A) \
|
|
vpu_dmp_seq_ctrl(s, c, vdc[c].a, #a" ", \
|
|
d->m_##a, VPU_DMP_##A##_SZ)
|
|
|
|
VPU_SEQ_CTRL(reg, REG);
|
|
VPU_SEQ_CTRL(dmem, DMEM);
|
|
VPU_SEQ_CTRL(imem, IMEM);
|
|
#undef VPU_SEQ_CTRL
|
|
|
|
}
|
|
|
|
/**
|
|
* vpu_dmp_seq() - Show VPU dump of all cores
|
|
* @s: output seq file
|
|
*
|
|
* Called by vpu_debug_vpu_memory()
|
|
*/
|
|
void vpu_dmp_seq(struct seq_file *s)
|
|
{
|
|
int c;
|
|
|
|
for (c = 0; c < MTK_VPU_CORE; c++)
|
|
vpu_dmp_seq_core(s, c);
|
|
}
|
|
|
|
/**
|
|
* vpu_dmp_clear_all() - Free VPU dump of all cores
|
|
*/
|
|
void vpu_dmp_free_all(void)
|
|
{
|
|
int c;
|
|
|
|
for (c = 0; c < MTK_VPU_CORE; c++)
|
|
vpu_dmp_free(c);
|
|
}
|
|
|
|
static void vpu_dmp_init_iova(struct vpu_iova *i, struct vpu_shared_memory *s)
|
|
{
|
|
if (!s)
|
|
return;
|
|
|
|
i->va = s->va;
|
|
i->iova = s->pa;
|
|
}
|
|
|
|
static void vpu_dmp_init_map(int c)
|
|
{
|
|
if (c)
|
|
return;
|
|
|
|
#define MAPIO(a, A) do { \
|
|
m_##a = (unsigned long)ioremap_wc(A, 0x1000); \
|
|
if (!m_##a) \
|
|
pr_info("%s: unable to map %xh\n", __func__, A); \
|
|
} while (0)
|
|
|
|
MAPIO(infra_cfg, INFRA_CFG);
|
|
MAPIO(sleep, SLEEP);
|
|
MAPIO(gals, GALS);
|
|
MAPIO(smi_cmn0, SMI_CMN0);
|
|
MAPIO(smi_cmn1, SMI_CMN1);
|
|
#undef MAPIO
|
|
|
|
m_ipu_conn = vpu_syscfg_base();
|
|
m_ipu_vcore = vpu_vcore_base();
|
|
}
|
|
|
|
void vpu_dmp_init(int c)
|
|
{
|
|
if (c < 0 || c >= MTK_VPU_CORE)
|
|
return;
|
|
|
|
vpu_dmp_set(c, NULL);
|
|
vpu_dmp_init_map(c);
|
|
vpu_dmp_init_iova(&vdc[c].iova_kernel, vpu_get_kernel_lib(c));
|
|
vpu_dmp_init_iova(&vdc[c].iova_work, vpu_get_work_buf(c));
|
|
vdc[c].iova_iram.iova = vpu_get_iram_data(c);
|
|
}
|
|
|
|
void vpu_dmp_exit(int c)
|
|
{
|
|
if (c < 0 || c >= MTK_VPU_CORE)
|
|
return;
|
|
vpu_dmp_free_locked(c);
|
|
}
|
|
|