550 lines
21 KiB
C
550 lines
21 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MSDC_CUST_MT6739_H_
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#define _MSDC_CUST_MT6739_H_
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#include <dt-bindings/mmc/mt6739-msdc.h>
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#include <dt-bindings/clock/mt6739-clk.h>
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#include <mtk_spm_resource_req.h>
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/**************************************************************/
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/* Section 1: Device Tree */
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/**************************************************************/
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/* Names used for device tree lookup */
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#define DT_COMPATIBLE_NAME "mediatek,msdc"
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#define MSDC0_CLK_NAME "msdc0-clock"
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#define MSDC0_HCLK_NAME "msdc0-hclock"
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#define MSDC1_CLK_NAME "msdc1-clock"
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#define MSDC1_HCLK_NAME "msdc1-hclock"
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#define MSDC0_IOCFG_NAME "mediatek,io_cfg_lt"
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#define MSDC1_IOCFG_NAME "mediatek,io_cfg_lb"
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/**************************************************************/
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/* Section 2: Power */
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/**************************************************************/
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#define POWER_READY
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#ifdef POWER_READY
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#if !defined(FPGA_PLATFORM)
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#include <mt-plat/upmu_common.h>
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#define REG_VEMC_VOSEL_CAL PMIC_RG_VEMC_VOCAL_ADDR
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#define REG_VEMC_VOSEL PMIC_RG_VEMC_VOSEL_ADDR
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#define REG_VEMC_EN PMIC_RG_LDO_VEMC_EN_ADDR /* TBC */
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#define REG_VMC_VOSEL_CAL PMIC_RG_VMC_VOCAL_ADDR
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#define REG_VMC_VOSEL PMIC_RG_VMC_VOSEL_ADDR
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#define REG_VMC_EN PMIC_RG_LDO_VMC_EN_ADDR /* TBC */
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#define REG_VMCH_VOSEL_CAL PMIC_RG_VMCH_VOCAL_ADDR
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#define REG_VMCH_VOSEL PMIC_RG_VMCH_VOSEL_ADDR
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#define REG_VMCH_EN PMIC_RG_LDO_VMCH_EN_ADDR /* TBC */
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#define MASK_VEMC_VOSEL_CAL PMIC_RG_VEMC_VOCAL_MASK
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#define SHIFT_VEMC_VOSEL_CAL PMIC_RG_VEMC_VOCAL_SHIFT
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#define FIELD_VEMC_VOSEL_CAL (MASK_VEMC_VOSEL_CAL \
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<< SHIFT_VEMC_VOSEL_CAL)
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#define MASK_VEMC_VOSEL PMIC_RG_VEMC_VOSEL_MASK
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#define SHIFT_VEMC_VOSEL PMIC_RG_VEMC_VOSEL_SHIFT
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#define FIELD_VEMC_VOSEL (MASK_VEMC_VOSEL << SHIFT_VEMC_VOSEL)
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#define MASK_VEMC_EN PMIC_RG_LDO_VEMC_EN_MASK
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#define SHIFT_VEMC_EN PMIC_RG_LDO_VEMC_EN_SHIFT
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#define FIELD_VEMC_EN (MASK_VEMC_EN << SHIFT_VEMC_EN)
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#define MASK_VMC_VOSEL_CAL PMIC_RG_VMC_VOCAL_MASK
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#define SHIFT_VMC_VOSEL_CAL PMIC_RG_VMC_VOCAL_SHIFT
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#define FIELD_VMC_VOSEL_CAL (MASK_VMC_VOSEL_CAL \
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<< SHIFT_VMC_VOSEL_CAL)
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#define MASK_VMC_VOSEL PMIC_RG_VMC_VOSEL_MASK
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#define SHIFT_VMC_VOSEL PMIC_RG_VMC_VOSEL_SHIFT
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#define FIELD_VMC_VOSEL (MASK_VMC_VOSEL << SHIFT_VMC_VOSEL)
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#define MASK_VMC_EN PMIC_RG_LDO_VMC_EN_MASK
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#define SHIFT_VMC_EN PMIC_RG_LDO_VMC_EN_SHIFT
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#define FIELD_VMC_EN (MASK_VMC_EN << SHIFT_VMC_EN)
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#define MASK_VMCH_VOSEL_CAL PMIC_RG_VMCH_VOCAL_MASK
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#define SHIFT_VMCH_VOSEL_CAL PMIC_RG_VMCH_VOCAL_SHIFT
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#define FIELD_VMCH_VOSEL_CAL (MASK_VMCH_VOSEL_CAL \
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<< SHIFT_VMCH_VOSEL_CAL)
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#define MASK_VMCH_VOSEL PMIC_RG_VMCH_VOSEL_MASK
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#define SHIFT_VMCH_VOSEL PMIC_RG_VMCH_VOSEL_SHIFT
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#define FIELD_VMCH_VOSEL (MASK_VMCH_VOSEL << SHIFT_VMCH_VOSEL)
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#define MASK_VMCH_EN PMIC_RG_LDO_VMCH_EN_MASK
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#define SHIFT_VMCH_EN PMIC_RG_LDO_VMCH_EN_SHIFT
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#define FIELD_VMCH_EN (MASK_VMCH_EN << SHIFT_VMCH_EN)
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#define REG_VMCH_OC_RAW_STATUS PMIC_RG_INT_RAW_STATUS_VMCH_OC_ADDR
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#define MASK_VMCH_OC_RAW_STATUS PMIC_RG_INT_RAW_STATUS_VMCH_OC_MASK
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#define SHIFT_VMCH_OC_RAW_STATUS PMIC_RG_INT_RAW_STATUS_VMCH_OC_SHIFT
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#define FIELD_VMCH_OC_RAW_STATUS (MASK_VMCH_OC_RAW_STATUS << SHIFT_VMCH_OC_RAW_STATUS)
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#define REG_VMCH_OC_STATUS PMIC_RG_INT_STATUS_VMCH_OC_ADDR
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#define MASK_VMCH_OC_STATUS PMIC_RG_INT_STATUS_VMCH_OC_MASK
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#define SHIFT_VMCH_OC_STATUS PMIC_RG_INT_STATUS_VMCH_OC_SHIFT
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#define FIELD_VMCH_OC_STATUS (MASK_VMCH_OC_STATUS << SHIFT_VMCH_OC_STATUS)
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#define REG_VMCH_OC_EN PMIC_RG_INT_EN_VMCH_OC_ADDR
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#define MASK_VMCH_OC_EN PMIC_RG_INT_EN_VMCH_OC_MASK
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#define SHIFT_VMCH_OC_EN PMIC_RG_INT_EN_VMCH_OC_SHIFT
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#define FIELD_VMCH_OC_EN (MASK_VMCH_OC_EN << SHIFT_VMCH_OC_EN)
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#define REG_VMCH_OC_MASK PMIC_RG_INT_MASK_VMCH_OC_ADDR
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#define MASK_VMCH_OC_MASK PMIC_RG_INT_MASK_VMCH_OC_MASK
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#define SHIFT_VMCH_OC_MASK PMIC_RG_INT_MASK_VMCH_OC_SHIFT
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#define FIELD_VMCH_OC_MASK (MASK_VMCH_OC_MASK << SHIFT_VMCH_OC_MASK)
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#define VEMC_VOSEL_CAL_mV(cal) ((cal >= 0) ? ((cal)/10) : 0)
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#define VEMC_VOSEL_2V9 (0x2)
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#define VEMC_VOSEL_3V (0x3)
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#define VEMC_VOSEL_3V3 (0x5)
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#define VMC_VOSEL_CAL_mV(cal) ((cal >= 0) ? ((cal)/10) : 0)
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#define VMC_VOSEL_1V8 (0x4)
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#define VMC_VOSEL_2V9 (0xa)
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#define VMC_VOSEL_3V (0xb)
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#define VMC_VOSEL_3V3 (0xd)
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#define VMCH_VOSEL_CAL_mV(cal) ((cal >= 0) ? ((cal)/10) : 0)
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#define VMCH_VOSEL_2V9 (0x2)
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#define VMCH_VOSEL_3V (0x3)
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#define VMCH_VOSEL_3V3 (0x5)
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#define REG_VCORE_VOSEL 0x1522
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#define MASK_VCORE_VOSEL 0x7F
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#define SHIFT_VCORE_VOSEL 0
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#define VCORE_MIN_UV 518750
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#define VCORE_STEP_UV 6250
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#define REG_VIO18_VOCAL 0x1C4C
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#define MASK_VIO18_VOCAL 0xF
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#define SHIFT_VIO18_VOCAL 0
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#define VIO18_VOCAL_mV(cal) ((cal >= 0) ? ((cal)/10) : 0)
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#define VIO18_VOSEL_1V8 (0xc)
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/* Note: 6357 does not support 1.7V VIO18 */
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#endif
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#endif /* POWER_READY */
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#define SD_POWER_DEFAULT_ON (0)
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#define EMMC_VOL_ACTUAL VOL_3000
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#define SD_VOL_ACTUAL VOL_3000
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#define SD1V8_VOL_ACTUAL VOL_1860
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/**************************************************************/
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/* Section 3: Clock */
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/**************************************************************/
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#if !defined(FPGA_PLATFORM)
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/* MSDCPLL register offset */
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#define MSDCPLL_CON0_OFFSET (0x250)
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#define MSDCPLL_CON1_OFFSET (0x254)
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#define MSDCPLL_CON2_OFFSET (0x258)
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#define MSDCPLL_PWR_CON0_OFFSET (0x25c)
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#endif
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#define MSDCPLL_FREQ 400000000
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#define MSDC0_SRC_0 260000
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#define MSDC0_SRC_1 MSDCPLL_FREQ
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#define MSDC0_SRC_2 182000000
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#define MSDC0_SRC_3 78000000
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#define MSDC0_SRC_4 312000000
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#define MSDC0_SRC_5 273000000
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#define MSDC0_SRC_6 249600000
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#define MSDC0_SRC_7 156000000
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#define MSDC1_SRC_0 260000
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#define MSDC1_SRC_1 (MSDCPLL_FREQ/2)
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#define MSDC1_SRC_2 208000000
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#define MSDC1_SRC_3 182000000
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#define MSDC1_SRC_4 136500000
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#define MSDC1_SRC_5 156000000
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#define MSDC1_SRC_6 48000000
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#define MSDC1_SRC_7 91000000
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#define MSDC_SRC_FPGA 12000000
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/* FIX ME */
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#define CLOCK_READY
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#ifdef CLOCK_READY
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#define MSDC0_CG_NAME MTK_CG_PERI2_RG_MSDC0_CK_PDN_AP_NORM_STA
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#define MSDC1_CG_NAME MTK_CG_PERI2_RG_MSDC1_CK_PDN_STA
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#endif
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/**************************************************************/
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/* Section 4: GPIO and Pad */
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/**************************************************************/
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/*--------------------------------------------------------------------------*/
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/* MSDC0~1 GPIO and IO Pad Configuration Base */
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/*--------------------------------------------------------------------------*/
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#define MSDC_GPIO_BASE gpio_base /* 0x10005000 */
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#define MSDC0_IO_CFG_BASE (msdc_io_cfg_bases[0]) /* 0x10002000 */
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#define MSDC1_IO_CFG_BASE (msdc_io_cfg_bases[1]) /* 0x10002400 */
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/*--------------------------------------------------------------------------*/
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/* MSDC GPIO Related Register */
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/*--------------------------------------------------------------------------*/
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/* MSDC0 */
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#define MSDC0_GPIO_MODE4 (MSDC_GPIO_BASE + 0x340)
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#define MSDC0_GPIO_MODE5 (MSDC_GPIO_BASE + 0x350)
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#define MSDC0_GPIO_MODE6 (MSDC_GPIO_BASE + 0x360)
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#define MSDC0_GPIO_DRV0_ADDR (MSDC0_IO_CFG_BASE + 0x0)
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#define MSDC0_GPIO_DRV1_ADDR (MSDC0_IO_CFG_BASE + 0x10)
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#define MSDC0_GPIO_IES_ADDR (MSDC0_IO_CFG_BASE + 0x30)
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#define MSDC0_GPIO_PUPD_ADDR (MSDC0_IO_CFG_BASE + 0x40)
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#define MSDC0_GPIO_R0_ADDR (MSDC0_IO_CFG_BASE + 0x50)
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#define MSDC0_GPIO_R1_ADDR (MSDC0_IO_CFG_BASE + 0x60)
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#define MSDC0_GPIO_RDSEL0_ADDR (MSDC0_IO_CFG_BASE + 0x70)
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#define MSDC0_GPIO_RDSEL1_ADDR (MSDC0_IO_CFG_BASE + 0x80)
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#define MSDC0_GPIO_SMT_ADDR (MSDC0_IO_CFG_BASE + 0x90)
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#define MSDC0_GPIO_SR_ADDR (MSDC1_IO_CFG_BASE + 0xA0)
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#define MSDC0_GPIO_TDSEL_ADDR (MSDC0_IO_CFG_BASE + 0xB0)
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/* MSDC1 */
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#define MSDC1_GPIO_MODE8 (MSDC_GPIO_BASE + 0x380)
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#define MSDC1_GPIO_MODE9 (MSDC_GPIO_BASE + 0x390)
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#define MSDC1_GPIO_DRV_ADDR (MSDC1_IO_CFG_BASE + 0x0)
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#define MSDC1_GPIO_IES_ADDR (MSDC1_IO_CFG_BASE + 0x20)
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#define MSDC1_GPIO_PUPD_ADDR (MSDC1_IO_CFG_BASE + 0x30)
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#define MSDC1_GPIO_R0_ADDR (MSDC1_IO_CFG_BASE + 0x50)
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#define MSDC1_GPIO_R1_ADDR (MSDC1_IO_CFG_BASE + 0x60)
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#define MSDC1_GPIO_RDSEL_ADDR (MSDC1_IO_CFG_BASE + 0x70)
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#define MSDC1_GPIO_SMT_ADDR (MSDC1_IO_CFG_BASE + 0x90)
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#define MSDC1_GPIO_SR_ADDR (MSDC1_IO_CFG_BASE + 0xA0)
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#define MSDC1_GPIO_TDSEL_ADDR (MSDC1_IO_CFG_BASE + 0xB0)
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/*
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* MSDC0 GPIO and PAD register and bitfields definition
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*/
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/* MSDC0_GPIO_MODE4, 001b is msdc mode */
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#define MSDC0_MODE_CMD_MASK (0x7 << 24)
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#define MSDC0_MODE_DSL_MASK (0x7 << 28)
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/* MSDC0_GPIO_MODE5, 001b is msdc mode*/
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#define MSDC0_MODE_CLK_MASK (0x7 << 0)
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#define MSDC0_MODE_DAT0_MASK (0x7 << 4)
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#define MSDC0_MODE_DAT1_MASK (0x7 << 8)
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#define MSDC0_MODE_DAT2_MASK (0x7 << 12)
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#define MSDC0_MODE_DAT3_MASK (0x7 << 16)
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#define MSDC0_MODE_DAT4_MASK (0x7 << 20)
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#define MSDC0_MODE_DAT5_MASK (0x7 << 24)
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#define MSDC0_MODE_DAT6_MASK (0x7 << 28)
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/* MSDC0_GPIO_MODE6, 001b is msdc mode */
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#define MSDC0_MODE_DAT7_MASK (0x7 << 0)
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#define MSDC0_MODE_RSTB_MASK (0x7 << 4)
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/* MSDC0 IES mask*/
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#define MSDC0_IES_CLK_MASK (0x1 << 6)
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#define MSDC0_IES_CMD_MASK (0x1 << 7)
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#define MSDC0_IES_DAT_MASK (0xff << 8)
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#define MSDC0_IES_DAT0_MASK (0x1 << 8)
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#define MSDC0_IES_DAT1_MASK (0x1 << 9)
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#define MSDC0_IES_DAT2_MASK (0x1 << 10)
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#define MSDC0_IES_DAT3_MASK (0x1 << 11)
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#define MSDC0_IES_DAT4_MASK (0x1 << 12)
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#define MSDC0_IES_DAT5_MASK (0x1 << 13)
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#define MSDC0_IES_DAT6_MASK (0x1 << 14)
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#define MSDC0_IES_DAT7_MASK (0x1 << 15)
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#define MSDC0_IES_DSL_MASK (0x1 << 16)
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#define MSDC0_IES_RSTB_MASK (0x1 << 17)
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#define MSDC0_IES_ALL_MASK (0xfff << 6)
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/* MSDC0 SMT mask*/
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#define MSDC0_SMT_CLK_MASK (0x1 << 1)
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#define MSDC0_SMT_CMD_MASK (0x1 << 2)
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#define MSDC0_SMT_DAT_MASK (0x1 << 3)
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#define MSDC0_SMT_DSL_MASK (0x1 << 4)
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#define MSDC0_SMT_RSTB_MASK (0x1 << 5)
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#define MSDC0_SMT_ALL_MASK (0x1f << 1)
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/* MSDC0 TDSEL mask*/
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#define MSDC0_TDSEL_CLK_MASK (0xf << 4)
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#define MSDC0_TDSEL_CMD_MASK (0xf << 8)
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#define MSDC0_TDSEL_DAT_MASK (0xf << 12)
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#define MSDC0_TDSEL_DSL_MASK (0xf << 16)
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#define MSDC0_TDSEL_RSTB_MASK (0xf << 20)
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#define MSDC0_TDSEL_ALL_MASK (0xfffff << 4)
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/* MSDC0 RDSEL mask*/
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#define MSDC0_RDSEL_CLK_MASK (0x3f << 6)
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#define MSDC0_RDSEL_CMD_MASK (0x3f << 12)
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#define MSDC0_RDSEL_DAT_MASK (0x3f << 18)
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#define MSDC0_RDSEL_DSL_MASK (0x3f << 24)
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#define MSDC0_RDSEL0_ALL_MASK (0xffffff << 6)
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#define MSDC0_RDSEL_RSTB_MASK (0x3f << 0)
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#define MSDC0_RDSEL1_ALL_MASK (0x3f << 0)
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/* MSDC0 SR mask*/
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#define MSDC0_SR_CLK_MASK (0x1 << 6)
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#define MSDC0_SR_CMD_MASK (0x1 << 7)
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#define MSDC0_SR_DAT_MASK (0xff << 8)
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#define MSDC0_SR_DAT0_MASK (0x1 << 8)
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#define MSDC0_SR_DAT1_MASK (0x1 << 9)
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#define MSDC0_SR_DAT2_MASK (0x1 << 10)
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#define MSDC0_SR_DAT3_MASK (0x1 << 11)
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#define MSDC0_SR_DAT4_MASK (0x1 << 12)
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#define MSDC0_SR_DAT5_MASK (0x1 << 13)
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#define MSDC0_SR_DAT6_MASK (0x1 << 14)
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#define MSDC0_SR_DAT7_MASK (0x1 << 15)
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#define MSDC0_SR_DSL_MASK (0x1 << 16)
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#define MSDC0_SR_RSTB_MASK (0x1 << 17)
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#define MSDC0_SR_ALL_MASK (0xfff << 6)
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/* MSDC0 DRV mask*/
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#define MSDC0_DRV_CMD_MASK (0x7 << 18)
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#define MSDC0_DRV_CLK_MASK (0x7 << 21)
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#define MSDC0_DRV_DAT0_MASK (0x7 << 24)
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#define MSDC0_DRV_DAT1_MASK (0x7 << 27)
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#define MSDC0_DRV0_ALL_MASK (0xfff << 18)
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#define MSDC0_DRV_DAT2_MASK (0x7 << 0)
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#define MSDC0_DRV_DAT3_MASK (0x7 << 3)
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#define MSDC0_DRV_DAT4_MASK (0x7 << 6)
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#define MSDC0_DRV_DAT5_MASK (0x7 << 9)
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#define MSDC0_DRV_DAT6_MASK (0x7 << 12)
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#define MSDC0_DRV_DAT7_MASK (0x7 << 15)
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#define MSDC0_DRV_DSL_MASK (0x7 << 18)
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#define MSDC0_DRV_RSTB_MASK (0x7 << 21)
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#define MSDC0_DRV1_ALL_MASK (0xffffff << 0)
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/* MSDC0 PUPD mask */
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#define MSDC0_PUPD_CLK_MASK (0x1 << 6)
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#define MSDC0_PUPD_CMD_MASK (0x1 << 7)
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#define MSDC0_PUPD_DAT_MASK (0xff << 8)
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#define MSDC0_PUPD_DAT0_MASK (0x1 << 8)
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#define MSDC0_PUPD_DAT1_MASK (0x1 << 9)
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#define MSDC0_PUPD_DAT2_MASK (0x1 << 10)
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#define MSDC0_PUPD_DAT3_MASK (0x1 << 11)
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#define MSDC0_PUPD_DAT4_MASK (0x1 << 12)
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#define MSDC0_PUPD_DAT5_MASK (0x1 << 13)
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#define MSDC0_PUPD_DAT6_MASK (0x1 << 14)
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#define MSDC0_PUPD_DAT7_MASK (0x1 << 15)
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#define MSDC0_PUPD_DSL_MASK (0x7 << 16)
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#define MSDC0_PUPD_RSTB_MASK (0x7 << 17)
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#define MSDC0_PUPD_MASK_WITH_RSTB (0xFFF << 6)
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#define MSDC0_PUPD_ALL_MASK (0x7FF << 6)
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/* MSDC0 R0 mask */
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#define MSDC0_R0_CLK_MASK (0x1 << 6)
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#define MSDC0_R0_CMD_MASK (0x1 << 7)
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#define MSDC0_R0_DAT_MASK (0xff << 8)
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#define MSDC0_R0_DAT0_MASK (0x1 << 8)
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#define MSDC0_R0_DAT1_MASK (0x1 << 9)
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#define MSDC0_R0_DAT2_MASK (0x1 << 10)
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#define MSDC0_R0_DAT3_MASK (0x1 << 11)
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#define MSDC0_R0_DAT4_MASK (0x1 << 12)
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#define MSDC0_R0_DAT5_MASK (0x1 << 13)
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#define MSDC0_R0_DAT6_MASK (0x1 << 14)
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#define MSDC0_R0_DAT7_MASK (0x1 << 15)
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#define MSDC0_R0_DSL_MASK (0x7 << 16)
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#define MSDC0_R0_RSTB_MASK (0x7 << 17)
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#define MSDC0_R0_MASK_WITH_RSTB (0xFFF << 6)
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#define MSDC0_R0_ALL_MASK (0x7FF << 6)
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/* MSDC0 R1 mask */
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#define MSDC0_R1_CLK_MASK (0x1 << 6)
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#define MSDC0_R1_CMD_MASK (0x1 << 7)
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#define MSDC0_R1_DAT_MASK (0xff << 8)
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#define MSDC0_R1_DAT0_MASK (0x1 << 8)
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#define MSDC0_R1_DAT1_MASK (0x1 << 9)
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#define MSDC0_R1_DAT2_MASK (0x1 << 10)
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#define MSDC0_R1_DAT3_MASK (0x1 << 11)
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#define MSDC0_R1_DAT4_MASK (0x1 << 12)
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#define MSDC0_R1_DAT5_MASK (0x1 << 13)
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#define MSDC0_R1_DAT6_MASK (0x1 << 14)
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#define MSDC0_R1_DAT7_MASK (0x1 << 15)
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#define MSDC0_R1_DSL_MASK (0x7 << 16)
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#define MSDC0_R1_RSTB_MASK (0x7 << 17)
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#define MSDC0_R1_MASK_WITH_RSTB (0xFFF << 6)
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#define MSDC0_R1_ALL_MASK (0x7FF << 6)
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/*
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* MSDC1 GPIO and PAD register and bitfields definition
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*/
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/* MSDC1_GPIO_MODE8, 0001b is msdc mode */
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#define MSDC1_MODE_CMD_MASK (0x7 << 28)
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/* MSDC1_GPIO_MODE9, 0001b is msdc mode */
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#define MSDC1_MODE_CLK_MASK (0x7 << 0)
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#define MSDC1_MODE_DAT0_MASK (0x7 << 4)
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#define MSDC1_MODE_DAT1_MASK (0x7 << 8)
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#define MSDC1_MODE_DAT2_MASK (0x7 << 12)
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#define MSDC1_MODE_DAT3_MASK (0x7 << 16)
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/* MSDC1 IES mask*/
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#define MSDC1_IES_CLK_MASK (0x1 << 2)
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#define MSDC1_IES_CMD_MASK (0x1 << 3)
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#define MSDC1_IES_DAT_MASK (0xf << 4)
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#define MSDC1_IES_DAT0_MASK (0x1 << 4)
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#define MSDC1_IES_DAT1_MASK (0x1 << 5)
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#define MSDC1_IES_DAT2_MASK (0x1 << 6)
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#define MSDC1_IES_DAT3_MASK (0x1 << 7)
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#define MSDC1_IES_ALL_MASK (0x3f << 2)
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/* MSDC1 SMT mask*/
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#define MSDC1_SMT_CLK_MASK (0x1 << 1)
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#define MSDC1_SMT_CMD_MASK (0x1 << 2)
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#define MSDC1_SMT_DAT_MASK (0x1 << 3)
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#define MSDC1_SMT_ALL_MASK (0x7 << 1)
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/* MSDC1 TDSEL mask*/
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#define MSDC1_TDSEL_DAT_MASK (0xf << 4)
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#define MSDC1_TDSEL_CMD_MASK (0xf << 8)
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#define MSDC1_TDSEL_CLK_MASK (0xf << 12)
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#define MSDC1_TDSEL_ALL_MASK (0xfff << 4)
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/* MSDC1 RDSEL mask*/
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#define MSDC1_RDSEL_CLK_MASK (0x3f << 6)
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#define MSDC1_RDSEL_CMD_MASK (0x3f << 12)
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#define MSDC1_RDSEL_DAT_MASK (0x3f << 18)
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#define MSDC1_RDSEL_ALL_MASK (0x3ffff << 6)
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/* MSDC1 SR mask*/
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#define MSDC1_SR_CLK_MASK (0x1 << 2)
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#define MSDC1_SR_CMD_MASK (0x1 << 3)
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#define MSDC1_SR_DAT_MASK (0x1 << 4)
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#define MSDC1_SR_DAT0_MASK (0x1 << 4)
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#define MSDC1_SR_DAT1_MASK (0x1 << 5)
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#define MSDC1_SR_DAT2_MASK (0x1 << 6)
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#define MSDC1_SR_DAT3_MASK (0x1 << 7)
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#define MSDC1_SR_ALL_MASK (0x3f << 2)
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/* MSDC1 DRV mask*/
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#define MSDC1_DRV_CLK_MASK (0x7 << 3)
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#define MSDC1_DRV_CMD_MASK (0x7 << 6)
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#define MSDC1_DRV_DAT_MASK (0x7 << 9)
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#define MSDC1_DRV_ALL_MASK (0x1ff << 3)
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/* MSDC1 PUPD mask */
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#define MSDC1_PUPD_CLK_MASK (0x7 << 2)
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#define MSDC1_PUPD_CMD_MASK (0x7 << 3)
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#define MSDC1_PUPD_DAT0_MASK (0x7 << 4)
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#define MSDC1_PUPD_DAT1_MASK (0x7 << 5)
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#define MSDC1_PUPD_DAT2_MASK (0x7 << 6)
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#define MSDC1_PUPD_DAT3_MASK (0x7 << 7)
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#define MSDC1_PUPD_ALL_MASK (0x3F << 2)
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/* MSDC1 R0 mask */
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#define MSDC1_R0_CLK_MASK (0x7 << 2)
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#define MSDC1_R0_CMD_MASK (0x7 << 3)
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#define MSDC1_R0_DAT0_MASK (0x7 << 4)
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#define MSDC1_R0_DAT1_MASK (0x7 << 5)
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#define MSDC1_R0_DAT2_MASK (0x7 << 6)
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#define MSDC1_R0_DAT3_MASK (0x7 << 7)
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#define MSDC1_R0_ALL_MASK (0x3F << 2)
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/* MSDC1 R1 mask */
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#define MSDC1_R1_CLK_MASK (0x7 << 2)
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#define MSDC1_R1_CMD_MASK (0x7 << 3)
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#define MSDC1_R1_DAT0_MASK (0x7 << 4)
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#define MSDC1_R1_DAT1_MASK (0x7 << 5)
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#define MSDC1_R1_DAT2_MASK (0x7 << 6)
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#define MSDC1_R1_DAT3_MASK (0x7 << 7)
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#define MSDC1_R1_ALL_MASK (0x3F << 2)
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/* FOR msdc_io_check() */
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#define MSDC1_PUPD_DAT0_ADDR (MSDC1_GPIO_PUPD_ADDR)
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#define MSDC1_PUPD_DAT1_ADDR (MSDC1_GPIO_PUPD_ADDR)
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#define MSDC1_PUPD_DAT2_ADDR (MSDC1_GPIO_PUPD_ADDR)
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/**************************************************************/
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/* Section 5: Adjustable Driver Parameter */
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/**************************************************************/
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#define HOST_MAX_BLKSZ (2048)
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#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
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/* data timeout counter. 1048576 * 3 sclk. */
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#define DEFAULT_DTOC (3)
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#define MAX_DMA_CNT (4 * 1024 * 1024)
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/* a WIFI transaction may be 50K */
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#define MAX_DMA_CNT_SDIO (0xFFFFFFFF - 255)
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/* a LTE transaction may be 128K */
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#define MAX_HW_SGMTS (MAX_BD_NUM)
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#define MAX_PHY_SGMTS (MAX_BD_NUM)
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#define MAX_SGMT_SZ (MAX_DMA_CNT)
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#define MAX_SGMT_SZ_SDIO (MAX_DMA_CNT_SDIO)
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#define HOST_MAX_NUM (2)
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#ifdef CONFIG_PWR_LOSS_MTK_TEST
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#define MAX_REQ_SZ (512 * 65536)
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#else
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#define MAX_REQ_SZ (512 * 1024)
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#endif
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#ifdef FPGA_PLATFORM
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#define HOST_MAX_MCLK (200000000)
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#else
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#define HOST_MAX_MCLK (200000000)
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#endif
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#define HOST_MIN_MCLK (260000)
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/* SD card, bad card handling settings */
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/* if continuous data timeout reach the limit */
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/* driver will force remove card */
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#define MSDC_MAX_DATA_TIMEOUT_CONTINUOUS (100)
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/* if continuous power cycle fail reach the limit */
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/* driver will force remove card */
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#define MSDC_MAX_POWER_CYCLE_FAIL_CONTINUOUS (3)
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/* sdcard esd recovery */
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/* power reset sdcard when sdcard hang from esd */
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#define SDCARD_ESD_RECOVERY
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/* #define MSDC_HQA */
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/* #define SDIO_HQA */
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/**************************************************************/
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/* Section 6: BBChip-depenent Tunnig Parameter */
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/**************************************************************/
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#define EMMC_MAX_FREQ_DIV 4 /* lower frequence to 12.5M */
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#define MSDC_CLKTXDLY 0
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#define MSDC0_DDR50_DDRCKD 1 /* FIX ME: may be removed */
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#define VOL_CHG_CNT_DEFAULT_VAL 0x1F4 /* =500 */
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#define MSDC_PB0_DEFAULT_VAL 0x403C0007
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#define MSDC_PB1_DEFAULT_VAL 0xFFE60349
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#define MSDC_PB2_DEFAULT_RESPWAITCNT 0x3
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#define MSDC_PB2_DEFAULT_RESPSTENSEL 0x1
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#define MSDC_PB2_DEFAULT_CRCSTSENSEL 0x1
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#if defined(FPGA_PLATFORM)
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#undef MSDC_PB2_DEFAULT_CRCSTSENSEL
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#define MSDC_PB2_DEFAULT_CRCSTSENSEL 0
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#endif
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#define EMMC50_CFG_END_BIT_CHK_CNT 0x3
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/**************************************************************/
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/* Section 7: SDIO host */
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/**************************************************************/
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#ifdef CONFIG_MTK_COMBO_COMM
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#include <mt-plat/mtk_wcn_cmb_stub.h>
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#define CFG_DEV_SDIO 3
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#endif
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/**************************************************************/
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/* Section 8: ECO Variation */
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/**************************************************************/
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#if !defined(FPGA_PLATFORM)
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#include <mt-plat/mtk_chip.h>
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#else
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#define mt_get_chip_hw_ver() 0
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/* #define CHIP_SW_VER_01 0 */
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#endif
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/* FIXME: check if the following lines are used on MT6739 */
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#define ENABLE_HW_DVFS_WITH_CLK_OFF() \
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MSDC_SET_BIT32(MSDC_CFG, MSDC_CFG_DVFS_IDLE)
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#define DISABLE_HW_DVFS_WITH_CLK_OFF() \
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MSDC_CLR_BIT32(MSDC_CFG, MSDC_CFG_DVFS_IDLE)
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#define ENABLE_SDC_RX_ENH() \
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MSDC_SET_BIT32(SDC_ADV_CFG0, SDC_ADV_CFG0_SDC_RX_ENH_EN)
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#define DISABLE_SDC_RX_ENH() \
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MSDC_CLR_BIT32(SDC_ADV_CFG0, SDC_ADV_CFG0_SDC_RX_ENH_EN)
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#define SET_EMMC50_CFG_END_BIT_CHK_CNT(CNT) \
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MSDC_SET_FIELD(EMMC50_CFG0, MSDC_EMMC50_CFG_END_BIT_CHK_CNT, CNT)
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#endif /* _MSDC_CUST_MT6739_H_ */
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