209 lines
7.2 KiB
C
209 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MSDC_CUST_MT6765_H_
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#define _MSDC_CUST_MT6765_H_
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#ifdef CONFIG_FPGA_EARLY_PORTING
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#define FPGA_PLATFORM
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#else
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/* #define MTK_MSDC_BRINGUP_DEBUG */
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#endif
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#if defined(CONFIG_MACH_MT6765)
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#include <dt-bindings/mmc/mt6765-msdc.h>
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#else
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#include <dt-bindings/mmc/mt6761-msdc.h>
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#endif
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/* #define CONFIG_MTK_MSDC_BRING_UP_BYPASS */
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#if !defined(FPGA_PLATFORM)
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#if defined(CONFIG_MACH_MT6765)
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#include <dt-bindings/clock/mt6765-clk.h>
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#else
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#include <dt-bindings/clock/mt6761-clk.h>
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#endif
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#endif
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#ifndef CONFIG_MTK_MSDC_BRING_UP_BYPASS
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//#include <mtk_spm_resource_req.h>
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#endif
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/**************************************************************/
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/* Section 1: Device Tree */
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/**************************************************************/
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/* Names used for device tree lookup */
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#define DT_COMPATIBLE_NAME "mediatek,msdc"
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#define MSDC0_CLK_NAME "msdc0-clock"
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#if defined(CONFIG_MTK_HW_FDE) || defined(CONFIG_MMC_CRYPTO)
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#define MSDC0_AES_CLK_NAME "msdc0-aes-clock"
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#endif
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#define MSDC0_HCLK_NAME "msdc0-hclock"
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#define MSDC1_CLK_NAME "msdc1-clock"
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#define MSDC1_HCLK_NAME "msdc1-hclock"
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#define MSDC3_CLK_NAME "msdc3-clock"
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#define MSDC3_HCLK_NAME "msdc3-hclock"
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#define MSDC0_IOCFG_NAME "mediatek,io_cfg_lt"
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#define MSDC1_IOCFG_NAME "mediatek,io_cfg_lb"
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/**************************************************************/
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/* Section 2: Power */
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/**************************************************************/
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#define SD_POWER_DEFAULT_ON (0)
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#include <mt-plat/upmu_common.h>
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#define EMMC_VOL_ACTUAL VOL_3000
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#define SD_VOL_ACTUAL VOL_3000
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/**************************************************************/
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/* Section 3: Clock */
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/**************************************************************/
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#define MSDCPLL_FREQ 800000000
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/* list the other value by clock owners' clock table doc if needed */
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#define MSDC0_SRC_0 260000
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#define MSDC0_SRC_1 (MSDCPLL_FREQ/2)
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#define MSDC1_SRC_0 260000
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#define MSDC1_SRC_1 208000000
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#define MSDC1_SRC_2 (MSDCPLL_FREQ/4)
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#define MSDC3_SRC_0 260000
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#define MSDC3_SRC_1 208000000
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#define MSDC3_SRC_2 (MSDCPLL_FREQ/2)
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#define MSDC3_SRC_3 156000000
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#define MSDC3_SRC_4 182000000
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#define MSDC3_SRC_5 312000000
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#define MSDC3_SRC_6 364000000
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#define MSDC3_SRC_7 (MSDCPLL_FREQ/4)
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#define MSDC_SRC_FPGA 12000000
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/**************************************************************/
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/* Section 4: GPIO and Pad */
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/**************************************************************/
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/*--------------------------------------------------------------------------*/
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/* MSDC0~1 GPIO and IO Pad Configuration Base */
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/*--------------------------------------------------------------------------*/
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#define MSDC_GPIO_BASE gpio_base /* 0x10005000 */
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#define MSDC0_IO_PAD_BASE (msdc_io_cfg_bases[0]) /* 0x10002000 */
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#define MSDC1_IO_PAD_BASE (msdc_io_cfg_bases[1]) /* 0x10002400 */
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/*--------------------------------------------------------------------------*/
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/* MSDC GPIO Related Register */
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/*--------------------------------------------------------------------------*/
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/* MSDC0 */
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#define MSDC0_GPIO_MODE0 (MSDC_GPIO_BASE + 0x3f0)
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#define MSDC0_GPIO_MODE1 (MSDC_GPIO_BASE + 0x400)
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#define MSDC0_GPIO_MODE_TRAP (MSDC_GPIO_BASE + 0x6f0)
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#define MSDC0_GPIO_IES (MSDC0_IO_PAD_BASE + 0x10)
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#define MSDC0_GPIO_SMT (MSDC0_IO_PAD_BASE + 0x80)
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#define MSDC0_GPIO_TDSEL (MSDC0_IO_PAD_BASE + 0x90)
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#define MSDC0_GPIO_RDSEL (MSDC0_IO_PAD_BASE + 0x70)
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#define MSDC0_GPIO_DRV (MSDC0_IO_PAD_BASE + 0)
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#define MSDC0_GPIO_PUPD (MSDC0_IO_PAD_BASE + 0x30)
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#define MSDC0_GPIO_R0 (MSDC0_IO_PAD_BASE + 0x50)
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#define MSDC0_GPIO_R1 (MSDC0_IO_PAD_BASE + 0x60)
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/* MSDC1 */
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#define MSDC1_GPIO_MODE0 (MSDC_GPIO_BASE + 0x330)
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#define MSDC1_GPIO_MODE1 (MSDC_GPIO_BASE + 0x340)
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#define MSDC1_GPIO_IES (MSDC1_IO_PAD_BASE + 0x20)
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#define MSDC1_GPIO_SMT (MSDC1_IO_PAD_BASE + 0xb0)
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#define MSDC1_GPIO_TDSEL (MSDC1_IO_PAD_BASE + 0xd0)
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#define MSDC1_GPIO_RDSEL (MSDC1_IO_PAD_BASE + 0x90)
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#define MSDC1_GPIO_DRV (MSDC1_IO_PAD_BASE + 0)
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#define MSDC1_GPIO_SR (MSDC1_IO_PAD_BASE + 0xc0)
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#define MSDC1_GPIO_PUPD (MSDC1_IO_PAD_BASE + 0x50)
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#define MSDC1_GPIO_R0 (MSDC1_IO_PAD_BASE + 0x70)
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#define MSDC1_GPIO_R1 (MSDC1_IO_PAD_BASE + 0x80)
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/**************************************************************/
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/* Section 5: Adjustable Driver Parameter */
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/**************************************************************/
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#define HOST_MAX_BLKSZ (2048)
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#define MSDC_OCR_AVAIL\
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(MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 \
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| MMC_VDD_31_32 | MMC_VDD_32_33)
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/* data timeout counter. 1048576 * 3 sclk. */
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#define DEFAULT_DTOC (3)
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#define MAX_DMA_CNT (4 * 1024 * 1024)
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/* a WIFI transaction may be 50K */
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#define MAX_DMA_CNT_SDIO (0xFFFFFFFF - 255)
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/* a LTE transaction may be 128K */
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#define MAX_HW_SGMTS (MAX_BD_NUM)
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#define MAX_PHY_SGMTS (MAX_BD_NUM)
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#define MAX_SGMT_SZ (MAX_DMA_CNT)
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#define MAX_SGMT_SZ_SDIO (MAX_DMA_CNT_SDIO)
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#define HOST_MAX_NUM (2)
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#ifdef CONFIG_PWR_LOSS_MTK_TEST
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#define MAX_REQ_SZ (512 * 65536)
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#else
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#define MAX_REQ_SZ (512 * 1024)
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#endif
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#ifdef FPGA_PLATFORM
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#define HOST_MAX_MCLK (200000000)
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#else
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#define HOST_MAX_MCLK (200000000)
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#endif
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#define HOST_MIN_MCLK (260000)
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/* SD card, bad card handling settings */
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/* if continuous data timeout reach the limit */
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/* driver will force remove card */
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#define MSDC_MAX_DATA_TIMEOUT_CONTINUOUS (100)
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/* if continuous power cycle fail reach the limit */
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/* driver will force remove card */
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#define MSDC_MAX_POWER_CYCLE_FAIL_CONTINUOUS (3)
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#define SDCARD_ESD_RECOVERY
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/* #define MSDC_HQA */
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/* sd read/write crc error happen in mt6885 when vcore changes,
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* sd can't support autok merge by fix vcore(like emmc),
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* so add runtime autok merge function
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*/
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#define SD_RUNTIME_AUTOK_MERGE
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/* fix vcore in kernel will affect other module,
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* use emmc runtime autok merge intead of the original emmc autok
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*/
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#define EMMC_RUNTIME_AUTOK_MERGE
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/**************************************************************/
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/* Section 6: BBChip-depenent Tunnig Parameter */
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/**************************************************************/
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#define EMMC_MAX_FREQ_DIV 4 /* lower frequence to 12.5M */
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#define MSDC_CLKTXDLY 0
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#define MSDC0_DDR50_DDRCKD 1 /* FIX ME: may be removed */
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#define VOL_CHG_CNT_DEFAULT_VAL 0x1F4 /* =500 */
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/* hw diff: 0xB0[0]=1 */
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#define MSDC_PB0_DEFAULT_VAL 0x403C0007
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#define MSDC_PB1_DEFAULT_VAL 0xFFFA0349
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#define MSDC_PB2_DEFAULT_RESPWAITCNT 0x3
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#define MSDC_PB2_DEFAULT_RESPSTENSEL 0x1
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#define MSDC_PB2_DEFAULT_CRCSTSENSEL 0x1
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#endif /* _MSDC_CUST_MT6765_H_ */
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