525 lines
20 KiB
C
525 lines
20 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MSDC_CUST_MT6885_H_
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#define _MSDC_CUST_MT6885_H_
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#ifdef CONFIG_FPGA_EARLY_PORTING
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#define FPGA_PLATFORM
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#else
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/* #define MTK_MSDC_BRINGUP_DEBUG */
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#endif
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#include <dt-bindings/mmc/mt6885-msdc.h>
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//#define CONFIG_MTK_MSDC_BRING_UP_BYPASS
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#if !defined(FPGA_PLATFORM)
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#include <dt-bindings/clock/mt6885-clk.h>
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#endif
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/**************************************************************/
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/* Section 1: Device Tree */
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/**************************************************************/
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/* Names used for device tree lookup */
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#define DT_COMPATIBLE_NAME "mediatek,msdc"
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#define MSDC0_CLK_NAME "msdc0-clock"
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#if defined(CONFIG_MTK_HW_FDE) || defined(CONFIG_MMC_CRYPTO)
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#define MSDC0_AES_CLK_NAME "msdc0-aes-clock"
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#endif
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#define MSDC0_HCLK_NAME "msdc0-hclock"
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#define MSDC1_CLK_NAME "msdc1-clock"
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#define MSDC1_HCLK_NAME "msdc1-hclock"
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#define MSDC0_IOCFG_NAME "mediatek,iocfg_tm"
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#define MSDC1_IOCFG_NAME "mediatek,iocfg_lm"
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#define MSDC1_A_IOCFG_NAME "mediatek,iocfg_rm"
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/**************************************************************/
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/* Section 2: Power */
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/**************************************************************/
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#define SD_POWER_DEFAULT_ON (0)
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#if !defined(FPGA_PLATFORM)
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#include <mt-plat/upmu_common.h>
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#define REG_VEMC_VOSEL_CAL PMIC_RG_VEMC_VOCAL_0_ADDR
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#define MASK_VEMC_VOSEL_CAL PMIC_RG_VEMC_VOCAL_0_MASK
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#define SHIFT_VEMC_VOSEL_CAL PMIC_RG_VEMC_VOCAL_0_SHIFT
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#define FIELD_VEMC_VOSEL_CAL (MASK_VEMC_VOSEL_CAL \
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<< SHIFT_VEMC_VOSEL_CAL)
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#define REG_VEMC_VOSEL PMIC_RG_VEMC_VOSEL_0_ADDR
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#define MASK_VEMC_VOSEL PMIC_RG_VEMC_VOSEL_0_MASK
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#define SHIFT_VEMC_VOSEL PMIC_RG_VEMC_VOSEL_0_SHIFT
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#define FIELD_VEMC_VOSEL (MASK_VEMC_VOSEL << SHIFT_VEMC_VOSEL)
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#define REG_VEMC_EN PMIC_RG_LDO_VEMC_EN_ADDR
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#define MASK_VEMC_EN PMIC_RG_LDO_VEMC_EN_MASK
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#define SHIFT_VEMC_EN PMIC_RG_LDO_VEMC_EN_SHIFT
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#define FIELD_VEMC_EN (MASK_VEMC_EN << SHIFT_VEMC_EN)
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#define REG_VMC_VOSEL_CAL PMIC_RG_VMC_VOCAL_ADDR
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#define MASK_VMC_VOSEL_CAL PMIC_RG_VMC_VOCAL_MASK
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#define SHIFT_VMC_VOSEL_CAL PMIC_RG_VMC_VOCAL_SHIFT
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#define FIELD_VMC_VOSEL_CAL (MASK_VMC_VOSEL_CAL \
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<< SHIFT_VMC_VOSEL_CAL)
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#define REG_VMC_VOSEL PMIC_RG_VMC_VOSEL_ADDR
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#define MASK_VMC_VOSEL PMIC_RG_VMC_VOSEL_MASK
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#define SHIFT_VMC_VOSEL PMIC_RG_VMC_VOSEL_SHIFT
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#define FIELD_VMC_VOSEL (MASK_VMC_VOSEL << SHIFT_VMC_VOSEL)
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#define REG_VMC_EN PMIC_RG_LDO_VMC_EN_ADDR
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#define MASK_VMC_EN PMIC_RG_LDO_VMC_EN_MASK
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#define SHIFT_VMC_EN PMIC_RG_LDO_VMC_EN_SHIFT
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#define FIELD_VMC_EN (MASK_VMC_EN << SHIFT_VMC_EN)
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#define REG_VMCH_VOSEL_CAL PMIC_RG_VMCH_VOCAL_ADDR
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#define MASK_VMCH_VOSEL_CAL PMIC_RG_VMCH_VOCAL_MASK
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#define SHIFT_VMCH_VOSEL_CAL PMIC_RG_VMCH_VOCAL_SHIFT
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#define FIELD_VMCH_VOSEL_CAL (MASK_VMCH_VOSEL_CAL \
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<< SHIFT_VMCH_VOSEL_CAL)
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#define REG_VMCH_VOSEL PMIC_RG_VMCH_VOSEL_ADDR
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#define MASK_VMCH_VOSEL PMIC_RG_VMCH_VOSEL_MASK
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#define SHIFT_VMCH_VOSEL PMIC_RG_VMCH_VOSEL_SHIFT
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#define FIELD_VMCH_VOSEL (MASK_VMCH_VOSEL << SHIFT_VMCH_VOSEL)
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#define REG_VMCH_EN PMIC_RG_LDO_VMCH_EN_ADDR
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#define MASK_VMCH_EN PMIC_RG_LDO_VMCH_EN_MASK
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#define SHIFT_VMCH_EN PMIC_RG_LDO_VMCH_EN_SHIFT
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#define FIELD_VMCH_EN (MASK_VMCH_EN << SHIFT_VMCH_EN)
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#define REG_VMCH_OC_RAW_STATUS PMIC_RG_INT_RAW_STATUS_VMCH_OC_ADDR
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#define MASK_VMCH_OC_RAW_STATUS PMIC_RG_INT_RAW_STATUS_VMCH_OC_MASK
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#define SHIFT_VMCH_OC_RAW_STATUS PMIC_RG_INT_RAW_STATUS_VMCH_OC_SHIFT
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#define FIELD_VMCH_OC_RAW_STATUS (MASK_VMCH_OC_RAW_STATUS \
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<< SHIFT_VMCH_OC_RAW_STATUS)
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#define REG_VMCH_OC_STATUS PMIC_RG_INT_STATUS_VMCH_OC_ADDR
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#define MASK_VMCH_OC_STATUS PMIC_RG_INT_STATUS_VMCH_OC_MASK
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#define SHIFT_VMCH_OC_STATUS PMIC_RG_INT_STATUS_VMCH_OC_SHIFT
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#define FIELD_VMCH_OC_STATUS (MASK_VMCH_OC_STATUS << SHIFT_VMCH_OC_STATUS)
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#define VEMC_VOSEL_CAL_mV(cal) ((cal >= 0) ? ((cal)/10) : 0)
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#define VEMC_VOSEL_2V9 (10)
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#define VEMC_VOSEL_3V (11)
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#define VEMC_VOSEL_3V3 (13)
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#define VMC_VOSEL_CAL_mV(cal) ((cal >= 0) ? ((cal)/10) : 0)
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#define VMC_VOSEL_1V8 (4)
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#define VMC_VOSEL_2V9 (10)
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#define VMC_VOSEL_3V (11)
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#define VMC_VOSEL_3V3 (13)
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#define VMCH_VOSEL_CAL_mV(cal) ((cal >= 0) ? ((cal)/10) : 0)
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#define VMCH_VOSEL_2V9 (2)
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#define VMCH_VOSEL_3V (3)
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#define VMCH_VOSEL_3V3 (5)
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#endif
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#define EMMC_VOL_ACTUAL VOL_3000
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#define SD_VOL_ACTUAL VOL_3000
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/**************************************************************/
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/* Section 3: Clock */
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/**************************************************************/
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#if !defined(FPGA_PLATFORM)
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/* MSDCPLL register offset */
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#define MSDCPLL_CON0_OFFSET (0x350)
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#define MSDCPLL_CON1_OFFSET (0x354)
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#define MSDCPLL_CON2_OFFSET (0x358)
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#define MSDCPLL_PWR_CON0_OFFSET (0x35c)
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#endif
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#define MSDCPLL_FREQ 400000000
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#define MSDC0_SRC_0 26000000
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#define MSDC0_SRC_1 MSDCPLL_FREQ
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#define MSDC0_SRC_2 (MSDCPLL_FREQ/2)
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#define MSDC0_SRC_3 156000000
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#define MSDC0_SRC_4 182000000
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#define MSDC0_SRC_5 312000000
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#define MSDC1_SRC_0 26000000
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#define MSDC1_SRC_1 208000000
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#define MSDC1_SRC_2 182000000
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#define MSDC1_SRC_3 156000000
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#define MSDC1_SRC_4 (MSDCPLL_FREQ/2)
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#define MSDC_SRC_FPGA 12000000
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/**************************************************************/
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/* Section 4: GPIO and Pad */
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/**************************************************************/
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/*--------------------------------------------------------------------------*/
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/* MSDC0~1 GPIO and IO Pad Configuration Base */
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/*--------------------------------------------------------------------------*/
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/* 0x10005000 */
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#define MSDC_GPIO_BASE gpio_base
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/*0x11F3_0000*/
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#define MSDC0_IO_PAD_BASE (msdc_io_cfg_bases[0])
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/*0x11E2_0000*/
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#define MSDC1_IO_PAD_BASE (msdc_io_cfg_bases[1])
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/*--------------------------------------------------------------------------*/
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/* MSDC GPIO Related Register */
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/*--------------------------------------------------------------------------*/
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/* MSDC0 */
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#define MSDC0_GPIO_MODE22 (MSDC_GPIO_BASE + 0x460)
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#define MSDC0_GPIO_MODE23 (MSDC_GPIO_BASE + 0x470)
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#define MSDC0_GPIO_MODE24 (MSDC_GPIO_BASE + 0x480)
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#define MSDC0_GPIO_DRV0 (MSDC0_IO_PAD_BASE + 0x00)
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#define MSDC0_GPIO_IES (MSDC0_IO_PAD_BASE + 0x50)
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#define MSDC0_GPIO_PUPD0 (MSDC0_IO_PAD_BASE + 0x80)
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#define MSDC0_GPIO_R0 (MSDC0_IO_PAD_BASE + 0xA0)
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#define MSDC0_GPIO_R1 (MSDC0_IO_PAD_BASE + 0xB0)
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#define MSDC0_GPIO_RDSEL0 (MSDC0_IO_PAD_BASE + 0xC0)
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#define MSDC0_GPIO_RDSEL0_1 (MSDC0_IO_PAD_BASE + 0xD0)
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#define MSDC0_GPIO_SMT (MSDC0_IO_PAD_BASE + 0xF0)
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#define MSDC0_GPIO_TDSEL0 (MSDC0_IO_PAD_BASE + 0x100)
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/* MSDC1 */
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#define MSDC1_GPIO_MODE6 (MSDC_GPIO_BASE + 0x360)
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#define MSDC1_GPIO_MODE7 (MSDC_GPIO_BASE + 0x370)
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#define MSDC1_GPIO_DRV0 (MSDC1_IO_PAD_BASE + 0x00)
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#define MSDC1_GPIO_IES (MSDC1_IO_PAD_BASE + 0x20)
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#define MSDC1_GPIO_PUPD0 (MSDC1_IO_PAD_BASE + 0x40)
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#define MSDC1_GPIO_R0 (MSDC1_IO_PAD_BASE + 0x60)
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#define MSDC1_GPIO_R1 (MSDC1_IO_PAD_BASE + 0x70)
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#define MSDC1_GPIO_RDSEL0 (MSDC1_IO_PAD_BASE + 0x80)
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#define MSDC1_GPIO_SMT (MSDC1_IO_PAD_BASE + 0x90)
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#define MSDC1_GPIO_SR (MSDC1_IO_PAD_BASE + 0xA0)
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#define MSDC1_GPIO_TDSEL0 (MSDC1_IO_PAD_BASE + 0xB0)
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#define MSDC1_GPIO_TDSEL0_1 (MSDC1_IO_PAD_BASE + 0xC0)
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/* MSDC1_PADA */
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#define MSDC1_GPIO_MISC (MSDC_GPIO_BASE + 0x600)
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#define MSDC1_GPIO_MODE1 (MSDC_GPIO_BASE + 0x310)
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#define MSDC1_GPIO_DRV0_A (MSDC1_IO_PAD_BASE + 0x00)
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#define MSDC1_GPIO_IES_A (MSDC1_IO_PAD_BASE + 0x20)
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#define MSDC1_GPIO_PUPD0_A (MSDC1_IO_PAD_BASE + 0x40)
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#define MSDC1_GPIO_R0_A (MSDC1_IO_PAD_BASE + 0x60)
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#define MSDC1_GPIO_R1_A (MSDC1_IO_PAD_BASE + 0x70)
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#define MSDC1_GPIO_RDSEL0_A (MSDC1_IO_PAD_BASE + 0x80)
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#define MSDC1_GPIO_SMT_A (MSDC1_IO_PAD_BASE + 0x90)
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#define MSDC1_GPIO_SR (MSDC1_IO_PAD_BASE + 0xA0)
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#define MSDC1_GPIO_TDSEL0_A (MSDC1_IO_PAD_BASE + 0xB0)
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/*
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* MSDC0 GPIO and PAD register and bitfields definition
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*/
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/* MSDC0_GPIO_MODE22, 001b is msdc mode*/
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#define MSDC0_MODE_CMD_MASK (0x7 << 28)
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/* MSDC0_GPIO_MODE23, 001b is msdc mode */
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#define MSDC0_MODE_DSL_MASK (0x7 << 28)
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#define MSDC0_MODE_DAT7_MASK (0x7 << 24)
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#define MSDC0_MODE_DAT5_MASK (0x7 << 20)
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#define MSDC0_MODE_DAT1_MASK (0x7 << 16)
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#define MSDC0_MODE_DAT6_MASK (0x7 << 12)
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#define MSDC0_MODE_DAT4_MASK (0x7 << 8)
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#define MSDC0_MODE_DAT2_MASK (0x7 << 4)
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#define MSDC0_MODE_DAT0_MASK (0x7 << 0)
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/* MSDC0_GPIO_MODE24, 001b is msdc mode */
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#define MSDC0_MODE_RSTB_MASK (0x7 << 8)
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#define MSDC0_MODE_DAT3_MASK (0x7 << 4)
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#define MSDC0_MODE_CLK_MASK (0x7 << 0)
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/* MSDC0 IES mask */
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#define MSDC0_IES_RSTB_MASK (0x1 << 29)
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#define MSDC0_IES_DSL_MASK (0x1 << 28)
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#define MSDC0_IES_DAT_MASK (0xFF << 20)
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#define MSDC0_IES_CMD_MASK (0x1 << 19)
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#define MSDC0_IES_CLK_MASK (0x1 << 18)
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#define MSDC0_IES_ALL_MASK (0xFFF << 18)
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/* MSDC0 SMT mask */
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#define MSDC0_SMT_DSL_MASK (0x1 << 5)
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#define MSDC0_SMT_DAT_MASK (0x1 << 4)
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#define MSDC0_SMT_CMD_MASK (0x1 << 3)
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#define MSDC0_SMT_CLK_MASK (0x1 << 2)
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#define MSDC0_SMT_ALL_MASK (0xF << 2)
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/* MSDC0 TDSEL0 mask */
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#define MSDC0_TDSEL0_DSL_MASK (0xF << 24)
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#define MSDC0_TDSEL0_DAT_MASK (0xF << 20)
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#define MSDC0_TDSEL0_CMD_MASK (0xF << 16)
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#define MSDC0_TDSEL0_CLK_MASK (0xF << 12)
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#define MSDC0_TDSEL0_ALL_MASK (0xFFFF << 12)
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/* MSDC0 RDSEL0 mask */
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#define MSDC0_RDSEL0_RSTB_MASK (0x3F << 0)
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#define MSDC0_RDSEL0_DSL_MASK (0x3F << 24)
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#define MSDC0_RDSEL0_DAT_MASK (0x3F << 18)
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#define MSDC0_RDSEL0_CMD_MASK (0x3F << 12)
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#define MSDC0_RDSEL0_CLK_MASK (0x3F << 6)
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#define MSDC0_RDSEL0_ALL_MASK_0 (0xFFFFFF << 6)
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#define MSDC0_RDSEL0_ALL_MASK_1 (0x3F << 0)
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/* MSDC0 DRV0 mask */
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#define MSDC0_DRV0_DSL_MASK (0x7 << 15)
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#define MSDC0_DRV0_DAT_MASK (0x7 << 12)
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#define MSDC0_DRV0_CMD_MASK (0x7 << 9)
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#define MSDC0_DRV0_CLK_MASK (0x7 << 6)
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#define MSDC0_DRV0_ALL_MASK (0xFFF << 6)
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/* MSDC0 PUPD mask*/
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#define MSDC0_PUPD_RSTB_MASK (0x1 << 11)
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#define MSDC0_PUPD_DSL_MASK (0x1 << 10)
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#define MSDC0_PUPD_DAT7_MASK (0x1 << 9)
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#define MSDC0_PUPD_DAT6_MASK (0x1 << 8)
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#define MSDC0_PUPD_DAT5_MASK (0x1 << 7)
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#define MSDC0_PUPD_DAT4_MASK (0x1 << 6)
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#define MSDC0_PUPD_DAT3_MASK (0x1 << 5)
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#define MSDC0_PUPD_DAT2_MASK (0x1 << 4)
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#define MSDC0_PUPD_DAT1_MASK (0x1 << 3)
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#define MSDC0_PUPD_DAT0_MASK (0x1 << 2)
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#define MSDC0_PUPD_CMD_MASK (0x1 << 1)
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#define MSDC0_PUPD_CLK_MASK (0x1 << 0)
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#define MSDC0_PUPD_DAT_MASK (0xFF << 2)
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#define MSDC0_PUPD_ALL_MASK (0x7FF << 0)
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/* MSDC0 R0 mask*/
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#define MSDC0_R0_RSTB_MASK (0x1 << 11)
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#define MSDC0_R0_DSL_MASK (0x1 << 10)
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#define MSDC0_R0_DAT7_MASK (0x1 << 9)
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#define MSDC0_R0_DAT6_MASK (0x1 << 8)
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#define MSDC0_R0_DAT5_MASK (0x1 << 7)
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#define MSDC0_R0_DAT4_MASK (0x1 << 6)
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#define MSDC0_R0_DAT3_MASK (0x1 << 5)
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#define MSDC0_R0_DAT2_MASK (0x1 << 4)
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#define MSDC0_R0_DAT1_MASK (0x1 << 3)
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#define MSDC0_R0_DAT0_MASK (0x1 << 2)
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#define MSDC0_R0_CMD_MASK (0x1 << 1)
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#define MSDC0_R0_CLK_MASK (0x1 << 0)
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#define MSDC0_R0_DAT_MASK (0xFF << 2)
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#define MSDC0_R0_ALL_MASK (0x7FF << 0)
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/* MSDC0 R1 mask*/
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#define MSDC0_R1_RSTB_MASK (0x1 << 11)
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#define MSDC0_R1_DSL_MASK (0x1 << 10)
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#define MSDC0_R1_DAT7_MASK (0x1 << 9)
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#define MSDC0_R1_DAT6_MASK (0x1 << 8)
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#define MSDC0_R1_DAT5_MASK (0x1 << 7)
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#define MSDC0_R1_DAT4_MASK (0x1 << 6)
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#define MSDC0_R1_DAT3_MASK (0x1 << 5)
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#define MSDC0_R1_DAT2_MASK (0x1 << 4)
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#define MSDC0_R1_DAT1_MASK (0x1 << 3)
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#define MSDC0_R1_DAT0_MASK (0x1 << 2)
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#define MSDC0_R1_CMD_MASK (0x1 << 1)
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#define MSDC0_R1_CLK_MASK (0x1 << 0)
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#define MSDC0_R1_DAT_MASK (0xFF << 2)
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#define MSDC0_R1_ALL_MASK (0x7FF << 0)
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/*
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* MSDC1 GPIO and PAD register and bitfields definition
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*/
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/* MSDC1_GPIO_MODE6, 0001b is msdc mode */
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#define MSDC1_MODE_CMD_MASK (0x7 << 16)
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#define MSDC1_MODE_CLK_MASK (0x7 << 12)
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/* MSDC1_GPIO_MODE7, 0001b is msdc mode */
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#define MSDC1_MODE_DAT1_MASK (0x7 << 0)
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#define MSDC1_MODE_DAT2_MASK (0x7 << 28)
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#define MSDC1_MODE_DAT0_MASK (0x7 << 24)
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#define MSDC1_MODE_DAT3_MASK (0x7 << 20)
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/* MSDC1 IES mask*/
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#define MSDC1_IES_DAT_MASK (0xF << 18)
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#define MSDC1_IES_CMD_MASK (0x1 << 17)
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#define MSDC1_IES_CLK_MASK (0x1 << 16)
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#define MSDC1_IES_ALL_MASK (0x3F << 16)
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/* MSDC1 SMT mask*/
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#define MSDC1_SMT_DAT_MASK (0x1 << 8)
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#define MSDC1_SMT_CMD_MASK (0x1 << 7)
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#define MSDC1_SMT_CLK_MASK (0x1 << 6)
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#define MSDC1_SMT_ALL_MASK (0x7 << 6)
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/* MSDC1 TDSEL0 mask*/
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#define MSDC1_TDSEL0_DAT_MASK (0xF << 0)
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#define MSDC1_TDSEL0_CMD_MASK (0xF << 28)
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#define MSDC1_TDSEL0_CLK_MASK (0xF << 24)
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#define MSDC1_TDSEL0_ALL_MASK (0xFF << 24)
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/* MSDC1 RDSEL0 mask*/
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#define MSDC1_RDSEL0_DAT_MASK (0x3F << 24)
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#define MSDC1_RDSEL0_CMD_MASK (0x3F << 18)
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#define MSDC1_RDSEL0_CLK_MASK (0x3F << 12)
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#define MSDC1_RDSEL0_ALL_MASK (0x3FFFF << 12)
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/* MSDC1 DRV0 mask*/
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#define MSDC1_DRV0_DAT_MASK (0x7 << 24)
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#define MSDC1_DRV0_CMD_MASK (0x7 << 21)
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#define MSDC1_DRV0_CLK_MASK (0x7 << 18)
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#define MSDC1_DRV0_ALL_MASK (0x1FF << 18)
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/* MSDC1 PUPD mask*/
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#define MSDC1_PUPD_DAT3_MASK (0x1 << 5)
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#define MSDC1_PUPD_DAT2_MASK (0x1 << 4)
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#define MSDC1_PUPD_DAT1_MASK (0x1 << 3)
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#define MSDC1_PUPD_DAT0_MASK (0x1 << 2)
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#define MSDC1_PUPD_CMD_MASK (0x1 << 1)
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#define MSDC1_PUPD_CLK_MASK (0x1 << 0)
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#define MSDC1_PUPD_ALL_MASK (0x3F << 0)
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/* MSDC1 R0 mask*/
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#define MSDC1_R0_DAT3_MASK (0x1 << 5)
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#define MSDC1_R0_DAT2_MASK (0x1 << 4)
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#define MSDC1_R0_DAT1_MASK (0x1 << 3)
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#define MSDC1_R0_DAT0_MASK (0x1 << 2)
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#define MSDC1_R0_CMD_MASK (0x1 << 1)
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#define MSDC1_R0_CLK_MASK (0x1 << 0)
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#define MSDC1_R0_ALL_MASK (0x3F << 0)
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/* MSDC1 R1 mask*/
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#define MSDC1_R1_DAT3_MASK (0x1 << 5)
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#define MSDC1_R1_DAT2_MASK (0x1 << 4)
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#define MSDC1_R1_DAT1_MASK (0x1 << 3)
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#define MSDC1_R1_DAT0_MASK (0x1 << 2)
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#define MSDC1_R1_CMD_MASK (0x1 << 1)
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#define MSDC1_R1_CLK_MASK (0x1 << 0)
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#define MSDC1_R1_ALL_MASK (0x3F << 0)
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/* FOR msdc_io_check() */
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#define MSDC1_PUPD_DAT0_ADDR MSDC1_GPIO_PUPD0
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#define MSDC1_PUPD_DAT1_ADDR MSDC1_GPIO_PUPD0
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#define MSDC1_PUPD_DAT2_ADDR MSDC1_GPIO_PUPD0
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#define MSDC1_R0_DAT0_ADDR MSDC1_GPIO_R0
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#define MSDC1_R0_DAT1_ADDR MSDC1_GPIO_R0
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#define MSDC1_R0_DAT2_ADDR MSDC1_GPIO_R0
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#define MSDC1_R1_DAT0_ADDR MSDC1_GPIO_R1
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#define MSDC1_R1_DAT1_ADDR MSDC1_GPIO_R1
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#define MSDC1_R1_DAT2_ADDR MSDC1_GPIO_R1
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#define MSDC1_PU (0)
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#define MSDC1_PD (1)
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#define MSDC1_8K (1)
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/* MSDC1_A_PIN_MUX_SEL */
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#define MSDC1_PIN_MUX_SEL_MASK_A (0x1 << 9)
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/*MSDC1_GPIO_MODE1, 0001b is msdc mode */
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#define MSDC1_MODE_DAT1_A_MASK (0x7 << 28)
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#define MSDC1_MODE_DAT2_A_MASK (0x7 << 24)
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#define MSDC1_MODE_DAT0_A_MASK (0x7 << 20)
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#define MSDC1_MODE_DAT3_A_MASK (0x7 << 16)
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#define MSDC1_MODE_CMD_A_MASK (0x7 << 12)
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#define MSDC1_MODE_CLK_A_MASK (0x7 << 8)
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/* MSDC1_A IES mask*/
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#define MSDC1_IES_ALL_MASK_A (0x3F << 9)
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/* MSDC1_A SMT mask*/
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#define MSDC1_SMT_ALL_MASK_A (0x1 << 4)
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/* MSDC1_A TDSEL0 mask*/
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#define MSDC1_TDSEL0_DAT_MASK_A (0xF << 16)
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#define MSDC1_TDSEL0_CMD_MASK_A (0xF << 16)
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#define MSDC1_TDSEL0_CLK_MASK_A (0xF << 16)
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/* MSDC1_A RDSEL0 mask*/
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#define MSDC1_RDSEL0_DAT_MASK_A (0x3F << 8)
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#define MSDC1_RDSEL0_CMD_MASK_A (0x3F << 8)
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#define MSDC1_RDSEL0_CLK_MASK_A (0x3F << 8)
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/* MSDC1_A DRV0 mask*/
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#define MSDC1_DRV0_DAT1_MASK_A (0x7 << 12)
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#define MSDC1_DRV0_DAT2_MASK_A (0x7 << 12)
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#define MSDC1_DRV0_DAT0_MASK_A (0x7 << 12)
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#define MSDC1_DRV0_DAT3_MASK_A (0x7 << 12)
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#define MSDC1_DRV0_CMD_MASK_A (0x7 << 12)
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#define MSDC1_DRV0_CLK_MASK_A (0x7 << 12)
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/* MSDC1_A PUPD mask*/
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#define MSDC1_PUPD_DAT1_MASK_A (0x1 << 5)
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#define MSDC1_PUPD_DAT2_MASK_A (0x1 << 4)
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#define MSDC1_PUPD_DAT0_MASK_A (0x1 << 3)
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#define MSDC1_PUPD_DAT3_MASK_A (0x1 << 2)
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#define MSDC1_PUPD_CMD_MASK_A (0x1 << 1)
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#define MSDC1_PUPD_CLK_MASK_A (0x1 << 0)
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#define MSDC1_PUPD_ALL_MASK_A (0x3F << 0)
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/* MSDC1_A R0 mask*/
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#define MSDC1_R0_DAT1_MASK_A (0x1 << 5)
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#define MSDC1_R0_DAT2_MASK_A (0x1 << 4)
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#define MSDC1_R0_DAT0_MASK_A (0x1 << 3)
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#define MSDC1_R0_DAT3_MASK_A (0x1 << 2)
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#define MSDC1_R0_CMD_MASK_A (0x1 << 1)
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#define MSDC1_R0_CLK_MASK_A (0x1 << 0)
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#define MSDC1_R0_ALL_MASK_A (0x3F << 0)
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/* MSDC1_A R1 mask*/
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#define MSDC1_R1_DAT1_MASK_A (0x1 << 5)
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#define MSDC1_R1_DAT2_MASK_A (0x1 << 4)
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#define MSDC1_R1_DAT0_MASK_A (0x1 << 3)
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#define MSDC1_R1_DAT3_MASK_A (0x1 << 2)
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#define MSDC1_R1_CMD_MASK_A (0x1 << 1)
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#define MSDC1_R1_CLK_MASK_A (0x1 << 0)
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#define MSDC1_R1_ALL_MASK_A (0x3F << 0)
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/* FOR msdc1_A_io_check() */
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#define MSDC1_PUPD_DAT0_ADDR_A MSDC1_GPIO_PUPD0_A
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#define MSDC1_PUPD_DAT1_ADDR_A MSDC1_GPIO_PUPD0_A
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#define MSDC1_PUPD_DAT2_ADDR_A MSDC1_GPIO_PUPD0_A
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#define MSDC1_R0_DAT0_ADDR_A MSDC1_GPIO_R0_A
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#define MSDC1_R0_DAT1_ADDR_A MSDC1_GPIO_R0_A
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#define MSDC1_R0_DAT2_ADDR_A MSDC1_GPIO_R0_A
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#define MSDC1_R1_DAT0_ADDR_A MSDC1_GPIO_R1_A
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#define MSDC1_R1_DAT1_ADDR_A MSDC1_GPIO_R1_A
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#define MSDC1_R1_DAT2_ADDR_A MSDC1_GPIO_R1_A
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/**************************************************************/
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/* Section 5: Adjustable Driver Parameter */
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/**************************************************************/
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#define HOST_MAX_BLKSZ (2048)
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#define MSDC_OCR_AVAIL\
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(MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 \
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| MMC_VDD_31_32 | MMC_VDD_32_33)
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/* data timeout counter. 1048576 * 3 sclk. */
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#define DEFAULT_DTOC (3)
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#define MAX_DMA_CNT (4 * 1024 * 1024)
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/* a WIFI transaction may be 50K */
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#define MAX_DMA_CNT_SDIO (0xFFFFFFFF - 255)
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/* a LTE transaction may be 128K */
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#define MAX_HW_SGMTS (MAX_BD_NUM)
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#define MAX_PHY_SGMTS (MAX_BD_NUM)
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#define MAX_SGMT_SZ (MAX_DMA_CNT)
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#define MAX_SGMT_SZ_SDIO (MAX_DMA_CNT_SDIO)
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#define HOST_MAX_NUM (2)
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#ifdef CONFIG_PWR_LOSS_MTK_TEST
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#define MAX_REQ_SZ (512 * 65536)
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#else
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#define MAX_REQ_SZ (512 * 1024)
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#endif
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#ifdef FPGA_PLATFORM
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#define HOST_MAX_MCLK (200000000)
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#else
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#define HOST_MAX_MCLK (200000000)
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#endif
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#define HOST_MIN_MCLK (260000)
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/* SD card, bad card handling settings */
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/* if continuous data timeout reach the limit */
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/* driver will force remove card */
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#define MSDC_MAX_DATA_TIMEOUT_CONTINUOUS (100)
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/* if continuous power cycle fail reach the limit */
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/* driver will force remove card */
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#define MSDC_MAX_POWER_CYCLE_FAIL_CONTINUOUS (3)
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/* sdcard esd recovery */
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/* power reset sdcard when sdcard hang from esd */
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#define SDCARD_ESD_RECOVERY
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/* #define MSDC_HQA */
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/* #define SDIO_HQA */
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/* sd read/write crc error happen in mt6885 when vcore changes,
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* sd can't support autok merge by fix vcore(like emmc),
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* so add runtime autok merge function
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*/
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#define SD_RUNTIME_AUTOK_MERGE
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/**************************************************************/
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/* Section 6: BBChip-depenent Tunnig Parameter */
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/**************************************************************/
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#define EMMC_MAX_FREQ_DIV 4 /* lower frequence to 12.5M */
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#define MSDC_CLKTXDLY 0
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#define MSDC0_DDR50_DDRCKD 1 /* FIX ME: may be removed */
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#define VOL_CHG_CNT_DEFAULT_VAL 0x1F4 /* =500 */
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#define MSDC_PB0_DEFAULT_VAL 0x403C0006
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#define MSDC_PB1_DEFAULT_VAL 0xFFE20349
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#define MSDC_PB2_DEFAULT_RESPWAITCNT 0x3
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#define MSDC_PB2_DEFAULT_RESPSTENSEL 0x1
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#define MSDC_PB2_DEFAULT_CRCSTSENSEL 0x1
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#endif /* _MSDC_CUST_MT6885_H_ */
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