328 lines
9.5 KiB
C
328 lines
9.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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*/
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#include "mtk_charger_intf.h"
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#include <linux/power_supply.h>
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#include <mt-plat/mtk_boot.h>
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#include <mt-plat/upmu_common.h>
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#include <mt-plat/v1/charger_type.h>
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#ifndef _sgm41516d_SW_H_
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#define _sgm41516d_SW_H_
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#define sgm41516d_CON0 0x00
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#define sgm41516d_CON1 0x01
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#define sgm41516d_CON2 0x02
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#define sgm41516d_CON3 0x03
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#define sgm41516d_CON4 0x04
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#define sgm41516d_CON5 0x05
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#define sgm41516d_CON6 0x06
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#define sgm41516d_CON7 0x07
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#define sgm41516d_CON8 0x08
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#define sgm41516d_CON9 0x09
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#define sgm41516d_CON10 0x0A
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#define sgm41516d_CON11 0x0B
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#define sgm41516d_CON12 0x0C
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#define sgm41516d_CON13 0x0D
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#define sgm41516d_CON14 0x0E
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#define sgm41516d_CON15 0x0F
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#define sgm41516d_REG_NUM 16
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/**********************************************************
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*
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* [MASK/SHIFT]
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*
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*********************************************************/
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//CON0
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#define CON0_EN_HIZ_MASK 0x01
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#define CON0_EN_HIZ_SHIFT 7
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#define CON0_STAT_IMON_CTRL_MASK 0x03
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#define CON0_STAT_IMON_CTRL_SHIFT 5
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#define CON0_IINLIM_MASK 0x1F
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#define CON0_IINLIM_SHIFT 0
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//CON1
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#define CON1_PFM_MASK 0x01
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#define CON1_PFM_SHIFT 7
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#define CON1_WDT_RST_MASK 0x01
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#define CON1_WDT_RST_SHIFT 6
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#define CON1_OTG_CONFIG_MASK 0x01
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#define CON1_OTG_CONFIG_SHIFT 5
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#define CON1_CHG_CONFIG_MASK 0x01
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#define CON1_CHG_CONFIG_SHIFT 4
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#define CON1_SYS_MIN_MASK 0x07
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#define CON1_SYS_MIN_SHIFT 1
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#define CON1_MIN_VBAT_SEL_MASK 0x01
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#define CON1_MIN_VBAT_SEL_SHIFT 0
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//CON2
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#define CON2_BOOST_LIM_MASK 0x01
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#define CON2_BOOST_LIM_SHIFT 7
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#define CON2_Q1_FULLON_MASK 0x01
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#define CON2_Q1_FULLON_SHIFT 6
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#define CON2_ICHG_MASK 0x3F
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#define CON2_ICHG_SHIFT 0
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//CON3
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#define CON3_IPRECHG_MASK 0x0F
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#define CON3_IPRECHG_SHIFT 4
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#define CON3_ITERM_MASK 0x0F
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#define CON3_ITERM_SHIFT 0
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//CON4
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#define CON4_VREG_MASK 0x1F
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#define CON4_VREG_SHIFT 3
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#define CON4_TOPOFF_TIMER_MASK 0x03
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#define CON4_TOPOFF_TIMER_SHIFT 1
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#define CON4_VRECHG_MASK 0x01
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#define CON4_VRECHG_SHIFT 0
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//CON5
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#define CON5_EN_TERM_MASK 0x01
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#define CON5_EN_TERM_SHIFT 7
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#define CON5_WATCHDOG_MASK 0x03
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#define CON5_WATCHDOG_SHIFT 4
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#define CON5_EN_TIMER_MASK 0x01
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#define CON5_EN_TIMER_SHIFT 3
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#define CON5_CHG_TIMER_MASK 0x01
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#define CON5_CHG_TIMER_SHIFT 2
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#define CON5_TREG_MASK 0x01
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#define CON5_TREG_SHIFT 1
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//CON6
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#define CON6_OVP_MASK 0x03
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#define CON6_OVP_SHIFT 6
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#define CON6_BOOSTV_MASK 0x3
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#define CON6_BOOSTV_SHIFT 4
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#define CON6_VINDPM_MASK 0x0F
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#define CON6_VINDPM_SHIFT 0
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//CON7
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#define CON7_FORCE_DPDM_MASK 0x01
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#define CON7_FORCE_DPDM_SHIFT 7
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#define CON7_TMR2X_EN_MASK 0x01
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#define CON7_TMR2X_EN_SHIFT 6
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#define CON7_BATFET_Disable_MASK 0x01
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#define CON7_BATFET_Disable_SHIFT 5
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#define CON7_BATFET_DLY_MASK 0x01
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#define CON7_BATFET_DLY_SHIFT 3
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#define CON7_BATFET_RST_EN_MASK 0x01
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#define CON7_BATFET_RST_EN_SHIFT 2
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#define CON7_VDPM_BAT_TRACK_MASK 0x03
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#define CON7_VDPM_BAT_TRACK_SHIFT 0
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//CON8
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#define CON8_VBUS_STAT_MASK 0x07
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#define CON8_VBUS_STAT_SHIFT 5
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#define CON8_CHRG_STAT_MASK 0x03
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#define CON8_CHRG_STAT_SHIFT 3
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#define CON8_PG_STAT_MASK 0x01
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#define CON8_PG_STAT_SHIFT 2
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#define CON8_THERM_STAT_MASK 0x01
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#define CON8_THERM_STAT_SHIFT 1
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#define CON8_VSYS_STAT_MASK 0x01
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#define CON8_VSYS_STAT_SHIFT 0
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//CON9
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#define CON9_WATCHDOG_FAULT_MASK 0x01
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#define CON9_WATCHDOG_FAULT_SHIFT 7
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#define CON9_OTG_FAULT_MASK 0x01
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#define CON9_OTG_FAULT_SHIFT 6
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#define CON9_CHRG_FAULT_MASK 0x03
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#define CON9_CHRG_FAULT_SHIFT 4
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#define CON9_BAT_FAULT_MASK 0x01
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#define CON9_BAT_FAULT_SHIFT 3
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#define CON9_NTC_FAULT_MASK 0x07
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#define CON9_NTC_FAULT_SHIFT 0
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//CON10
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#define CON10_VBUS_GD_MASK 0x01
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#define CON10_VBUS_GD_SHIFT 7
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#define CON10_VINDPM_STAT_MASK 0x01
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#define CON10_VINDPM_STAT_SHIFT 6
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#define CON10_IINDPM_STAT_MASK 0x01
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#define CON10_IINDPM_STAT_SHIFT 5
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#define CON10_TOPOFF_ACTIVE_MASK 0x01
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#define CON10_TOPOFF_ACTIVE_SHIFT 3
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#define CON10_ACOV_STAT_MASK 0x01
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#define CON10_ACOV_STAT_SHIFT 2
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#define CON10_VINDPM_INT_MASK 0x01
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#define CON10_VINDPM_INT_SHIFT 1
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#define CON10_INT_MASK_MASK 0x03
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#define CON10_INT_MASK_SHIFT 0
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//CON11
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#define CON11_REG_RST_MASK 0x01
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#define CON11_REG_RST_SHIFT 7
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#define CON11_PN_MASK 0x0F
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#define CON11_PN_SHIFT 3
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#define CON11_Rev_MASK 0x03
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#define CON11_Rev_SHIFT 0
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//CON13
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#define CV_OFFSET 3856000
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#define SPECIAL_CV_VAL 4352000
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#define SPECIAL_CV_BIT 0xF
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#define CON13_REG_EN_PUMPX_MASK 0x01
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#define CON13_REG_EN_PUMPX_SHIFT 7
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#define CON13_REG_DP_VSET_MASK 0x3
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#define CON13_REG_DP_VSET_SHIFT 3
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#define CON13_REG_DM_VSET_MASK 0x3
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#define CON13_REG_DM_VSET_SHIFT 1
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//CON15
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//MIVR VALUE
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#define VINDPM_OS0_MIVR_MIN 3900
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#define VINDPM_OS0_MIVR_MAX 5400
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#define VINDPM_OS1_MIVR_MIN 5900
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#define VINDPM_OS1_MIVR_MAX 7400
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#define VINDPM_OS2_MIVR_MIN 7500
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#define VINDPM_OS2_MIVR_MAX 9000
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#define VINDPM_OS3_MIVR_MIN 10500
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#define VINDPM_OS3_MIVR_MAX 12000
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#define VINDPM_OS_MIVR_STEP 100
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#define CON15_REG_VINDPM_OS_MASK 0x03
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#define CON15_REG_VINDPM_OS_SHIFT 0
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#define CON15_REG_FINE_TUNING_MASK 0x3
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#define CON15_REG_FINE_TUNING_SHIFT 6
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//CV fine tuning
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#define SMG41516_CV_TUNING_POST_VAL 8000
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#define SMG41516_CV_TUNING_POST 1
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#define SMG41516_CV_TUNING_NEG_VAL 8000
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#define SMG41516_CV_TUNING_NEG 2
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#define bq25600d_VENDOR_ID (0x01)
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#define bq25601_VENDOR_ID (0x02)
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#define SGM41516_VENDOR_ID (0x0C)
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#define SGM41516D_VENDOR_ID (0x0D)
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struct chg_type_record{
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int chg_type;
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int chg_type_count;
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};
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#define RECORD_NUM (11)
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struct sgm41516d_info {
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struct charger_device *chg_dev;
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struct charger_properties chg_props;
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struct device *dev;
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struct i2c_client *client;
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struct mutex sgm41516d_i2c_access;
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struct mutex sgm41516d_access_lock;
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const char *chg_dev_name;
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const char *eint_name;
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enum charger_type chg_type;
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int irq;
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};
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/**********************************************************
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*
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* [Extern Function]
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*
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*********************************************************/
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//CON0----------------------------------------------------
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extern void sgm41516d_set_en_hiz(struct sgm41516d_info *info, bool val);
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extern void sgm41516d_set_vindpm(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_iinlim(struct sgm41516d_info *info, unsigned int val);
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//CON1----------------------------------------------------
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extern void sgm41516d_set_reg_rst(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_pfm(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_wdt_rst(struct sgm41516d_info *info, bool val);
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extern void sgm41516d_set_chg_config(struct sgm41516d_info *info, bool val);
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extern void sgm41516d_set_otg_config(struct sgm41516d_info *info, bool val);
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extern void sgm41516d_set_sys_min(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_boost_lim(struct sgm41516d_info *info, unsigned int val);
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//CON2----------------------------------------------------
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extern void sgm41516d_set_ichg(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_rdson(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_force_20pct(struct sgm41516d_info *info, unsigned int val);
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//CON3----------------------------------------------------
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extern void sgm41516d_set_iprechg(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_iterm(struct sgm41516d_info *info, unsigned int val);
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//CON4----------------------------------------------------
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extern void sgm41516d_set_vreg(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_batlowv(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_vrechg(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_topoff_timer(struct sgm41516d_info *info, unsigned int val);
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//CON5----------------------------------------------------
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extern void sgm41516d_set_en_term(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_term_stat(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_watchdog(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_en_timer(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_chg_timer(struct sgm41516d_info *info, unsigned int val);
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//CON6----------------------------------------------------
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extern void sgm41516d_set_treg(struct sgm41516d_info *info, unsigned int val);
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//CON7----------------------------------------------------
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extern void sgm41516d_set_tmr2x_en(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_batfet_disable(struct sgm41516d_info *info, unsigned int val);
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extern void sgm41516d_set_int_mask(struct sgm41516d_info *info, unsigned int val);
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//CON8----------------------------------------------------
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extern unsigned int sgm41516d_get_system_status(struct sgm41516d_info *info);
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extern unsigned int sgm41516d_get_vbus_stat(struct sgm41516d_info *info);
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extern unsigned int sgm41516d_get_chrg_stat(struct sgm41516d_info *info);
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extern unsigned int sgm41516d_get_vsys_stat(struct sgm41516d_info *info);
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//---------------------------------------------------------
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extern unsigned int sgm41516d_read_interface (struct sgm41516d_info *info,
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unsigned char RegNum,
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unsigned char *val,
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unsigned char MASK,
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unsigned char SHIFT);
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extern unsigned int sgm41516d_config_interface (struct sgm41516d_info *info,
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unsigned char RegNum,
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unsigned char val,
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unsigned char MASK,
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unsigned char SHIFT);
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#endif // _sgm41516d_SW_H_
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