146 lines
3.6 KiB
C
146 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 MediaTek Inc.
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*/
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#ifndef __DEVAPC_MT6781_H__
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#define __DEVAPC_MT6781_H__
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/******************************************************************************
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* VARIABLE DEFINATION
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******************************************************************************/
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/* dbg status default setting */
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#define PLAT_DBG_UT_DEFAULT false
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#define PLAT_DBG_KE_DEFAULT true
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#define PLAT_DBG_AEE_DEFAULT true
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#define PLAT_DBG_DAPC_DEFAULT false
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#define PLAT_VIO_CFG_MAX_IDX 518
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#define PLAT_VIO_MAX_IDX 558
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#define PLAT_VIO_MASK_STA_NUM 18
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#define PLAT_VIO_SHIFT_MAX_BIT 21
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/******************************************************************************
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* DATA STRUCTURE & FUNCTION DEFINATION
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******************************************************************************/
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const char *bus_id_to_master(int bus_id, uint32_t vio_addr, int vio_idx);
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const char *index_to_subsys(unsigned int index);
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/* violation index corresponds to subsys */
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enum SMI_INDEX {
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SMI_COMMON = 161,
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SMI_LARB0 = 162,
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SMI_LARB1 = 163,
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DISP_SMI_2X1_SUB_COMMON_U0 = 186,
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DISP_SMI_2X1_SUB_COMMON_U1 = 187,
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IMG1_SMI_2X1_SUB_COMMON = 189,
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SMI_LARB9 = 222,
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SMI_LARB11 = 255,
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SMI_LARB12 = 256,
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SMI_LARB7 = 277,
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SMI_LARB13 = 285,
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SMI_LARB14 = 286,
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CAM_SIM_3X1_SUB_COMMON_U0 = 296,
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CAM_SIM_4X1_SUB_COMMON_U0 = 297,
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SMI_LARB_16 = 299,
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SMI_LARB_17 = 300,
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SMI_LARB0_S = 472,
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IPE_SMI_2X1_SUB_COMMON = 500,
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SMI_LARB20 = 501,
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SMI_LARB19 = 517,
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};
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enum MMSYS_INDEX {
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MMSYS_MDP_START = 245,
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MMSYS_MDP_END = 252,
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MMSYS_DISP_START = 253,
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MMSYS_DISP_END = 271,
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MMSYS_MDP2_START = 272,
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MMSYS_MDP2_END = 279,
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};
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enum IMGSYS_INDEX {
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IMGSYS1_TOP = 208,
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IMGSYS2_TOP = 240,
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};
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enum VENCSYS_INDEX {
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VENC_GLOBAL_CON = 276,
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VENC = 278,
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VENC_MBIST_CTR = 282,
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};
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enum VDECSYS_INDEX {
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VDECSYS_START = 258,
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VDECSYS_END = 274,
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};
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enum CAMSYS_INDEX {
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CAMSYS_START = 332,
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CAMSYS_END = 443,
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CAMSYS_SENINF_START = 288,
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CAMSYS_SENINF_END = 295,
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CAMSYS_P1_START = 430,
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CAMSYS_P1_END = 443,
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};
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enum OTHER_TYPES_INDEX {
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SRAMROM_VIO_INDEX = 546,
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TOPAXI_SI0_DECERR = 540,
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PERIAXI_SI1_DECERR = 542,
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};
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enum BUSID_LENGTH {
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PERIAXI_INT_MI_BIT_LENGTH = 4,
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TOPAXI_MI0_BIT_LENGTH = 14,
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};
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/* bit == 2 means don't care */
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struct PERIAXI_ID_INFO {
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const char *master;
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uint8_t bit[PERIAXI_INT_MI_BIT_LENGTH];
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};
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struct TOPAXI_ID_INFO {
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const char *master;
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uint8_t bit[TOPAXI_MI0_BIT_LENGTH];
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};
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/******************************************************************************
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* PLATFORM DEFINATION
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******************************************************************************/
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/* For Infra VIO_DBG */
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#define INFRA_VIO_DBG_MSTID 0x0000FFFF
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#define INFRA_VIO_DBG_MSTID_START_BIT 0
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#define INFRA_VIO_DBG_DMNID 0x003F0000
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#define INFRA_VIO_DBG_DMNID_START_BIT 16
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#define INFRA_VIO_DBG_W_VIO 0x00400000
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#define INFRA_VIO_DBG_W_VIO_START_BIT 22
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#define INFRA_VIO_DBG_R_VIO 0x00800000
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#define INFRA_VIO_DBG_R_VIO_START_BIT 23
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#define INFRA_VIO_ADDR_HIGH 0x0F000000
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#define INFRA_VIO_ADDR_HIGH_START_BIT 24
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/* For SRAMROM VIO */
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#define SRAMROM_SEC_VIO_ID_MASK 0x00FFFF00
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#define SRAMROM_SEC_VIO_ID_SHIFT 8
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#define SRAMROM_SEC_VIO_DOMAIN_MASK 0x0F000000
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#define SRAMROM_SEC_VIO_DOMAIN_SHIFT 24
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#define SRAMROM_SEC_VIO_RW_MASK 0x80000000
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#define SRAMROM_SEC_VIO_RW_SHIFT 31
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/* For DEVAPC PD */
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#define PD_VIO_MASK_OFFSET 0x0
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#define PD_VIO_STA_OFFSET 0x400
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#define PD_VIO_DBG0_OFFSET 0x900
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#define PD_VIO_DBG1_OFFSET 0x904
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#define PD_APC_CON_OFFSET 0xF00
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#define PD_SHIFT_STA_OFFSET 0xF10
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#define PD_SHIFT_SEL_OFFSET 0xF14
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#define PD_SHIFT_CON_OFFSET 0xF20
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#endif /* __DEVAPC_MT6781_H__ */
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