123 lines
3.4 KiB
C
123 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015-2020 MediaTek Inc.
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*/
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#ifndef __DAPC_H__
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#define __DAPC_H__
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#include <linux/types.h>
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/******************************************************************************
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* CONSTANT DEFINATION
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******************************************************************************/
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#define MOD_NO_IN_1_DEVAPC 16
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#define DEVAPC_TAG "DEVAPC"
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/* 1: Force to enable enhanced one-core violation debugging */
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/* 0: Enhanced one-core violation debugging can be enabled dynamically */
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/* Notice: You should only use one core to debug */
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#ifdef DBG_ENABLE
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#define DEVAPC_ENABLE_ONE_CORE_VIOLATION_DEBUG 1
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#else
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#define DEVAPC_ENABLE_ONE_CORE_VIOLATION_DEBUG 0
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#endif
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#define MTK_SIP_LK_DAPC 0x82000101
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#define DAPC_DEVICE_TREE_NODE_PD_INFRA_INDEX 0
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/* Uncomment to enable AEE */
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#define DEVAPC_ENABLE_AEE 1
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#define DEVAPC_TOTAL_SLAVES 214
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#if defined(CONFIG_MTK_AEE_FEATURE) && defined(DEVAPC_ENABLE_AEE)
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/* This is necessary for AEE */
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#endif
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/* For Infra VIO_DBG */
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#define INFRA_VIO_DBG_MSTID 0x0000FFFF
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#define INFRA_VIO_DBG_MSTID_START_BIT 0
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#define INFRA_VIO_DBG_DMNID 0x003F0000
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#define INFRA_VIO_DBG_DMNID_START_BIT 16
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#define INFRA_VIO_DBG_W_VIO 0x00400000
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#define INFRA_VIO_DBG_W_VIO_START_BIT 22
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#define INFRA_VIO_DBG_R_VIO 0x00800000
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#define INFRA_VIO_DBG_R_VIO_START_BIT 23
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#define INFRA_VIO_ADDR_HIGH 0x0F000000
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#define INFRA_VIO_ADDR_HIGH_START_BIT 24
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/******************************************************************************
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* REGISTER ADDRESS DEFINATION
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******************************************************************************/
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/* Device APC PD */
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#define PD_INFRA_VIO_SHIFT_MAX_BIT 22
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#define PD_INFRA_VIO_MASK_MAX_INDEX 276
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#define PD_INFRA_VIO_STA_MAX_INDEX 276
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#define DEVAPC_PD_INFRA_VIO_MASK(index) \
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((unsigned int *)(devapc_pd_infra_base + 0x4 * index))
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#define DEVAPC_PD_INFRA_VIO_STA(index) \
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((unsigned int *)(devapc_pd_infra_base + 0x400 + 0x4 * index))
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#define DEVAPC_PD_INFRA_VIO_DBG0 \
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((unsigned int *)(devapc_pd_infra_base+0x900))
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#define DEVAPC_PD_INFRA_VIO_DBG1 \
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((unsigned int *)(devapc_pd_infra_base+0x904))
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#define DEVAPC_PD_INFRA_APC_CON \
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((unsigned int *)(devapc_pd_infra_base+0xF00))
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#define DEVAPC_PD_INFRA_VIO_SHIFT_STA \
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((unsigned int *)(devapc_pd_infra_base+0xF10))
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#define DEVAPC_PD_INFRA_VIO_SHIFT_SEL \
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((unsigned int *)(devapc_pd_infra_base+0xF14))
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#define DEVAPC_PD_INFRA_VIO_SHIFT_CON \
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((unsigned int *)(devapc_pd_infra_base+0xF20))
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struct DEVICE_INFO {
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const char *device;
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bool enable_vio_irq;
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};
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#ifdef CONFIG_MTK_HIBERNATION
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extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
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extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
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#endif
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enum DEVAPC_SLAVE_TYPE {
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E_DAPC_INFRA_PERI_SLAVE = 0,
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E_DAPC_MM_SLAVE,
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E_DAPC_MD_SLAVE,
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E_DAPC_PERI_SLAVE,
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E_DAPC_MM2ND_SLAVE,
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E_DAPC_OTHERS_SLAVE,
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E_DAPC_SLAVE_TYPE_RESERVRD = 0x7FFFFFFF /* force enum to use 32 bits */
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};
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enum E_MASK_DOM {
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E_DOMAIN_0 = 0,
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E_DOMAIN_1,
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E_DOMAIN_2,
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E_DOMAIN_3,
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E_DOMAIN_4,
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E_DOMAIN_5,
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E_DOMAIN_6,
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E_DOMAIN_7,
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E_DOMAIN_8,
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E_DOMAIN_9,
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E_DOMAIN_10,
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E_DOMAIN_11,
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E_DOMAIN_12,
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E_DOMAIN_13,
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E_DOMAIN_14,
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E_DOMAIN_15,
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E_DOMAIN_OTHERS,
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E_MASK_DOM_RESERVRD = 0x7FFFFFFF /* force enum to use 32 bits */
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};
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#endif /* __DAPC_H__ */
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