399 lines
11 KiB
C
399 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT6761_H
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#define _DT_BINDINGS_CLK_MT6761_H
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_MFGPLL 2
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#define CLK_APMIXED_MMPLL 3
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#define CLK_APMIXED_UNIV2PLL 4
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#define CLK_APMIXED_MSDCPLL 5
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#define CLK_APMIXED_APLL1 6
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#define CLK_APMIXED_MPLL 7
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#define CLK_APMIXED_ULPOSC1 8
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#define CLK_APMIXED_ULPOSC2 9
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#define CLK_APMIXED_SSUSB26M 10
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#define CLK_APMIXED_APPLL26M 11
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#define CLK_APMIXED_MIPIC0_26M 12
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#define CLK_APMIXED_MDPLLGP26M 13
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#define CLK_APMIXED_MMSYS_F26M 14
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#define CLK_APMIXED_UFS26M 15
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#define CLK_APMIXED_MIPIC1_26M 16
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#define CLK_APMIXED_MEMPLL26M 17
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#define CLK_APMIXED_CLKSQ_LVPLL_26M 18
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#define CLK_APMIXED_MIPID0_26M 19
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#define CLK_APMIXED_NR_CLK 20
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/* TOPCKGEN */
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#define CLK_TOP_CLK32K 0
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#define CLK_TOP_CLK26M 1
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#define CLK_TOP_SYSPLL 2
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#define CLK_TOP_SYSPLL_D2 3
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#define CLK_TOP_SYSPLL1_D2 4
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#define CLK_TOP_SYSPLL1_D4 5
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#define CLK_TOP_SYSPLL1_D8 6
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#define CLK_TOP_SYSPLL1_D16 7
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#define CLK_TOP_SYSPLL_D3 8
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#define CLK_TOP_SYSPLL2_D2 9
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#define CLK_TOP_SYSPLL2_D4 10
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#define CLK_TOP_SYSPLL2_D8 11
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#define CLK_TOP_SYSPLL_D5 12
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#define CLK_TOP_SYSPLL3_D2 13
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#define CLK_TOP_SYSPLL3_D4 14
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#define CLK_TOP_SYSPLL_D7 15
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#define CLK_TOP_SYSPLL4_D2 16
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#define CLK_TOP_SYSPLL4_D4 17
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#define CLK_TOP_USB20_192M 18
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#define CLK_TOP_USB20_192M_D4 19
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#define CLK_TOP_USB20_192M_D8 20
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#define CLK_TOP_USB20_192M_D16 21
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#define CLK_TOP_USB20_192M_D32 22
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#define CLK_TOP_USB_PHY48M 23
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#define CLK_TOP_UNIVPLL 24
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#define CLK_TOP_UNIVPLL_D2 25
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#define CLK_TOP_UNIVPLL1_D2 26
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#define CLK_TOP_UNIVPLL1_D4 27
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#define CLK_TOP_UNIVPLL_D3 28
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#define CLK_TOP_UNIVPLL2_D2 29
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#define CLK_TOP_UNIVPLL2_D4 30
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#define CLK_TOP_UNIVPLL2_D8 31
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#define CLK_TOP_UNIVPLL2_D32 32
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#define CLK_TOP_UNIVPLL_D5 33
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#define CLK_TOP_UNIVPLL3_D2 34
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#define CLK_TOP_UNIVPLL3_D4 35
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#define CLK_TOP_MMPLL 36
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#define CLK_TOP_MMPLL_D2 37
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#define CLK_TOP_MPLL_104M 38
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#define CLK_TOP_MPLL_52M 39
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#define CLK_TOP_MFGPLL 40
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#define CLK_TOP_MSDCPLL 41
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#define CLK_TOP_MSDCPLL_D2 42
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#define CLK_TOP_APLL1 43
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#define CLK_TOP_APLL1_D2 44
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#define CLK_TOP_APLL1_D4 45
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#define CLK_TOP_APLL1_D8 46
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#define CLK_TOP_ULPOSC1_D2 47
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#define CLK_TOP_ULPOSC1_D4 48
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#define CLK_TOP_ULPOSC1_D8 49
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#define CLK_TOP_ULPOSC1_D16 50
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#define CLK_TOP_ULPOSC1_D32 51
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#define CLK_TOP_DMPLL 52
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#define CLK_TOP_DA_USB20_48M_DIV 53
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#define CLK_TOP_DA_UNIV_48M_DIV 54
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#define CLK_TOP_DA_MPLL_104M_DIV 55
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#define CLK_TOP_DA_MPLL_52M_DIV 56
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#define CLK_TOP_CSW_FAXI 57
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#define CLK_TOP_CSW_FMSDC30_1 58
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#define CLK_TOP_CSW_FMSDC30_2 59
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#define CLK_TOP_AXI 60
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#define CLK_TOP_MEM 61
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#define CLK_TOP_MM 62
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#define CLK_TOP_SCP 63
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#define CLK_TOP_MFG 64
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#define CLK_TOP_F_FUART 65
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#define CLK_TOP_SPI 66
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#define CLK_TOP_MSDC50_0 67
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#define CLK_TOP_AUDIO 68
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#define CLK_TOP_AUD_1 69
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#define CLK_TOP_AUD_ENGEN1 70
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#define CLK_TOP_F_FDISP_PWM 71
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#define CLK_TOP_SSPM 72
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#define CLK_TOP_DXCC 73
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#define CLK_TOP_I2C 74
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#define CLK_TOP_F_FPWM 75
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#define CLK_TOP_F_FSENINF 76
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#define CLK_TOP_AES_FDE 77
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#define CLK_TOP_F_BIST2FPC 78
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#define CLK_TOP_ARMPLL_DIVIDER_PLL0 79
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#define CLK_TOP_ARMPLL_DIVIDER_PLL1 80
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#define CLK_TOP_ARMPLL_DIVIDER_PLL2 81
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#define CLK_TOP_UFS_TICK1US 82
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#define CLK_TOP_APLL12_DIV0 83
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#define CLK_TOP_APLL12_DIV1 84
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#define CLK_TOP_APLL12_DIV2 85
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#define CLK_TOP_APLL12_DIV3 86
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#define CLK_TOP_APLL12_DIV4 87
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#define CLK_TOP_APLL12_DIVB 88
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#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 89
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#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 90
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#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 91
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#define CLK_TOP_FMEM_OCC_DRC_EN 92
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#define CLK_TOP_USB20_48M_EN 93
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#define CLK_TOP_UNIVPLL_48M_EN 94
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#define CLK_TOP_MPLL_104M_EN 95
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#define CLK_TOP_MPLL_52M_EN 96
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#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 97
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#define CLK_TOP_UFS_TICK1US_EN 98
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#define CLK_TOP_F_BIST2FPC_EN 99
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#define CLK_TOP_QS_CG 100
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#define CLK_TOP_MD_32K 101
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#define CLK_TOP_MD_26M 102
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#define CLK_TOP_CONN_32K 103
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#define CLK_TOP_CONN_26M 104
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#define CLK_TOP_AXI_SEL 105
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#define CLK_TOP_MEM_SEL 106
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#define CLK_TOP_MM_SEL 107
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#define CLK_TOP_SCP_SEL 108
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#define CLK_TOP_MFG_SEL 109
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#define CLK_TOP_ATB_SEL 110
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#define CLK_TOP_CAMTG_SEL 111
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#define CLK_TOP_CAMTG1_SEL 112
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#define CLK_TOP_CAMTG2_SEL 113
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#define CLK_TOP_CAMTG3_SEL 114
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#define CLK_TOP_UART_SEL 115
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#define CLK_TOP_SPI_SEL 116
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#define CLK_TOP_MSDC50_0_HCLK_SEL 117
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#define CLK_TOP_MSDC50_0_SEL 118
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#define CLK_TOP_MSDC30_1_SEL 119
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#define CLK_TOP_AUDIO_SEL 120
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#define CLK_TOP_AUD_INTBUS_SEL 121
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#define CLK_TOP_AUD_1_SEL 122
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#define CLK_TOP_AUD_ENGEN1_SEL 123
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#define CLK_TOP_DISP_PWM_SEL 124
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#define CLK_TOP_SSPM_SEL 125
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#define CLK_TOP_DXCC_SEL 126
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#define CLK_TOP_USB_TOP_SEL 127
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#define CLK_TOP_SPM_SEL 128
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#define CLK_TOP_I2C_SEL 129
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#define CLK_TOP_PWM_SEL 130
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#define CLK_TOP_SENINF_SEL 131
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#define CLK_TOP_AES_FDE_SEL 132
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#define CLK_TOP_PWRAP_ULPOSC_SEL 133
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#define CLK_TOP_CAMTM_SEL 134
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#define CLK_TOP_CLK13M 135
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#define CLK_TOP_NR_CLK 136
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/* INFRACFG */
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#define CLK_IFR_TOPAXI_DISABLE 0
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#define CLK_IFR_PMIC_TMR 1
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#define CLK_IFR_PMIC_AP 2
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#define CLK_IFR_PMIC_MD 3
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#define CLK_IFR_PMIC_CONN 4
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#define CLK_IFR_SCP_CORE 5
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#define CLK_IFR_SEJ 6
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#define CLK_IFR_APXGPT 7
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#define CLK_IFR_ICUSB 8
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#define CLK_IFR_GCE 9
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#define CLK_IFR_THERM 10
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#define CLK_IFR_I2C_AP 11
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#define CLK_IFR_I2C_CCU 12
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#define CLK_IFR_I2C_SSPM 13
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#define CLK_IFR_I2C_RSV 14
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#define CLK_IFR_PWM_HCLK 15
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#define CLK_IFR_PWM1 16
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#define CLK_IFR_PWM2 17
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#define CLK_IFR_PWM3 18
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#define CLK_IFR_PWM4 19
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#define CLK_IFR_PWM5 20
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#define CLK_IFR_PWM 21
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#define CLK_IFR_UART0 22
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#define CLK_IFR_UART1 23
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#define CLK_IFR_GCE_26M 24
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#define CLK_IFR_CQ_DMA_FPC 25
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#define CLK_IFR_BTIF 26
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#define CLK_IFR_SPI0 27
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#define CLK_IFR_MSDC0 28
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#define CLK_IFR_MSDC1 29
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#define CLK_IFR_DVFSRC 30
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#define CLK_IFR_GCPU 31
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#define CLK_IFR_TRNG 32
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#define CLK_IFR_AUXADC 33
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#define CLK_IFR_CPUM 34
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#define CLK_IFR_CCIF1_AP 35
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#define CLK_IFR_CCIF1_MD 36
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#define CLK_IFR_AUXADC_MD 37
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#define CLK_IFR_AP_DMA 38
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#define CLK_IFR_XIU 39
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#define CLK_IFR_DEVICE_APC 40
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#define CLK_IFR_CCIF_AP 41
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#define CLK_IFR_DEBUGSYS 42
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#define CLK_IFR_AUDIO 43
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#define CLK_IFR_CCIF_MD 44
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#define CLK_IFR_DXCC_SEC_CORE 45
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#define CLK_IFR_DXCC_AO 46
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#define CLK_IFR_DRAMC_F26M 47
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#define CLK_IFR_RG_PWM_FBCLK6 48
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#define CLK_IFR_DISP_PWM 49
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#define CLK_IFR_CLDMA_BCLK 50
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#define CLK_IFR_AUDIO_26M_BCLK 51
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#define CLK_IFR_SPI1 52
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#define CLK_IFR_I2C4 53
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#define CLK_IFR_MODEM_TEMP_SHARE 54
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#define CLK_IFR_SPI2 55
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#define CLK_IFR_SPI3 56
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#define CLK_IFR_SSPM 57
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#define CLK_IFR_I2C5 58
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#define CLK_IFR_I2C5_ARBITER 59
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#define CLK_IFR_I2C5_IMM 60
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#define CLK_IFR_I2C1_ARBITER 61
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#define CLK_IFR_I2C1_IMM 62
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#define CLK_IFR_I2C2_ARBITER 63
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#define CLK_IFR_I2C2_IMM 64
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#define CLK_IFR_SPI4 65
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#define CLK_IFR_SPI5 66
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#define CLK_IFR_CQ_DMA 67
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#define CLK_IFR_BIST2FPC 68
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#define CLK_IFR_FAES_FDE 69
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#define CLK_IFR_MSDC0_SELF 70
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#define CLK_IFR_MSDC1_SELF 71
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#define CLK_IFR_MSDC2_SELF 72
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#define CLK_IFR_SSPM_26M_SELF 73
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#define CLK_IFR_SSPM_32K_SELF 74
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#define CLK_IFR_UFS_AXI 75
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#define CLK_IFR_I2C6 76
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#define CLK_IFR_AP_MSDC0 77
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#define CLK_IFR_MD_MSDC0 78
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#define CLK_IFR_MSDC0_SRC 79
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#define CLK_IFR_MSDC1_SRC 80
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#define CLK_IFR_MSDC2_SRC 81
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#define CLK_IFR_PWRAP_TMR 82
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#define CLK_IFR_PWRAP_SPI 83
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#define CLK_IFR_PWRAP_SYS 84
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#define CLK_IFR_SEJ_F13M 85
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#define CLK_IFR_AES_TOP0_BCLK 86
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#define CLK_IFR_MCU_PM_BCLK 87
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#define CLK_IFR_CCIF2_AP 88
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#define CLK_IFR_CCIF2_MD 89
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#define CLK_IFR_CCIF3_AP 90
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#define CLK_IFR_CCIF3_MD 91
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#define CLK_IFR_PERI_DCM_RG_FORCE_CLKOFF 92
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#define CLK_IFR_NR_CLK 93
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/* PERICFG */
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#define CLK_PERIAXI_DISABLE 0
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#define CLK_PERI_NR_CLK 1
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/* GCE */
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#define CLK_GCE_FAXI 0
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#define CLK_GCE_NR_CLK 1
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/* AUDIO */
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#define CLK_AUDIO_AFE 0
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#define CLK_AUDIO_22M 1
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#define CLK_AUDIO_APLL_TUNER 2
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#define CLK_AUDIO_ADC 3
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#define CLK_AUDIO_DAC 4
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#define CLK_AUDIO_DAC_PREDIS 5
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#define CLK_AUDIO_TML 6
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#define CLK_AUDIO_I2S1_BCLK 7
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#define CLK_AUDIO_I2S2_BCLK 8
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#define CLK_AUDIO_I2S3_BCLK 9
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#define CLK_AUDIO_I2S4_BCLK 10
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#define CLK_AUDIO_NR_CLK 11
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/* MIPI_RX_ANA_CSI0A */
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#define CLK_MIPI0A_CSR_CSI_EN_0A 0
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#define CLK_MIPI0A_NR_CLK 1
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/* MIPI_RX_ANA_CSI0B */
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#define CLK_MIPI0B_CSR_CSI_EN_0B 0
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#define CLK_MIPI0B_NR_CLK 1
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/* MIPI_RX_ANA_CSI1A */
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#define CLK_MIPI1A_CSR_CSI_EN_1A 0
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#define CLK_MIPI1A_NR_CLK 1
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/* MIPI_RX_ANA_CSI1B */
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#define CLK_MIPI1B_CSR_CSI_EN_1B 0
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#define CLK_MIPI1B_NR_CLK 1
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/* MIPI_RX_ANA_CSI2A */
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#define CLK_MIPI2A_CSR_CSI_EN_2A 0
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#define CLK_MIPI2A_NR_CLK 1
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/* MIPI_RX_ANA_CSI2B */
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#define CLK_MIPI2B_CSR_CSI_EN_2B 0
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#define CLK_MIPI2B_NR_CLK 1
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/* MFG */
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#define CLK_MFGCFG_BAXI 0
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#define CLK_MFGCFG_BMEM 1
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#define CLK_MFGCFG_BG3D 2
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#define CLK_MFGCFG_B26M 3
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#define CLK_MFGCFG_NR_CLK 4
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/* MMSYS_CONFIG */
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#define CLK_MM_MDP_RDMA0 0
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#define CLK_MM_MDP_CCORR0 1
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#define CLK_MM_MDP_RSZ0 2
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#define CLK_MM_MDP_RSZ1 3
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#define CLK_MM_MDP_TDSHP0 4
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#define CLK_MM_MDP_WROT0 5
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#define CLK_MM_MDP_WDMA0 6
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#define CLK_MM_DISP_OVL0 7
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#define CLK_MM_DISP_OVL0_2L 8
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#define CLK_MM_DISP_RSZ0 9
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#define CLK_MM_DISP_RDMA0 10
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#define CLK_MM_DISP_WDMA0 11
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#define CLK_MM_DISP_COLOR0 12
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#define CLK_MM_DISP_CCORR0 13
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#define CLK_MM_DISP_AAL0 14
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#define CLK_MM_DISP_GAMMA0 15
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#define CLK_MM_DISP_DITHER0 16
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#define CLK_MM_DSI0 17
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#define CLK_MM_FAKE_ENG 18
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#define CLK_MM_SMI_COMMON 19
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#define CLK_MM_SMI_LARB0 20
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#define CLK_MM_SMI_COMM0 21
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#define CLK_MM_SMI_COMM1 22
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#define CLK_MM_CAM_MDP 23
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#define CLK_MM_SMI_IMG 24
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#define CLK_MM_SMI_CAM 25
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#define CLK_MM_IMG_DL_RELAY 26
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#define CLK_MM_IMG_DL_ASYNC_TOP 27
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#define CLK_MM_DIG_DSI 28
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#define CLK_MM_F26M_HRTWT 29
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#define CLK_MM_NR_CLK 30
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/* CAMSYS */
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#define CLK_CAM_LARB2 0
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#define CLK_CAM 1
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#define CLK_CAMTG 2
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#define CLK_CAM_SENINF 3
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#define CLK_CAMSV0 4
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#define CLK_CAMSV1 5
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#define CLK_CAM_FDVT 6
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#define CLK_CAM_NR_CLK 7
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/* VENCSYS */
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#define CLK_VENC_SET0_LARB 0
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#define CLK_VENC_SET1_VENC 1
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#define CLK_VENC_SET2_JPGENC 2
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#define CLK_VENC_SET3_VDEC 3
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#define CLK_VENC_NR_CLK 4
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/* SCP_SYS */
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#define SCP_SYS_MD1 0
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#define SCP_SYS_CONN 1
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#define SCP_SYS_DPY 2
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#define SCP_SYS_DIS 3
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#define SCP_SYS_MFG 4
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#define SCP_SYS_IFR 5
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#define SCP_SYS_MFG_CORE0 6
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#define SCP_SYS_MFG_ASYNC 7
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#define SCP_SYS_CAM 8
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#define SCP_SYS_VCODEC 9
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#define SCP_NR_SYSS 10
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#endif /* _DT_BINDINGS_CLK_MT6761_H */
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