319 lines
8.4 KiB
C
319 lines
8.4 KiB
C
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/*
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* Copyright (c) 2016, The OpenThread Authors.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the copyright holder nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* This file implements the OpenThread platform abstraction for UART communication.
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*
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*/
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#include <openthread-core-config.h>
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#include <openthread/config.h>
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#include <stdarg.h>
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#include <stddef.h>
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#include <stdio.h>
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#include <openthread/platform/debug_uart.h>
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#include <openthread/platform/logging.h>
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#include "platform-cc2538.h"
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#include "utils/code_utils.h"
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#include "utils/uart.h"
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enum
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{
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kPlatformClock = 32000000,
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kBaudRate = 115200,
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kReceiveBufferSize = 128,
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};
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extern void UART0IntHandler(void);
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static void processReceive(void);
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static void processTransmit(void);
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static const uint8_t *sTransmitBuffer = NULL;
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static uint16_t sTransmitLength = 0;
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typedef struct RecvBuffer
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{
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// The data buffer
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uint8_t mBuffer[kReceiveBufferSize];
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// The offset of the first item written to the list.
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uint16_t mHead;
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// The offset of the next item to be written to the list.
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uint16_t mTail;
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} RecvBuffer;
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static RecvBuffer sReceive;
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static void enable_uart_clocks(void)
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{
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static int uart_clocks_done = 0;
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if (uart_clocks_done)
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{
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return;
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}
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uart_clocks_done = 1;
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#if OPENTHREAD_CONFIG_ENABLE_DEBUG_UART
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HWREG(SYS_CTRL_RCGCUART) = (SYS_CTRL_RCGCUART_UART0 | SYS_CTRL_RCGCUART_UART1);
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HWREG(SYS_CTRL_SCGCUART) = (SYS_CTRL_SCGCUART_UART0 | SYS_CTRL_SCGCUART_UART1);
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HWREG(SYS_CTRL_DCGCUART) = (SYS_CTRL_DCGCUART_UART0 | SYS_CTRL_DCGCUART_UART1);
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#else
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HWREG(SYS_CTRL_RCGCUART) = SYS_CTRL_RCGCUART_UART0;
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HWREG(SYS_CTRL_SCGCUART) = SYS_CTRL_SCGCUART_UART0;
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HWREG(SYS_CTRL_DCGCUART) = SYS_CTRL_DCGCUART_UART0;
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#endif
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}
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otError otPlatUartEnable(void)
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{
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uint32_t div;
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sReceive.mHead = 0;
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sReceive.mTail = 0;
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// clock
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enable_uart_clocks();
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HWREG(UART0_BASE + UART_O_CC) = 0;
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// tx pin
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HWREG(IOC_PA1_SEL) = IOC_MUX_OUT_SEL_UART0_TXD;
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HWREG(IOC_PA1_OVER) = IOC_OVERRIDE_OE;
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HWREG(GPIO_A_BASE + GPIO_O_AFSEL) |= GPIO_PIN_1;
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// rx pin
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HWREG(IOC_UARTRXD_UART0) = IOC_PAD_IN_SEL_PA0;
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HWREG(IOC_PA0_OVER) = IOC_OVERRIDE_DIS;
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HWREG(GPIO_A_BASE + GPIO_O_AFSEL) |= GPIO_PIN_0;
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HWREG(UART0_BASE + UART_O_CTL) = 0;
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// baud rate
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div = (((kPlatformClock * 8) / kBaudRate) + 1) / 2;
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HWREG(UART0_BASE + UART_O_IBRD) = div / 64;
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HWREG(UART0_BASE + UART_O_FBRD) = div % 64;
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HWREG(UART0_BASE + UART_O_LCRH) = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE;
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// configure interrupts
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HWREG(UART0_BASE + UART_O_IM) |= UART_IM_RXIM | UART_IM_RTIM;
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// enable
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HWREG(UART0_BASE + UART_O_CTL) = UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE;
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// enable interrupts
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HWREG(NVIC_EN0) = 1 << ((INT_UART0 - 16) & 31);
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return OT_ERROR_NONE;
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}
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otError otPlatUartDisable(void)
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{
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return OT_ERROR_NONE;
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}
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otError otPlatUartSend(const uint8_t *aBuf, uint16_t aBufLength)
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{
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otError error = OT_ERROR_NONE;
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otEXPECT_ACTION(sTransmitBuffer == NULL, error = OT_ERROR_BUSY);
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sTransmitBuffer = aBuf;
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sTransmitLength = aBufLength;
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exit:
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return error;
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}
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void processReceive(void)
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{
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// Copy tail to prevent multiple reads
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uint16_t tail = sReceive.mTail;
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// If the data wraps around, process the first part
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if (sReceive.mHead > tail)
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{
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otPlatUartReceived(sReceive.mBuffer + sReceive.mHead, kReceiveBufferSize - sReceive.mHead);
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// Reset the buffer mHead back to zero.
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sReceive.mHead = 0;
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}
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// For any data remaining, process it
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if (sReceive.mHead != tail)
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{
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otPlatUartReceived(sReceive.mBuffer + sReceive.mHead, tail - sReceive.mHead);
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// Set mHead to the local tail we have cached
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sReceive.mHead = tail;
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}
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}
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otError otPlatUartFlush(void)
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{
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otEXPECT(sTransmitBuffer != NULL);
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for (; sTransmitLength > 0; sTransmitLength--)
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{
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while (HWREG(UART0_BASE + UART_O_FR) & UART_FR_TXFF)
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;
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HWREG(UART0_BASE + UART_O_DR) = *sTransmitBuffer++;
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}
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sTransmitBuffer = NULL;
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return OT_ERROR_NONE;
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exit:
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return OT_ERROR_INVALID_STATE;
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}
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void processTransmit(void)
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{
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otPlatUartFlush();
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otPlatUartSendDone();
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}
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void cc2538UartProcess(void)
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{
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processReceive();
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processTransmit();
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}
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void UART0IntHandler(void)
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{
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uint32_t mis;
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uint8_t byte;
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mis = HWREG(UART0_BASE + UART_O_MIS);
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HWREG(UART0_BASE + UART_O_ICR) = mis;
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if (mis & (UART_IM_RXIM | UART_IM_RTIM))
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{
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while (!(HWREG(UART0_BASE + UART_O_FR) & UART_FR_RXFE))
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{
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byte = HWREG(UART0_BASE + UART_O_DR);
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// We can only write if incrementing mTail doesn't equal mHead
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if (sReceive.mHead != (sReceive.mTail + 1) % kReceiveBufferSize)
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{
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sReceive.mBuffer[sReceive.mTail] = byte;
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sReceive.mTail = (sReceive.mTail + 1) % kReceiveBufferSize;
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}
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}
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}
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}
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#if OPENTHREAD_CONFIG_ENABLE_DEBUG_UART
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int otPlatDebugUart_kbhit(void)
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{
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uint32_t v;
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/* get flags */
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v = HWREG(UART1_BASE + UART_O_FR);
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/* if FIFO empty we have no data */
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return !(v & UART_FR_RXFE);
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}
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int otPlatDebugUart_getc(void)
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{
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int v = 1;
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/* if nothing in fifo */
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if (!otPlatDebugUart_kbhit())
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{
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return -1;
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}
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/* fetch */
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v = (int)HWREG(UART0_BASE + UART_O_DR);
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v = (v & 0x0ff);
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return v;
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}
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void otPlatDebugUart_putchar_raw(int b)
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{
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/* wait till not busy */
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while (HWREG(UART1_BASE + UART_O_FR) & UART_FR_TXFF)
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;
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/* write byte */
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HWREG(UART1_BASE + UART_O_DR) = ((uint32_t)(b & 0x0ff));
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}
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void cc2538DebugUartInit(void)
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{
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int32_t a, b;
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// clocks
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enable_uart_clocks();
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HWREG(UART1_BASE + UART_O_CC) = 0;
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// UART1 - tx pin
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// Using an RF06 Evaluation board
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// http://www.ti.com/tool/cc2538dk
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// PA3 => is jumper position RF1.14
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// To use these, you will require a "flying-lead" UART adapter
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HWREG(IOC_PA3_SEL) = IOC_MUX_OUT_SEL_UART1_TXD;
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HWREG(IOC_PA3_OVER) = IOC_OVERRIDE_OE;
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HWREG(GPIO_A_BASE + GPIO_O_AFSEL) |= GPIO_PIN_3;
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// UART1 - rx pin we don't really use but we setup anyway
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// PA2 => is jumper position RF1.16
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HWREG(IOC_UARTRXD_UART1) = IOC_PAD_IN_SEL_PA2;
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HWREG(IOC_PA2_OVER) = IOC_OVERRIDE_DIS;
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HWREG(GPIO_A_BASE + GPIO_O_AFSEL) |= GPIO_PIN_2;
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HWREG(UART1_BASE + UART_O_CC) = 0;
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// baud rate
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b = (((kPlatformClock * 8) / kBaudRate) + 1) / 2;
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a = b / 64;
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b = b % 64;
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HWREG(UART1_BASE + UART_O_IBRD) = a;
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HWREG(UART1_BASE + UART_O_FBRD) = b;
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HWREG(UART1_BASE + UART_O_LCRH) = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE;
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/* NOTE:
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* uart1 is not using IRQs it is tx only
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* and we block when writing bytes
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*/
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HWREG(UART1_BASE + UART_O_CTL) = UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE;
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}
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#endif
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