#ifndef CMDQ_EVENT_COMMON
#define CMDQ_EVENT_COMMON

/* Define CMDQ events
 *
 * For hardware event must define in device tree.
 * For SW event assign event ID here directly.
 *
 * Note: event name must sync to cmdq_events table in cmdq_event_common.c
 */
enum CMDQ_EVENT_ENUM {
	/* MDP start frame */
	CMDQ_EVENT_MDP_RDMA0_SOF = 0,
	CMDQ_EVENT_MDP_RDMA1_SOF,			/* 1 */
	CMDQ_EVENT_MDP_RSZ0_SOF,			/* 2 */
	CMDQ_EVENT_MDP_RSZ1_SOF,			/* 3 */
	CMDQ_EVENT_MDP_RSZ2_SOF,			/* 4 */
	CMDQ_EVENT_MDP_TDSHP_SOF,			/* 5 */
	CMDQ_EVENT_MDP_TDSHP0_SOF,			/* 6 */
	CMDQ_EVENT_MDP_TDSHP1_SOF,			/* 7 */
	CMDQ_EVENT_MDP_WDMA_SOF,			/* 8 */
	CMDQ_EVENT_MDP_WROT_SOF,			/* 9 */
	CMDQ_EVENT_MDP_WROT0_SOF,			/* 10 */
	CMDQ_EVENT_MDP_WROT1_SOF,			/* 11 */
	CMDQ_EVENT_MDP_COLOR_SOF,			/* 12 */
	CMDQ_EVENT_MDP_MVW_SOF,				/* 13 */
	CMDQ_EVENT_MDP_CROP_SOF,			/* 14 */

	/* Display start frame */
	CMDQ_EVENT_DISP_OVL0_SOF,			/* 15 */
	CMDQ_EVENT_DISP_OVL1_SOF,			/* 16 */
	CMDQ_EVENT_DISP_2L_OVL0_SOF,			/* 17 */
	CMDQ_EVENT_DISP_2L_OVL1_SOF,			/* 18 */
	CMDQ_EVENT_DISP_RDMA0_SOF,			/* 19 */
	CMDQ_EVENT_DISP_RDMA1_SOF,			/* 20 */
	CMDQ_EVENT_DISP_RDMA2_SOF,			/* 21 */
	CMDQ_EVENT_DISP_WDMA0_SOF,			/* 22 */
	CMDQ_EVENT_DISP_WDMA1_SOF,			/* 23 */
	CMDQ_EVENT_DISP_COLOR_SOF,			/* 24 */
	CMDQ_EVENT_DISP_COLOR0_SOF,			/* 25 */
	CMDQ_EVENT_DISP_COLOR1_SOF,			/* 26 */
	CMDQ_EVENT_DISP_CCORR_SOF,			/* 27 */
	CMDQ_EVENT_DISP_CCORR0_SOF,			/* 28 */
	CMDQ_EVENT_DISP_CCORR1_SOF,			/* 29 */
	CMDQ_EVENT_DISP_AAL_SOF,			/* 30 */
	CMDQ_EVENT_DISP_AAL0_SOF,			/* 31 */
	CMDQ_EVENT_DISP_AAL1_SOF,			/* 32 */
	CMDQ_EVENT_DISP_GAMMA_SOF,			/* 33 */
	CMDQ_EVENT_DISP_GAMMA0_SOF,			/* 34 */
	CMDQ_EVENT_DISP_GAMMA1_SOF,			/* 35 */
	CMDQ_EVENT_DISP_DITHER_SOF,			/* 36 */
	CMDQ_EVENT_DISP_DITHER0_SOF,			/* 37 */
	CMDQ_EVENT_DISP_DITHER1_SOF,			/* 38 */
	CMDQ_EVENT_DISP_UFOE_SOF,			/* 39 */
	CMDQ_EVENT_DISP_PWM0_SOF,			/* 40 */
	CMDQ_EVENT_DISP_PWM1_SOF,			/* 41 */
	CMDQ_EVENT_DISP_OD_SOF,				/* 42 */
	CMDQ_EVENT_DISP_DSC_SOF,			/* 43 */

	CMDQ_EVENT_UFOD_RAMA0_L0_SOF,			/* 44 */
	CMDQ_EVENT_UFOD_RAMA0_L1_SOF,			/* 45 */
	CMDQ_EVENT_UFOD_RAMA0_L2_SOF,			/* 46 */
	CMDQ_EVENT_UFOD_RAMA0_L3_SOF,			/* 47 */
	CMDQ_EVENT_UFOD_RAMA1_L0_SOF,			/* 48 */
	CMDQ_EVENT_UFOD_RAMA1_L1_SOF,			/* 49 */
	CMDQ_EVENT_UFOD_RAMA1_L2_SOF,			/* 50 */
	CMDQ_EVENT_UFOD_RAMA1_L3_SOF,			/* 51 */

	/* MDP frame done */
	CMDQ_EVENT_MDP_RDMA0_EOF,			/* 52 */
	CMDQ_EVENT_MDP_RDMA1_EOF,			/* 53 */
	CMDQ_EVENT_MDP_RSZ0_EOF,			/* 54 */
	CMDQ_EVENT_MDP_RSZ1_EOF,			/* 55 */
	CMDQ_EVENT_MDP_RSZ2_EOF,			/* 56 */
	CMDQ_EVENT_MDP_TDSHP_EOF,			/* 57 */
	CMDQ_EVENT_MDP_TDSHP0_EOF,			/* 58 */
	CMDQ_EVENT_MDP_TDSHP1_EOF,			/* 59 */
	CMDQ_EVENT_MDP_WDMA_EOF,			/* 60 */
	CMDQ_EVENT_MDP_WROT_WRITE_EOF,			/* 61 */
	CMDQ_EVENT_MDP_WROT_READ_EOF,			/* 62 */
	CMDQ_EVENT_MDP_WROT0_WRITE_EOF,			/* 63 */
	CMDQ_EVENT_MDP_WROT0_READ_EOF,			/* 64 */
	CMDQ_EVENT_MDP_WROT1_WRITE_EOF,			/* 65 */
	CMDQ_EVENT_MDP_WROT1_READ_EOF,			/* 66 */
	CMDQ_EVENT_MDP_WROT0_W_EOF,			/* 67 */
	CMDQ_EVENT_MDP_WROT0_R_EOF,			/* 68 */
	CMDQ_EVENT_MDP_WROT1_W_EOF,			/* 69 */
	CMDQ_EVENT_MDP_WROT1_R_EOF,			/* 70 */
	CMDQ_EVENT_MDP_COLOR_EOF,			/* 71 */
	CMDQ_EVENT_MDP_CROP_EOF,			/* 72 */

	/* Display frame done */
	CMDQ_EVENT_DISP_OVL0_EOF,			/* 73 */
	CMDQ_EVENT_DISP_OVL1_EOF,			/* 74 */
	CMDQ_EVENT_DISP_2L_OVL0_EOF,			/* 75 */
	CMDQ_EVENT_DISP_2L_OVL1_EOF,			/* 76 */
	CMDQ_EVENT_DISP_RDMA0_EOF,			/* 77 */
	CMDQ_EVENT_DISP_RDMA1_EOF,			/* 78 */
	CMDQ_EVENT_DISP_RDMA2_EOF,			/* 79 */
	CMDQ_EVENT_DISP_WDMA0_EOF,			/* 80 */
	CMDQ_EVENT_DISP_WDMA1_EOF,			/* 81 */
	CMDQ_EVENT_DISP_COLOR_EOF,			/* 82 */
	CMDQ_EVENT_DISP_COLOR0_EOF,			/* 83 */
	CMDQ_EVENT_DISP_COLOR1_EOF,			/* 84 */
	CMDQ_EVENT_DISP_CCORR_EOF,			/* 85 */
	CMDQ_EVENT_DISP_CCORR0_EOF,			/* 86 */
	CMDQ_EVENT_DISP_CCORR1_EOF,			/* 87 */
	CMDQ_EVENT_DISP_AAL_EOF,			/* 88 */
	CMDQ_EVENT_DISP_AAL0_EOF,			/* 89 */
	CMDQ_EVENT_DISP_AAL1_EOF,			/* 90 */
	CMDQ_EVENT_DISP_GAMMA_EOF,			/* 91 */
	CMDQ_EVENT_DISP_GAMMA0_EOF,			/* 92 */
	CMDQ_EVENT_DISP_GAMMA1_EOF,			/* 93 */
	CMDQ_EVENT_DISP_DITHER_EOF,			/* 94 */
	CMDQ_EVENT_DISP_DITHER0_EOF,			/* 95 */
	CMDQ_EVENT_DISP_DITHER1_EOF,			/* 96 */
	CMDQ_EVENT_DISP_UFOE_EOF,			/* 97 */
	CMDQ_EVENT_DISP_OD_EOF,				/* 98 */
	CMDQ_EVENT_DISP_OD_RDMA_EOF,			/* 99 */
	CMDQ_EVENT_DISP_OD_WDMA_EOF,			/* 100 */
	CMDQ_EVENT_DISP_DSC_EOF,			/* 101 */
	CMDQ_EVENT_DISP_DSI0_EOF,			/* 102 */
	CMDQ_EVENT_DISP_DSI1_EOF,			/* 103 */
	CMDQ_EVENT_DISP_DPI0_EOF,			/* 104 */

	CMDQ_EVENT_UFOD_RAMA0_L0_EOF,			/* 105 */
	CMDQ_EVENT_UFOD_RAMA0_L1_EOF,			/* 106 */
	CMDQ_EVENT_UFOD_RAMA0_L2_EOF,			/* 107 */
	CMDQ_EVENT_UFOD_RAMA0_L3_EOF,			/* 108 */
	CMDQ_EVENT_UFOD_RAMA1_L0_EOF,			/* 109 */
	CMDQ_EVENT_UFOD_RAMA1_L1_EOF,			/* 110 */
	CMDQ_EVENT_UFOD_RAMA1_L2_EOF,			/* 111 */
	CMDQ_EVENT_UFOD_RAMA1_L3_EOF,			/* 112 */

	/* Mutex frame done */
	/* DISPSYS */
	CMDQ_EVENT_MUTEX0_STREAM_EOF,			/* 113 */
	/* DISPSYS */
	CMDQ_EVENT_MUTEX1_STREAM_EOF,			/* 114 */
	/* DISPSYS */
	CMDQ_EVENT_MUTEX2_STREAM_EOF,			/* 115 */
	/* DISPSYS */
	CMDQ_EVENT_MUTEX3_STREAM_EOF,			/* 116 */
	/* DISPSYS, please refer to disp_hal.h */
	CMDQ_EVENT_MUTEX4_STREAM_EOF,			/* 117 */
	/* DpFramework */
	CMDQ_EVENT_MUTEX5_STREAM_EOF,			/* 118 */
	/* DpFramework */
	CMDQ_EVENT_MUTEX6_STREAM_EOF,			/* 119 */
	/* DpFramework */
	CMDQ_EVENT_MUTEX7_STREAM_EOF,			/* 120 */
	/* DpFramework */
	CMDQ_EVENT_MUTEX8_STREAM_EOF,			/* 121 */
	/* DpFramework via CMDQ_IOCTL_LOCK_MUTEX */
	CMDQ_EVENT_MUTEX9_STREAM_EOF,			/* 122 */
	CMDQ_EVENT_MUTEX10_STREAM_EOF,			/* 123 */
	CMDQ_EVENT_MUTEX11_STREAM_EOF,			/* 124 */
	CMDQ_EVENT_MUTEX12_STREAM_EOF,			/* 125 */
	CMDQ_EVENT_MUTEX13_STREAM_EOF,			/* 126 */
	CMDQ_EVENT_MUTEX14_STREAM_EOF,			/* 127 */
	CMDQ_EVENT_MUTEX15_STREAM_EOF,			/* 128 */

	/* Display underrun */
	CMDQ_EVENT_DISP_RDMA0_UNDERRUN,			/* 129 */
	CMDQ_EVENT_DISP_RDMA1_UNDERRUN,			/* 130 */
	CMDQ_EVENT_DISP_RDMA2_UNDERRUN,			/* 131 */

	/* Display TE */
	CMDQ_EVENT_DSI_TE,				/* 132 */
	CMDQ_EVENT_DSI0_TE,				/* 133 */
	CMDQ_EVENT_DSI1_TE,				/* 134 */
	CMDQ_EVENT_MDP_DSI0_TE_SOF,			/* 135 */
	CMDQ_EVENT_MDP_DSI1_TE_SOF,			/* 136 */
	CMDQ_EVENT_DISP_DSI0_SOF,			/* 137 */
	CMDQ_EVENT_DISP_DSI1_SOF,			/* 138 */
	CMDQ_EVENT_DSI0_TO_GCE_MMCK0,			/* 139 */
	CMDQ_EVENT_DSI0_TO_GCE_MMCK1,			/* 140 */
	CMDQ_EVENT_DSI0_TO_GCE_MMCK2,			/* 141 */
	CMDQ_EVENT_DSI0_TO_GCE_MMCK3,			/* 142 */
	CMDQ_EVENT_DSI0_TO_GCE_MMCK4,			/* 143 */
	CMDQ_EVENT_DSI1_TO_GCE_MMCK0,			/* 144 */
	CMDQ_EVENT_DSI1_TO_GCE_MMCK1,			/* 145 */
	CMDQ_EVENT_DSI1_TO_GCE_MMCK2,			/* 146 */
	CMDQ_EVENT_DSI1_TO_GCE_MMCK3,			/* 147 */
	CMDQ_EVENT_DSI1_TO_GCE_MMCK4,			/* 148 */

	/* Reset Event */
	CMDQ_EVENT_DISP_WDMA0_RST_DONE,			/* 149 */
	CMDQ_EVENT_DISP_WDMA1_RST_DONE,			/* 150 */
	CMDQ_EVENT_MDP_WROT0_RST_DONE,			/* 151 */
	CMDQ_EVENT_MDP_WROT1_RST_DONE,			/* 152 */
	CMDQ_EVENT_MDP_WDMA_RST_DONE,			/* 153 */
	CMDQ_EVENT_MDP_RDMA0_RST_DONE,			/* 154 */
	CMDQ_EVENT_MDP_RDMA1_RST_DONE,			/* 155 */

	/* Display Mutex */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD0,		/* 156 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD1,		/* 157 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD2,		/* 158 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD3,		/* 159 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD4,		/* 160 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD5,		/* 161 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD6,		/* 162 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD7,		/* 163 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD8,		/* 164 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD9,		/* 165 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD10,		/* 166 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD11,		/* 167 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD12,		/* 168 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD13,		/* 169 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD14,		/* 170 */
	CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD15,		/* 171 */

	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE0,	/* 172 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE1,	/* 173 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE2,	/* 174 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE3,	/* 175 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE4,	/* 176 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE5,	/* 177 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE6,	/* 178 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE7,	/* 179 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE8,	/* 180 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE9,	/* 181 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE10,	/* 182 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE11,	/* 183 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE12,	/* 184 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE13,	/* 185 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE14,	/* 186 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE15,	/* 187 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE16,	/* 188 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE17,	/* 189 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE18,	/* 190 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE19,	/* 191 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE20,	/* 192 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE21,	/* 193 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE22,	/* 194 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE23,	/* 195 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE24,	/* 196 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE25,	/* 197 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE26,	/* 198 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE27,	/* 199 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE28,	/* 200 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE29,	/* 201 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE30,	/* 202 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE31,	/* 203 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE32,	/* 204 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE33,	/* 205 */
	CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE34,	/* 206 */

	/* ISP frame done */
	CMDQ_EVENT_ISP_PASS2_2_EOF,			/* 207 */
	CMDQ_EVENT_ISP_PASS2_1_EOF,			/* 208 */
	CMDQ_EVENT_ISP_PASS2_0_EOF,			/* 209 */
	CMDQ_EVENT_ISP_PASS1_1_EOF,			/* 210 */
	CMDQ_EVENT_ISP_PASS1_0_EOF,			/* 211 */

	/* ISP (IMGSYS) frame done */
	CMDQ_EVENT_DIP_CQ_THREAD0_EOF,			/* 212 */
	CMDQ_EVENT_DIP_CQ_THREAD1_EOF,			/* 213 */
	CMDQ_EVENT_DIP_CQ_THREAD2_EOF,			/* 214 */
	CMDQ_EVENT_DIP_CQ_THREAD3_EOF,			/* 215 */
	CMDQ_EVENT_DIP_CQ_THREAD4_EOF,			/* 216 */
	CMDQ_EVENT_DIP_CQ_THREAD5_EOF,			/* 217 */
	CMDQ_EVENT_DIP_CQ_THREAD6_EOF,			/* 218 */
	CMDQ_EVENT_DIP_CQ_THREAD7_EOF,			/* 219 */
	CMDQ_EVENT_DIP_CQ_THREAD8_EOF,			/* 220 */
	CMDQ_EVENT_DIP_CQ_THREAD9_EOF,			/* 221 */
	CMDQ_EVENT_DIP_CQ_THREAD10_EOF,			/* 222 */
	CMDQ_EVENT_DIP_CQ_THREAD11_EOF,			/* 223 */
	CMDQ_EVENT_DIP_CQ_THREAD12_EOF,			/* 224 */
	CMDQ_EVENT_DIP_CQ_THREAD13_EOF,			/* 225 */
	CMDQ_EVENT_DIP_CQ_THREAD14_EOF,			/* 226 */
	CMDQ_EVENT_DPE_EOF,				/* 227 */
	CMDQ_EVENT_DVE_EOF,				/* 228 */
	CMDQ_EVENT_WMF_EOF,				/* 229 */
	CMDQ_EVENT_GEPF_EOF,				/* 230 */
	CMDQ_EVENT_GEPF_TEMP_EOF,			/* 231 */
	CMDQ_EVENT_GEPF_BYPASS_EOF,			/* 232 */
	CMDQ_EVENT_RSC_EOF,				/* 233 */

	/* ISP (IMGSYS) engine events */
	CMDQ_EVENT_ISP_SENINF_CAM1_2_3_FULL,		/* 234 */
	CMDQ_EVENT_ISP_SENINF_CAM0_FULL,		/* 235 */

	/* VENC frame done */
	CMDQ_EVENT_VENC_EOF,				/* 236 */

	/* JPEG frame done */
	CMDQ_EVENT_JPEG_ENC_EOF,			/* 237 */
	CMDQ_EVENT_JPEG_ENC_PASS2_EOF,			/* 238 */
	CMDQ_EVENT_JPEG_ENC_PASS1_EOF,			/* 239 */
	CMDQ_EVENT_JPEG_DEC_EOF,			/* 240 */

	/* VENC engine events */
	CMDQ_EVENT_VENC_MB_DONE,			/* 241 */
	CMDQ_EVENT_VENC_128BYTE_CNT_DONE,		/* 242 */

	/* ISP (CAMSYS) frame done */
	CMDQ_EVENT_ISP_FRAME_DONE_A,			/* 243 */
	CMDQ_EVENT_ISP_FRAME_DONE_B,			/* 244 */
	CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE,		/* 245 */
	CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE,		/* 246 */
	CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE,		/* 247 */
	CMDQ_EVENT_ISP_TSF_DONE,			/* 248 */

	/* ISP (CAMSYS) engine events */
	CMDQ_EVENT_SENINF_0_FIFO_FULL,			/* 249 */
	CMDQ_EVENT_SENINF_1_FIFO_FULL,			/* 250 */
	CMDQ_EVENT_SENINF_2_FIFO_FULL,			/* 251 */
	CMDQ_EVENT_SENINF_3_FIFO_FULL,			/* 252 */
	CMDQ_EVENT_SENINF_4_FIFO_FULL,			/* 253 */
	CMDQ_EVENT_SENINF_5_FIFO_FULL,			/* 254 */
	CMDQ_EVENT_SENINF_6_FIFO_FULL,			/* 255 */
	CMDQ_EVENT_SENINF_7_FIFO_FULL,			/* 256 */

	/* DPI1 frame done */
	CMDQ_EVENT_DISP_DPI1_EOF,			/* 257 */

	/* Keep this at the end of HW events */
	CMDQ_MAX_HW_EVENT_COUNT = 400,

	/* SW Sync Tokens (Pre-defined) */
	/* Config thread notify trigger thread */
	CMDQ_SYNC_TOKEN_CONFIG_DIRTY = 401,
	/* Trigger thread notify config thread */
	CMDQ_SYNC_TOKEN_STREAM_EOF = 402,
	/* Block Trigger thread until the ESD check finishes. */
	CMDQ_SYNC_TOKEN_ESD_EOF = 403,
	/* check CABC setup finish */
	CMDQ_SYNC_TOKEN_CABC_EOF = 404,
	/* Block Trigger thread until the path freeze finishes */
	CMDQ_SYNC_TOKEN_FREEZE_EOF = 405,
	/* Pass-2 notifies VENC frame is ready to be encoded */
	CMDQ_SYNC_TOKEN_VENC_INPUT_READY = 406,
	/* VENC notifies Pass-2 encode done so next frame may start */
	CMDQ_SYNC_TOKEN_VENC_EOF = 407,

	/* Notify normal CMDQ there are some secure task done */
	CMDQ_SYNC_SECURE_THR_EOF = 408,
	/* Lock WSM resource */
	CMDQ_SYNC_SECURE_WSM_LOCK = 409,

	/* SW Sync Tokens (User-defined) */
	CMDQ_SYNC_TOKEN_USER_0 = 410,
	CMDQ_SYNC_TOKEN_USER_1 = 411,
	CMDQ_SYNC_TOKEN_POLL_MONITOR = 412,

	/* Secure video path notify SW token */
	CMDQ_SYNC_DISP_OVL0_2NONSEC_END = 420,
	CMDQ_SYNC_DISP_OVL1_2NONSEC_END = 421,
	CMDQ_SYNC_DISP_2LOVL0_2NONSEC_END = 422,
	CMDQ_SYNC_DISP_2LOVL1_2NONSEC_END = 423,
	CMDQ_SYNC_DISP_RDMA0_2NONSEC_END = 424,
	CMDQ_SYNC_DISP_RDMA1_2NONSEC_END = 425,
	CMDQ_SYNC_DISP_WDMA0_2NONSEC_END = 426,
	CMDQ_SYNC_DISP_WDMA1_2NONSEC_END = 427,
	CMDQ_SYNC_DISP_EXT_STREAM_EOF = 428,

	/* Event for CMDQ to block executing command when append command
	 * Plz sync CMDQ_SYNC_TOKEN_APPEND_THR(id) in cmdq_core source file.
	 */
	CMDQ_SYNC_TOKEN_APPEND_THR0 = 432,
	CMDQ_SYNC_TOKEN_APPEND_THR1 = 433,
	CMDQ_SYNC_TOKEN_APPEND_THR2 = 434,
	CMDQ_SYNC_TOKEN_APPEND_THR3 = 435,
	CMDQ_SYNC_TOKEN_APPEND_THR4 = 436,
	CMDQ_SYNC_TOKEN_APPEND_THR5 = 437,
	CMDQ_SYNC_TOKEN_APPEND_THR6 = 438,
	CMDQ_SYNC_TOKEN_APPEND_THR7 = 439,
	CMDQ_SYNC_TOKEN_APPEND_THR8 = 440,
	CMDQ_SYNC_TOKEN_APPEND_THR9 = 441,
	CMDQ_SYNC_TOKEN_APPEND_THR10 = 442,
	CMDQ_SYNC_TOKEN_APPEND_THR11 = 443,
	CMDQ_SYNC_TOKEN_APPEND_THR12 = 444,
	CMDQ_SYNC_TOKEN_APPEND_THR13 = 445,
	CMDQ_SYNC_TOKEN_APPEND_THR14 = 446,
	CMDQ_SYNC_TOKEN_APPEND_THR15 = 447,

	/* GPR access tokens (for HW register backup) */
	/* There are 15 32-bit GPR, 3 GPR form a set (64-bit for address, 32-bit for
	 * value)
	 */
	CMDQ_SYNC_TOKEN_GPR_SET_0 = 450,
	CMDQ_SYNC_TOKEN_GPR_SET_1 = 451,
	CMDQ_SYNC_TOKEN_GPR_SET_2 = 452,
	CMDQ_SYNC_TOKEN_GPR_SET_3 = 453,
	CMDQ_SYNC_TOKEN_GPR_SET_4 = 454,

	/* Resource lock event to control resource in GCE thread */
	CMDQ_SYNC_RESOURCE_WROT0 = 460,
	CMDQ_SYNC_RESOURCE_WROT1 = 461,

	/* Event for CMDQ delay implement
	 * Plz sync CMDQ_SYNC_TOKEN_DELAY_THR(id) in cmdq_core source file.
	 */
	CMDQ_SYNC_TOKEN_DELAY_THR0 = 470,
	CMDQ_SYNC_TOKEN_DELAY_THR1 = 471,
	CMDQ_SYNC_TOKEN_DELAY_THR2 = 472,
	CMDQ_SYNC_TOKEN_DELAY_THR3 = 473,
	CMDQ_SYNC_TOKEN_DELAY_THR4 = 474,
	CMDQ_SYNC_TOKEN_DELAY_THR5 = 475,
	CMDQ_SYNC_TOKEN_DELAY_THR6 = 476,
	CMDQ_SYNC_TOKEN_DELAY_THR7 = 477,
	CMDQ_SYNC_TOKEN_DELAY_THR8 = 478,
	CMDQ_SYNC_TOKEN_DELAY_THR9 = 479,
	CMDQ_SYNC_TOKEN_DELAY_THR10 = 480,
	CMDQ_SYNC_TOKEN_DELAY_THR11 = 481,
	CMDQ_SYNC_TOKEN_DELAY_THR12 = 482,
	CMDQ_SYNC_TOKEN_DELAY_THR13 = 483,
	CMDQ_SYNC_TOKEN_DELAY_THR14 = 484,
	CMDQ_SYNC_TOKEN_DELAY_THR15 = 485,
	CMDQ_SYNC_TOKEN_DELAY_THR16 = 486,
	CMDQ_SYNC_TOKEN_DELAY_THR17 = 487,
	CMDQ_SYNC_TOKEN_DELAY_THR18 = 488,
	CMDQ_SYNC_TOKEN_DELAY_THR19 = 489,
	CMDQ_SYNC_TOKEN_DELAY_THR20 = 490,
	CMDQ_SYNC_TOKEN_DELAY_THR21 = 491,
	CMDQ_SYNC_TOKEN_DELAY_THR22 = 492,
	CMDQ_SYNC_TOKEN_DELAY_THR23 = 493,
	CMDQ_SYNC_TOKEN_DELAY_THR24 = 494,
	CMDQ_SYNC_TOKEN_DELAY_THR25 = 495,
	CMDQ_SYNC_TOKEN_DELAY_THR26 = 496,
	CMDQ_SYNC_TOKEN_DELAY_THR27 = 497,
	CMDQ_SYNC_TOKEN_DELAY_THR28 = 498,
	CMDQ_SYNC_TOKEN_DELAY_THR29 = 499,
	CMDQ_SYNC_TOKEN_DELAY_THR30 = 500,
	CMDQ_SYNC_TOKEN_DELAY_THR31 = 501,
	CMDQ_SYNC_TOKEN_TIMER = 502,

	/* event id is 9 bit */
	CMDQ_SYNC_TOKEN_MAX = 0x1FF,
	CMDQ_SYNC_TOKEN_INVALID = -1,
};

#endif