/****************************************************************************
 ****************************************************************************
 ***
 ***   This header was automatically generated from a Linux kernel header
 ***   of the same name, to make information necessary for userspace to
 ***   call into the kernel available to libc.  It contains only constants,
 ***   structures, and macros generated from the original header, and thus,
 ***   contains no copyrightable information.
 ***
 ***   To edit the content of this header, modify the corresponding
 ***   source file (e.g. under external/kernel-headers/original/) then
 ***   run bionic/libc/kernel/tools/update_all.py
 ***
 ***   Any manual change here will be lost the next time this script will
 ***   be run. You've been warned!
 ***
 ****************************************************************************
 ****************************************************************************/
#ifndef CMDQ_EVENT_COMMON
#define CMDQ_EVENT_COMMON
enum cmdq_event {
  CMDQ_EVENT_MDP_RDMA0_SOF,
  CMDQ_EVENT_MDP_RDMA1_SOF,
  CMDQ_EVENT_MDP_RSZ0_SOF,
  CMDQ_EVENT_MDP_RSZ1_SOF,
  CMDQ_EVENT_MDP_RSZ2_SOF,
  CMDQ_EVENT_MDP_TDSHP_SOF,
  CMDQ_EVENT_MDP_TDSHP0_SOF,
  CMDQ_EVENT_MDP_TDSHP1_SOF,
  CMDQ_EVENT_MDP_WDMA_SOF,
  CMDQ_EVENT_MDP_WROT_SOF,
  CMDQ_EVENT_MDP_WROT0_SOF,
  CMDQ_EVENT_MDP_WROT1_SOF,
  CMDQ_EVENT_MDP_COLOR_SOF,
  CMDQ_EVENT_MDP_MVW_SOF,
  CMDQ_EVENT_MDP_CROP_SOF,
  CMDQ_EVENT_MDP_AAL_SOF,
  CMDQ_EVENT_DISP_OVL0_SOF,
  CMDQ_EVENT_DISP_OVL1_SOF,
  CMDQ_EVENT_DISP_2L_OVL0_SOF,
  CMDQ_EVENT_DISP_2L_OVL1_SOF,
  CMDQ_EVENT_DISP_RDMA0_SOF,
  CMDQ_EVENT_DISP_RDMA1_SOF,
  CMDQ_EVENT_DISP_RDMA2_SOF,
  CMDQ_EVENT_DISP_WDMA0_SOF,
  CMDQ_EVENT_DISP_WDMA1_SOF,
  CMDQ_EVENT_DISP_COLOR_SOF,
  CMDQ_EVENT_DISP_COLOR0_SOF,
  CMDQ_EVENT_DISP_COLOR1_SOF,
  CMDQ_EVENT_DISP_CCORR_SOF,
  CMDQ_EVENT_DISP_CCORR0_SOF,
  CMDQ_EVENT_DISP_CCORR1_SOF,
  CMDQ_EVENT_DISP_AAL_SOF,
  CMDQ_EVENT_DISP_AAL0_SOF,
  CMDQ_EVENT_DISP_AAL1_SOF,
  CMDQ_EVENT_DISP_GAMMA_SOF,
  CMDQ_EVENT_DISP_GAMMA0_SOF,
  CMDQ_EVENT_DISP_GAMMA1_SOF,
  CMDQ_EVENT_DISP_DITHER_SOF,
  CMDQ_EVENT_DISP_DITHER0_SOF,
  CMDQ_EVENT_DISP_DITHER1_SOF,
  CMDQ_EVENT_DISP_UFOE_SOF,
  CMDQ_EVENT_DISP_PWM0_SOF,
  CMDQ_EVENT_DISP_PWM1_SOF,
  CMDQ_EVENT_DISP_OD_SOF,
  CMDQ_EVENT_DISP_DSC_SOF,
  CMDQ_EVENT_UFOD_RAMA0_L0_SOF,
  CMDQ_EVENT_UFOD_RAMA0_L1_SOF,
  CMDQ_EVENT_UFOD_RAMA0_L2_SOF,
  CMDQ_EVENT_UFOD_RAMA0_L3_SOF,
  CMDQ_EVENT_UFOD_RAMA1_L0_SOF,
  CMDQ_EVENT_UFOD_RAMA1_L1_SOF,
  CMDQ_EVENT_UFOD_RAMA1_L2_SOF,
  CMDQ_EVENT_UFOD_RAMA1_L3_SOF,
  CMDQ_EVENT_MDP_RDMA0_EOF,
  CMDQ_EVENT_MDP_RDMA1_EOF,
  CMDQ_EVENT_MDP_RSZ0_EOF,
  CMDQ_EVENT_MDP_RSZ1_EOF,
  CMDQ_EVENT_MDP_RSZ2_EOF,
  CMDQ_EVENT_MDP_TDSHP_EOF,
  CMDQ_EVENT_MDP_TDSHP0_EOF,
  CMDQ_EVENT_MDP_TDSHP1_EOF,
  CMDQ_EVENT_MDP_WDMA_EOF,
  CMDQ_EVENT_MDP_WROT_WRITE_EOF,
  CMDQ_EVENT_MDP_WROT_READ_EOF,
  CMDQ_EVENT_MDP_WROT0_WRITE_EOF,
  CMDQ_EVENT_MDP_WROT0_READ_EOF,
  CMDQ_EVENT_MDP_WROT1_WRITE_EOF,
  CMDQ_EVENT_MDP_WROT1_READ_EOF,
  CMDQ_EVENT_MDP_WROT0_W_EOF,
  CMDQ_EVENT_MDP_WROT0_R_EOF,
  CMDQ_EVENT_MDP_WROT1_W_EOF,
  CMDQ_EVENT_MDP_WROT1_R_EOF,
  CMDQ_EVENT_MDP_COLOR_EOF,
  CMDQ_EVENT_MDP_CROP_EOF,
  CMDQ_EVENT_DISP_OVL0_EOF,
  CMDQ_EVENT_DISP_OVL1_EOF,
  CMDQ_EVENT_DISP_2L_OVL0_EOF,
  CMDQ_EVENT_DISP_2L_OVL1_EOF,
  CMDQ_EVENT_DISP_RDMA0_EOF,
  CMDQ_EVENT_DISP_RDMA1_EOF,
  CMDQ_EVENT_DISP_RDMA2_EOF,
  CMDQ_EVENT_DISP_WDMA0_EOF,
  CMDQ_EVENT_DISP_WDMA1_EOF,
  CMDQ_EVENT_DISP_COLOR_EOF,
  CMDQ_EVENT_DISP_COLOR0_EOF,
  CMDQ_EVENT_DISP_COLOR1_EOF,
  CMDQ_EVENT_DISP_CCORR_EOF,
  CMDQ_EVENT_DISP_CCORR0_EOF,
  CMDQ_EVENT_DISP_CCORR1_EOF,
  CMDQ_EVENT_DISP_AAL_EOF,
  CMDQ_EVENT_DISP_AAL0_EOF,
  CMDQ_EVENT_DISP_AAL1_EOF,
  CMDQ_EVENT_DISP_GAMMA_EOF,
  CMDQ_EVENT_DISP_GAMMA0_EOF,
  CMDQ_EVENT_DISP_GAMMA1_EOF,
  CMDQ_EVENT_DISP_DITHER_EOF,
  CMDQ_EVENT_DISP_DITHER0_EOF,
  CMDQ_EVENT_DISP_DITHER1_EOF,
  CMDQ_EVENT_DISP_UFOE_EOF,
  CMDQ_EVENT_DISP_OD_EOF,
  CMDQ_EVENT_DISP_OD_RDMA_EOF,
  CMDQ_EVENT_DISP_OD_WDMA_EOF,
  CMDQ_EVENT_DISP_DSC_EOF,
  CMDQ_EVENT_DISP_DSI0_EOF,
  CMDQ_EVENT_DISP_DSI1_EOF,
  CMDQ_EVENT_DISP_DPI0_EOF,
  CMDQ_EVENT_UFOD_RAMA0_L0_EOF,
  CMDQ_EVENT_UFOD_RAMA0_L1_EOF,
  CMDQ_EVENT_UFOD_RAMA0_L2_EOF,
  CMDQ_EVENT_UFOD_RAMA0_L3_EOF,
  CMDQ_EVENT_UFOD_RAMA1_L0_EOF,
  CMDQ_EVENT_UFOD_RAMA1_L1_EOF,
  CMDQ_EVENT_UFOD_RAMA1_L2_EOF,
  CMDQ_EVENT_UFOD_RAMA1_L3_EOF,
  CMDQ_EVENT_DISP_POSTMASK0_SOF,
  CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE,
  CMDQ_EVENT_DISP_POSTMASK0_FRAME_RST_DONE_PULSE,
  CMDQ_EVENT_MUTEX0_STREAM_EOF,
  CMDQ_EVENT_MUTEX1_STREAM_EOF,
  CMDQ_EVENT_MUTEX2_STREAM_EOF,
  CMDQ_EVENT_MUTEX3_STREAM_EOF,
  CMDQ_EVENT_MUTEX4_STREAM_EOF,
  CMDQ_EVENT_MUTEX5_STREAM_EOF,
  CMDQ_EVENT_MUTEX6_STREAM_EOF,
  CMDQ_EVENT_MUTEX7_STREAM_EOF,
  CMDQ_EVENT_MUTEX8_STREAM_EOF,
  CMDQ_EVENT_MUTEX9_STREAM_EOF,
  CMDQ_EVENT_MUTEX10_STREAM_EOF,
  CMDQ_EVENT_MUTEX11_STREAM_EOF,
  CMDQ_EVENT_MUTEX12_STREAM_EOF,
  CMDQ_EVENT_MUTEX13_STREAM_EOF,
  CMDQ_EVENT_MUTEX14_STREAM_EOF,
  CMDQ_EVENT_MUTEX15_STREAM_EOF,
  CMDQ_EVENT_DISP_RDMA0_UNDERRUN,
  CMDQ_EVENT_DISP_RDMA1_UNDERRUN,
  CMDQ_EVENT_DISP_RDMA2_UNDERRUN,
  CMDQ_EVENT_DISP_RDMA3_UNDERRUN,
  CMDQ_EVENT_DSI_TE,
  CMDQ_EVENT_DSI0_TE,
  CMDQ_EVENT_DSI1_TE,
  CMDQ_EVENT_MDP_DSI0_TE_SOF,
  CMDQ_EVENT_MDP_DSI1_TE_SOF,
  CMDQ_EVENT_DISP_DSI0_SOF,
  CMDQ_EVENT_DISP_DSI1_SOF,
  CMDQ_EVENT_DSI0_TO_GCE_MMCK0,
  CMDQ_EVENT_DSI0_TO_GCE_MMCK1,
  CMDQ_EVENT_DSI0_TO_GCE_MMCK2,
  CMDQ_EVENT_DSI0_TO_GCE_MMCK3,
  CMDQ_EVENT_DSI0_TO_GCE_MMCK4,
  CMDQ_EVENT_DSI1_TO_GCE_MMCK0,
  CMDQ_EVENT_DSI1_TO_GCE_MMCK1,
  CMDQ_EVENT_DSI1_TO_GCE_MMCK2,
  CMDQ_EVENT_DSI1_TO_GCE_MMCK3,
  CMDQ_EVENT_DSI1_TO_GCE_MMCK4,
  CMDQ_EVENT_DSI0_IRQ_EVENT,
  CMDQ_EVENT_DSI0_DONE_EVENT,
  CMDQ_EVENT_DSI1_IRQ_EVENT,
  CMDQ_EVENT_DSI1_DONE_EVENT,
  CMDQ_EVENT_DISP_WDMA0_RST_DONE,
  CMDQ_EVENT_DISP_WDMA1_RST_DONE,
  CMDQ_EVENT_MDP_WROT0_RST_DONE,
  CMDQ_EVENT_MDP_WROT1_RST_DONE,
  CMDQ_EVENT_MDP_WDMA_RST_DONE,
  CMDQ_EVENT_MDP_RDMA0_RST_DONE,
  CMDQ_EVENT_MDP_RDMA1_RST_DONE,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD0,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD1,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD2,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD3,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD4,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD5,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD6,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD7,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD8,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD9,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD10,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD11,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD12,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD13,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD14,
  CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD15,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE0,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE1,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE2,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE3,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE4,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE5,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE6,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE7,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE8,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE9,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE10,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE11,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE12,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE13,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE14,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE15,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE16,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE17,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE18,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE19,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE20,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE21,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE22,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE23,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE24,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE25,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE26,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE27,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE28,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE29,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE30,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE31,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE32,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE33,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE34,
  CMDQ_EVENT_ISP_PASS2_2_EOF,
  CMDQ_EVENT_ISP_PASS2_1_EOF,
  CMDQ_EVENT_ISP_PASS2_0_EOF,
  CMDQ_EVENT_ISP_PASS1_1_EOF,
  CMDQ_EVENT_ISP_PASS1_0_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD0_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD1_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD2_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD3_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD4_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD5_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD6_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD7_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD8_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD9_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD10_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD11_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD12_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD13_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD14_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD15_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD16_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD17_EOF,
  CMDQ_EVENT_DIP_CQ_THREAD18_EOF,
  CMDQ_EVENT_DPE_EOF,
  CMDQ_EVENT_DVE_EOF,
  CMDQ_EVENT_WMF_EOF,
  CMDQ_EVENT_GEPF_EOF,
  CMDQ_EVENT_GEPF_TEMP_EOF,
  CMDQ_EVENT_GEPF_BYPASS_EOF,
  CMDQ_EVENT_RSC_EOF,
  CMDQ_EVENT_DIP_DMA_ERR_EVENT,
  CMDQ_EVENT_ISP_SENINF_CAM1_2_3_FULL,
  CMDQ_EVENT_ISP_SENINF_CAM0_FULL,
  CMDQ_EVENT_VENC_EOF,
  CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE,
  CMDQ_EVENT_JPEG_ENC_EOF,
  CMDQ_EVENT_JPEG_ENC_PASS2_EOF,
  CMDQ_EVENT_JPEG_ENC_PASS1_EOF,
  CMDQ_EVENT_JPEG_DEC_EOF,
  CMDQ_EVENT_VENC_MB_DONE,
  CMDQ_EVENT_VENC_128BYTE_CNT_DONE,
  CMDQ_EVENT_ISP_FRAME_DONE_A,
  CMDQ_EVENT_ISP_FRAME_DONE_B,
  CMDQ_EVENT_ISP_FRAME_DONE_C,
  CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE,
  CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE,
  CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE,
  CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE,
  CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE,
  CMDQ_EVENT_ISP_TSF_DONE,
  CMDQ_EVENT_ISP_RELAY_SOF,
  CMDQ_EVENT_IPU_RELAY_SOF,
  CMDQ_EVENT_SENINF_0_FIFO_FULL,
  CMDQ_EVENT_SENINF_1_FIFO_FULL,
  CMDQ_EVENT_SENINF_2_FIFO_FULL,
  CMDQ_EVENT_SENINF_3_FIFO_FULL,
  CMDQ_EVENT_SENINF_4_FIFO_FULL,
  CMDQ_EVENT_SENINF_5_FIFO_FULL,
  CMDQ_EVENT_SENINF_6_FIFO_FULL,
  CMDQ_EVENT_SENINF_7_FIFO_FULL,
  CMDQ_EVENT_TG_OVRUN_A_INT_DLY,
  CMDQ_EVENT_TG_OVRUN_B_INT_DLY,
  CMDQ_EVENT_TG_OVRUN_C_INT,
  CMDQ_EVENT_TG_GRABERR_A_INT_DLY,
  CMDQ_EVENT_TG_GRABERR_B_INT_DLY,
  CMDQ_EVENT_TG_GRABERR_C_INT,
  CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY,
  CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY,
  CMDQ_EVENT_CQ_VR_SNAP_C_INT,
  CMDQ_EVENT_DISP_DSC1_SOF,
  CMDQ_EVENT_DISP_DSC2_SOF,
  CMDQ_EVENT_DISP_RSZ0_SOF,
  CMDQ_EVENT_DISP_RSZ1_SOF,
  CMDQ_EVENT_DISP_DSC0_EOF,
  CMDQ_EVENT_DISP_DSC1_EOF,
  CMDQ_EVENT_DISP_RSZ0_EOF,
  CMDQ_EVENT_DISP_RSZ1_EOF,
  CMDQ_EVENT_DISP_OVL0_RST_DONE,
  CMDQ_EVENT_DISP_OVL1_RST_DONE,
  CMDQ_EVENT_DISP_OVL0_2L_RST_DONE,
  CMDQ_EVENT_DISP_OVL1_2L_RST_DONE,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE35,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE36,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE37,
  CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE38,
  CMDQ_EVENT_WPE_A_EOF,
  CMDQ_EVENT_EAF_EOF,
  CMDQ_EVENT_VENC_BSDMA_FULL,
  CMDQ_EVENT_IPU0_EOF,
  CMDQ_EVENT_IPU1_EOF,
  CMDQ_EVENT_IPU2_EOF,
  CMDQ_EVENT_IPU3_EOF,
  CMDQ_EVENT_DISP_SPLIT_SOF,
  CMDQ_EVENT_DISP_SPLIT_FRAME_DONE,
  CMDQ_EVENT_AMD_FRAME_DONE,
  CMDQ_EVENT_DISP_DPI0_SOF,
  CMDQ_EVENT_DSI0_TE_INFRA,
  CMDQ_EVENT_DISP_DBI0_SOF,
  CMDQ_EVENT_DISP_DBI0_EOF,
  CMDQ_EVENT_MDP_CCORR_SOF,
  CMDQ_EVENT_MDP_CCORR_FRAME_DONE,
  CMDQ_EVENT_MDP_AAL_FRAME_DONE,
  CMDQ_EVENT_WPE_B_FRAME_DONE,
  CMDQ_EVENT_MFB_DONE,
  CMDQ_EVENT_OCC_DONE,
  CMDQ_EVENT_IPU_DONE_1_1,
  CMDQ_EVENT_IPU_DONE_1_2,
  CMDQ_EVENT_IPU_DONE_1_0,
  CMDQ_EVENT_IPU_DONE_1_3,
  CMDQ_EVENT_IPU_DONE_2_0,
  CMDQ_EVENT_IPU_DONE_2_1,
  CMDQ_EVENT_IPU_DONE_2_3,
  CMDQ_EVENT_IPU_DONE_2_2,
  CMDQ_EVENT_MDP_CCORR0_SOF,
  CMDQ_EVENT_MDP_CCORR0_FRAME_DONE,
  CMDQ_EVENT_IMG_DL_RELAY_SOF,
  CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY,
  CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY,
  CMDQ_EVENT_DMA_R1_ERROR_C_INT,
  CMDQ_EVENT_APU_GCE_CORE0_EVENT_0,
  CMDQ_EVENT_APU_GCE_CORE0_EVENT_1,
  CMDQ_EVENT_APU_GCE_CORE0_EVENT_2,
  CMDQ_EVENT_APU_GCE_CORE0_EVENT_3,
  CMDQ_EVENT_APU_GCE_CORE1_EVENT_0,
  CMDQ_EVENT_APU_GCE_CORE1_EVENT_1,
  CMDQ_EVENT_APU_GCE_CORE1_EVENT_2,
  CMDQ_EVENT_APU_GCE_CORE1_EVENT_3,
  CMDQ_EVENT_VDEC_EVENT_0,
  CMDQ_EVENT_VDEC_EVENT_1,
  CMDQ_EVENT_VDEC_EVENT_2,
  CMDQ_EVENT_VDEC_EVENT_3,
  CMDQ_EVENT_VDEC_EVENT_4,
  CMDQ_EVENT_VDEC_EVENT_5,
  CMDQ_EVENT_VDEC_EVENT_6,
  CMDQ_EVENT_VDEC_EVENT_7,
  CMDQ_EVENT_VDEC_EVENT_8,
  CMDQ_EVENT_VDEC_EVENT_9,
  CMDQ_EVENT_VDEC_EVENT_10,
  CMDQ_EVENT_VDEC_EVENT_11,
  CMDQ_EVENT_VDEC_EVENT_12,
  CMDQ_EVENT_VDEC_EVENT_13,
  CMDQ_EVENT_VDEC_EVENT_14,
  CMDQ_EVENT_VDEC_EVENT_15,
  CMDQ_EVENT_FDVT_DONE,
  CMDQ_EVENT_FE_DONE,
  CMDQ_EVENT_DVS_DONE_ASYNC_SHOT,
  CMDQ_EVENT_DVP_DONE_ASYNC_SHOT,
  CMDQ_MAX_HW_EVENT_COUNT = 512,
  CMDQ_SYNC_TOKEN_CONFIG_DIRTY = 640,
  CMDQ_SYNC_TOKEN_STREAM_EOF,
  CMDQ_SYNC_TOKEN_ESD_EOF,
  CMDQ_SYNC_TOKEN_CABC_EOF,
  CMDQ_SYNC_TOKEN_FREEZE_EOF,
  CMDQ_SYNC_TOKEN_VENC_INPUT_READY,
  CMDQ_SYNC_TOKEN_VENC_EOF,
  CMDQ_SYNC_SECURE_THR_EOF,
  CMDQ_SYNC_SECURE_WSM_LOCK,
  CMDQ_SYNC_TOKEN_USER_0,
  CMDQ_SYNC_TOKEN_USER_1,
  CMDQ_SYNC_TOKEN_POLL_MONITOR,
  CMDQ_SYNC_TOKEN_EXT_CONFIG_DIRTY,
  CMDQ_SYNC_TOKEN_EXT_STREAM_EOF,
  CMDQ_SYNC_TOKEN_EXT_CABC_EOF,
  CMDQ_SYNC_DISP_OVL0_2NONSEC_END,
  CMDQ_SYNC_DISP_OVL1_2NONSEC_END,
  CMDQ_SYNC_DISP_2LOVL0_2NONSEC_END,
  CMDQ_SYNC_DISP_2LOVL1_2NONSEC_END,
  CMDQ_SYNC_DISP_RDMA0_2NONSEC_END,
  CMDQ_SYNC_DISP_RDMA1_2NONSEC_END,
  CMDQ_SYNC_DISP_WDMA0_2NONSEC_END,
  CMDQ_SYNC_DISP_WDMA1_2NONSEC_END,
  CMDQ_SYNC_DISP_EXT_STREAM_EOF,
  CMDQ_SYNC_TOKEN_APPEND_THR0 = 670,
  CMDQ_SYNC_TOKEN_APPEND_THR1,
  CMDQ_SYNC_TOKEN_APPEND_THR2,
  CMDQ_SYNC_TOKEN_APPEND_THR3,
  CMDQ_SYNC_TOKEN_APPEND_THR4,
  CMDQ_SYNC_TOKEN_APPEND_THR5,
  CMDQ_SYNC_TOKEN_APPEND_THR6,
  CMDQ_SYNC_TOKEN_APPEND_THR7,
  CMDQ_SYNC_TOKEN_APPEND_THR8,
  CMDQ_SYNC_TOKEN_APPEND_THR9,
  CMDQ_SYNC_TOKEN_APPEND_THR10,
  CMDQ_SYNC_TOKEN_APPEND_THR11,
  CMDQ_SYNC_TOKEN_APPEND_THR12,
  CMDQ_SYNC_TOKEN_APPEND_THR13,
  CMDQ_SYNC_TOKEN_APPEND_THR14,
  CMDQ_SYNC_TOKEN_APPEND_THR15,
  CMDQ_SYNC_TOKEN_APPEND_THR16,
  CMDQ_SYNC_TOKEN_APPEND_THR17,
  CMDQ_SYNC_TOKEN_APPEND_THR18,
  CMDQ_SYNC_TOKEN_APPEND_THR19,
  CMDQ_SYNC_TOKEN_APPEND_THR20,
  CMDQ_SYNC_TOKEN_APPEND_THR21,
  CMDQ_SYNC_TOKEN_APPEND_THR22,
  CMDQ_SYNC_TOKEN_APPEND_THR23,
  CMDQ_SYNC_TOKEN_GPR_SET_0 = 700,
  CMDQ_SYNC_TOKEN_GPR_SET_1,
  CMDQ_SYNC_TOKEN_GPR_SET_2,
  CMDQ_SYNC_TOKEN_GPR_SET_3,
  CMDQ_SYNC_TOKEN_GPR_SET_4,
  CMDQ_SYNC_RESOURCE_WROT0 = 710,
  CMDQ_SYNC_RESOURCE_WROT1 = 711,
  CMDQ_SYNC_TOKEN_TIMER = 720,
  CMDQ_SYNC_TOKEN_DELAY_SET0 = 721,
  CMDQ_SYNC_TOKEN_DELAY_SET1 = 722,
  CMDQ_SYNC_TOKEN_DELAY_SET2 = 723,
  CMDQ_EVENT_TIMER_00 = 962,
  CMDQ_EVENT_TIMER_01 = 963,
  CMDQ_EVENT_TIMER_02 = 964,
  CMDQ_EVENT_TIMER_03 = 965,
  CMDQ_EVENT_TIMER_04 = 966,
  CMDQ_EVENT_TIMER_05 = 967,
  CMDQ_EVENT_TIMER_06 = 968,
  CMDQ_EVENT_TIMER_07 = 969,
  CMDQ_EVENT_TIMER_08 = 970,
  CMDQ_EVENT_TIMER_09 = 971,
  CMDQ_EVENT_TIMER_10 = 972,
  CMDQ_EVENT_TIMER_11 = 973,
  CMDQ_EVENT_TIMER_12 = 974,
  CMDQ_EVENT_TIMER_13 = 975,
  CMDQ_EVENT_TIMER_14 = 976,
  CMDQ_EVENT_TIMER_15 = 977,
  CMDQ_EVENT_TIMER_16 = 978,
  CMDQ_EVENT_TIMER_17 = 979,
  CMDQ_EVENT_TIMER_18 = 980,
  CMDQ_EVENT_TIMER_19 = 981,
  CMDQ_EVENT_TIMER_20 = 982,
  CMDQ_EVENT_TIMER_21 = 983,
  CMDQ_EVENT_TIMER_22 = 984,
  CMDQ_EVENT_TIMER_23 = 985,
  CMDQ_EVENT_TIMER_24 = 986,
  CMDQ_EVENT_TIMER_25 = 987,
  CMDQ_EVENT_TIMER_26 = 988,
  CMDQ_EVENT_TIMER_27 = 989,
  CMDQ_EVENT_TIMER_28 = 990,
  CMDQ_EVENT_TIMER_29 = 991,
  CMDQ_EVENT_TIMER_30 = 992,
  CMDQ_EVENT_TIMER_31 = 993,
  CMDQ_EVENT_TIMER_GPR = 994,
  CMDQ_SYNC_TOKEN_MAX = 0x3FF,
  CMDQ_SYNC_TOKEN_INVALID = - 1,
};
#endif