/**************************************************************************** **************************************************************************** *** *** This header was automatically generated from a Linux kernel header *** of the same name, to make information necessary for userspace to *** call into the kernel available to libc. It contains only constants, *** structures, and macros generated from the original header, and thus, *** contains no copyrightable information. *** *** To edit the content of this header, modify the corresponding *** source file (e.g. under external/kernel-headers/original/) then *** run bionic/libc/kernel/tools/update_all.py *** *** Any manual change here will be lost the next time this script will *** be run. You've been warned! *** **************************************************************************** ****************************************************************************/ #ifndef _UAPI_MEDIATEK_DRM_H #define _UAPI_MEDIATEK_DRM_H #include #define MTK_SUBMIT_NO_IMPLICIT 0x0 #define MTK_SUBMIT_IN_FENCE 0x1 #define MTK_SUBMIT_OUT_FENCE 0x2 #define MTK_DRM_PROP_OVERLAP_LAYER_NUM "OVERLAP_LAYER_NUM" #define MTK_DRM_PROP_NEXT_BUFF_IDX "NEXT_BUFF_IDX" #define MTK_DRM_PROP_PRESENT_FENCE "PRESENT_FENCE" #define MAX_DBV_PN 100 #define MAX_FPS_PN 20 #ifndef BIT #define BIT(n) (1 << (n)) #endif struct mml_frame_info; struct drm_mtk_gem_create { uint64_t size; uint32_t flags; uint32_t handle; }; struct drm_mtk_gem_map_off { uint32_t handle; uint32_t pad; uint64_t offset; }; struct drm_mtk_gem_submit { uint32_t type; uint32_t session_id; uint32_t layer_id; uint32_t layer_en; uint32_t fb_id; uint32_t index; int32_t fence_fd; uint32_t interface_index; int32_t interface_fence_fd; int32_t ion_fd; }; struct drm_mtk_sec_gem_hnd { uint32_t sec_hnd; uint32_t gem_hnd; }; struct drm_mtk_session { uint32_t type; uint32_t device_id; uint32_t mode; uint32_t session_id; }; enum drm_disp_ccorr_id_t { DRM_DISP_CCORR0 = 0, DRM_DISP_CCORR1, DRM_DISP_CCORR_TOTAL }; enum drm_disp_ccorr_linear_t { DRM_DISP_NONLINEAR = 0, DRM_DISP_LINEAR, }; struct DRM_DISP_CCORR_COEF_T { union { enum drm_disp_ccorr_id_t hw_id; enum drm_disp_ccorr_linear_t linear; }; unsigned int coef[3][3]; unsigned int offset[3]; int FinalBacklight; int silky_bright_flag; }; struct DISP_DITHER_PARAM { bool relay; uint32_t mode; }; struct DISP_AAL_TRIG_STATE { int curAli; int aliThreshold; unsigned int dre_frm_trigger; unsigned int dre3_en_state; unsigned int dre3_krn_flag; }; #define DRM_MTK_GEM_CREATE 0x00 #define DRM_MTK_GEM_MAP_OFFSET 0x01 #define DRM_MTK_GEM_SUBMIT 0x02 #define DRM_MTK_SESSION_CREATE 0x03 #define DRM_MTK_SESSION_DESTROY 0x04 #define DRM_MTK_LAYERING_RULE 0x05 #define DRM_MTK_CRTC_GETFENCE 0x06 #define DRM_MTK_WAIT_REPAINT 0x07 #define DRM_MTK_GET_DISPLAY_CAPS 0x08 #define DRM_MTK_SET_DDP_MODE 0x09 #define DRM_MTK_GET_SESSION_INFO 0x0A #define DRM_MTK_SEC_HND_TO_GEM_HND 0x0B #define DRM_MTK_GET_MASTER_INFO 0x0C #define DRM_MTK_CRTC_GETSFFENCE 0x0D #define DRM_MTK_MML_GEM_SUBMIT 0x0E #define DRM_MTK_SET_MSYNC_PARAMS 0x0F #define DRM_MTK_GET_MSYNC_PARAMS 0x10 #define DRM_MTK_FACTORY_LCM_AUTO_TEST 0x11 #define DRM_MTK_DRM_SET_LEASE_INFO 0x12 #define DRM_MTK_DRM_GET_LEASE_INFO 0x13 #define DRM_MTK_CRTC_FENCE_REL 0x14 #define DRM_MTK_GET_MODE_EXT_INFO 0x15 #define DRM_MTK_HWVSYNC_ON 0x16 #define DRM_MTK_SET_12BIT_GAMMALUT 0x1D #define DRM_MTK_PQ_PERSIST_PROPERTY 0x1F #define DRM_MTK_SET_CCORR 0x20 #define DRM_MTK_CCORR_EVENTCTL 0x21 #define DRM_MTK_CCORR_GET_IRQ 0x22 #define DRM_MTK_SET_GAMMALUT 0x23 #define DRM_MTK_SET_PQPARAM 0x24 #define DRM_MTK_SET_PQINDEX 0x25 #define DRM_MTK_SET_COLOR_REG 0x26 #define DRM_MTK_MUTEX_CONTROL 0x27 #define DRM_MTK_READ_REG 0x28 #define DRM_MTK_WRITE_REG 0x29 #define DRM_MTK_BYPASS_COLOR 0x2A #define DRM_MTK_PQ_SET_WINDOW 0x2B #define DRM_MTK_GET_LCM_INDEX 0x2C #define DRM_MTK_SUPPORT_COLOR_TRANSFORM 0x2D #define DRM_MTK_READ_SW_REG 0x2E #define DRM_MTK_WRITE_SW_REG 0x2F #define DRM_MTK_AAL_INIT_REG 0x30 #define DRM_MTK_AAL_GET_HIST 0x31 #define DRM_MTK_AAL_SET_PARAM 0x32 #define DRM_MTK_AAL_EVENTCTL 0x33 #define DRM_MTK_AAL_INIT_DRE30 0x34 #define DRM_MTK_AAL_GET_SIZE 0x35 #define DRM_MTK_AAL_SET_TRIGGER_STATE 0x5F #define DRM_MTK_AAL_SET_ESS20_SPECT_PARAM 0x36 #define DRM_MTK_HDMI_GET_DEV_INFO 0x3A #define DRM_MTK_HDMI_AUDIO_ENABLE 0x3B #define DRM_MTK_HDMI_AUDIO_CONFIG 0x3C #define DRM_MTK_HDMI_GET_CAPABILITY 0x3D #define DRM_MTK_DEBUG_LOG 0x3E /* C3D */ #define DRM_MTK_C3D_GET_BIN_NUM 0x40 #define DRM_MTK_C3D_GET_IRQ 0x41 #define DRM_MTK_C3D_EVENTCTL 0x42 #define DRM_MTK_C3D_SET_LUT 0x44 #define DRM_MTK_SET_BYPASS_C3D 0x45 /* CHIST */ #define DRM_MTK_GET_CHIST 0x46 #define DRM_MTK_GET_CHIST_CAPS 0x47 #define DRM_MTK_SET_CHIST_CONFIG 0x48 #define DRM_MTK_SET_DITHER_PARAM 0x43 #define DRM_MTK_BYPASS_DISP_GAMMA 0x49 /* DISP TDSHP */ #define DRM_MTK_SET_DISP_TDSHP_REG 0x50 #define DRM_MTK_DISP_TDSHP_GET_SIZE 0x51 #define DRM_MTK_CRTC_GETPQFENCE 0x52 #define DRM_MTK_CRTC_RELEASEPQFENCE 0x53 #define DRM_MTK_GET_PQ_CAPS 0x54 #define DRM_MTK_SET_PQ_CAPS 0x55 #define DRM_MTK_AIBLD_CV_MODE 0x56 #define DRM_MTK_ODDMR_LOAD_PARAM 0x57 #define DRM_MTK_ODDMR_CTL 0x58 #define DRM_MTK_SET_GAMMA_MUL_DISABLE 0x59 #define DRM_MTK_GET_PANELS_INFO 0x5a #define DRM_MTK_KICK_IDLE 0x5b #define DRM_MTK_PQ_FRAME_CONFIG 0x5c /* DISP_CLARITY */ #define DRM_MTK_DISP_CLARITY_SET_REG 0x5E #define DRM_MTK_PQ_PROXY_IOCTL 0x37 /* The device specific ioctl range is from DRM_COMMAND_BASE(0x40) to DRM_COMMAND_END(0x9f) * The index of ioctl which define here must be less then 0x60 */ /* C3D */ #define DISP_C3D_1DLUT_SIZE 32 #define MAX_FRAME_RATIO_NUMBER (5) /* Display Clarity */ #define MDP_AAL_CLARITY_READBACK_NUM (7) #define DISP_TDSHP_CLARITY_READBACK_NUM (12) struct DISP_C3D_LUT { unsigned int lut1d[DISP_C3D_1DLUT_SIZE]; unsigned long long lut3d; }; enum MTKFB_DISPIF_TYPE { DISPIF_TYPE_DBI = 0, DISPIF_TYPE_DPI, DISPIF_TYPE_DSI, DISPIF_TYPE_DPI0, DISPIF_TYPE_DPI1, DISPIF_TYPE_DSI0, DISPIF_TYPE_DSI1, HDMI = 7, HDMI_SMARTBOOK, MHL, DISPIF_TYPE_EPD, DISPLAYPORT, SLIMPORT }; enum MTKFB_DISPIF_MODE { DISPIF_MODE_VIDEO = 0, DISPIF_MODE_COMMAND }; struct mtk_dispif_info { unsigned int display_id; unsigned int isHwVsyncAvailable; enum MTKFB_DISPIF_TYPE displayType; unsigned int displayWidth; unsigned int displayHeight; unsigned int displayFormat; enum MTKFB_DISPIF_MODE displayMode; unsigned int vsyncFPS; unsigned int physicalWidth; unsigned int physicalHeight; unsigned int isConnected; unsigned int lcmOriginalWidth; unsigned int lcmOriginalHeight; }; enum MTK_DRM_SESSION_MODE { MTK_DRM_SESSION_INVALID = 0, MTK_DRM_SESSION_DL, MTK_DRM_SESSION_DOUBLE_DL, MTK_DRM_SESSION_DC_MIRROR, MTK_DRM_SESSION_TRIPLE_DL, MTK_DRM_SESSION_NUM, }; enum MTK_LAYERING_CAPS { MTK_LAYERING_OVL_ONLY = 0x00000001, MTK_MDP_RSZ_LAYER = 0x00000002, MTK_DISP_RSZ_LAYER = 0x00000004, MTK_MDP_ROT_LAYER = 0x00000008, MTK_MDP_HDR_LAYER = 0x00000010, MTK_NO_FBDC = 0x00000020, MTK_CLIENT_CLEAR_LAYER = 0x00000040, MTK_DISP_CLIENT_CLEAR_LAYER = 0x00000080, MTK_DMDP_RSZ_LAYER = 0x00000100, MTK_MML_OVL_LAYER = 0x00000200, MTK_MML_DISP_DIRECT_LINK_LAYER = 0x00000400, MTK_MML_DISP_DIRECT_DECOUPLE_LAYER = 0x00000800, MTK_MML_DISP_DECOUPLE_LAYER = 0x00001000, MTK_MML_DISP_MDP_LAYER = 0x00002000, MTK_MML_DISP_NOT_SUPPORT = 0x00004000, MTK_HWC_UNCHANGED_LAYER = 0x00008000, MTK_HWC_INACTIVE_LAYER = 0x00010000, MTK_HWC_UNCHANGED_FBT_LAYER = 0x00020000, MTK_DISP_UNCHANGED_RATIO_VALID = 0x00040000, MTK_DISP_FBT_RATIO_VALID = 0x00080000, MTK_DISP_CLIENT_LAYER = 0x00100000, MTK_DISP_SRC_YUV_LAYER = 0x00200000, }; enum MTK_DISP_CAPS { MTK_GLES_FBT_GET_RATIO = 0x00000001, MTK_GLES_FBT_UNCHANGED = 0x00000002, MTK_NEED_REPAINT = 0x00000004, }; struct drm_mtk_layer_config { uint32_t ovl_id; uint32_t src_fmt; int dataspace; uint32_t dst_offset_x, dst_offset_y; uint32_t dst_width, dst_height; int ext_sel_layer; uint32_t src_offset_x, src_offset_y; uint32_t src_width, src_height; uint32_t layer_caps; uint32_t clip; uint64_t buffer_alloc_id; __u8 compress; __u8 secure; __u8 wcg_force_gpu; /* drv internel use */ __u32 layer_hrt_weight; /* drv internal use */ }; struct wb_frame_info { uint32_t fmt; uint32_t src_width, src_height; uint32_t dst_width, dst_height; }; #define LYE_CRTC 4 struct drm_mtk_layering_info { struct drm_mtk_layer_config * input_config[LYE_CRTC]; int disp_mode[LYE_CRTC]; int disp_mode_idx[LYE_CRTC]; int layer_num[LYE_CRTC]; int gles_head[LYE_CRTC]; int gles_tail[LYE_CRTC]; uint32_t disp_caps[LYE_CRTC]; uint32_t frame_idx[LYE_CRTC]; int hrt_num; uint32_t disp_idx; uint32_t disp_list; int res_idx; uint32_t hrt_weight; uint32_t hrt_idx; struct mml_frame_info * mml_cfg[LYE_CRTC]; struct wb_frame_info wb_cfg[LYE_CRTC]; int color_mode[LYE_CRTC]; }; /* Msync 2.0 */ struct msync_level_table { uint32_t level_id; uint32_t level_fps; uint32_t max_fps; uint32_t min_fps; }; struct msync_parameter_table { uint32_t msync_max_fps; uint32_t msync_min_fps; uint32_t msync_level_num; struct msync_level_table *level_tb; }; struct drm_mtk_fence { uint32_t crtc_id; int32_t fence_fd; uint32_t fence_idx; }; enum DRM_REPAINT_TYPE { DRM_WAIT_FOR_REPAINT, DRM_REPAINT_FOR_ANTI_LATENCY, DRM_REPAINT_FOR_SWITCH_DECOUPLE, DRM_REPAINT_FOR_SWITCH_DECOUPLE_MIRROR, DRM_REPAINT_FOR_IDLE, DRM_REPAINT_TYPE_NUM, }; enum MTK_DRM_DISP_FEATURE { DRM_DISP_FEATURE_HRT = 0x00000001, DRM_DISP_FEATURE_DISP_SELF_REFRESH = 0x00000002, DRM_DISP_FEATURE_RPO = 0x00000004, DRM_DISP_FEATURE_FORCE_DISABLE_AOD = 0x00000008, DRM_DISP_FEATURE_OUTPUT_ROTATED = 0x00000010, DRM_DISP_FEATURE_THREE_SESSION = 0x00000020, DRM_DISP_FEATURE_FBDC = 0x00000040, DRM_DISP_FEATURE_SF_PRESENT_FENCE = 0x00000080, DRM_DISP_FEATURE_PQ_34_COLOR_MATRIX = 0x00000100, DRM_DISP_FEATURE_MSYNC2_0 = 0x00000200, DRM_DISP_FEATURE_MML_PRIMARY = 0x00000400, DRM_DISP_FEATURE_VIRUTAL_DISPLAY = 0x00000800, DRM_DISP_FEATURE_IOMMU = 0x00001000, DRM_DISP_FEATURE_OVL_BW_MONITOR = 0x00002000, DRM_DISP_FEATURE_GPU_CACHE = 0x00004000, DRM_DISP_FEATURE_SPHRT = 0x00008000, DRM_DISP_FEATURE_PARTIAL_UPDATE = 0x00010000, }; #define DRM_HDMI_DEV_DRV "dev/dri/card0" #define MTK_DRM_CHANNEL_2_BIT (1 << MTK_DRM_CHANNEL_2) #define MTK_DRM_CHANNEL_3_BIT (1 << MTK_DRM_CHANNEL_3) #define MTK_DRM_CHANNEL_4_BIT (1 << MTK_DRM_CHANNEL_4) #define MTK_DRM_CHANNEL_5_BIT (1 << MTK_DRM_CHANNEL_5) #define MTK_DRM_CHANNEL_6_BIT (1 << MTK_DRM_CHANNEL_6) #define MTK_DRM_CHANNEL_7_BIT (1 << MTK_DRM_CHANNEL_7) #define MTK_DRM_CHANNEL_8_BIT (1 << MTK_DRM_CHANNEL_8) #define MTK_DRM_SAMPLERATE_32K_BIT (1 << MTK_DRM_SAMPLERATE_32K) #define MTK_DRM_SAMPLERATE_44K_BIT (1 << MTK_DRM_SAMPLERATE_44K) #define MTK_DRM_SAMPLERATE_48K_BIT (1 << MTK_DRM_SAMPLERATE_48K) #define MTK_DRM_SAMPLERATE_96K_BIT (1 << MTK_DRM_SAMPLERATE_96K) #define MTK_DRM_SAMPLERATE_192K_BIT (1 << MTK_DRM_SAMPLERATE_192K) #define MTK_DRM_BITWIDTH_16_BIT (1 << MTK_DRM_BITWIDTH_16) #define MTK_DRM_BITWIDTH_24_BIT (1 << MTK_DRM_BITWIDTH_24) #define MTK_DRM_CAPABILITY_CHANNEL_MASK 0x7f #define MTK_DRM_CAPABILITY_CHANNEL_SFT 0 #define MTK_DRM_CAPABILITY_SAMPLERATE_MASK 0x1f #define MTK_DRM_CAPABILITY_SAMPLERATE_SFT 8 #define MTK_DRM_CAPABILITY_BITWIDTH_MASK 0x7 #define MTK_DRM_CAPABILITY_BITWIDTH_SFT 16 enum MTK_DRM_CHANNEL { MTK_DRM_CHANNEL_2, MTK_DRM_CHANNEL_3, MTK_DRM_CHANNEL_4, MTK_DRM_CHANNEL_5, MTK_DRM_CHANNEL_6, MTK_DRM_CHANNEL_7, MTK_DRM_CHANNEL_8, MTK_DRM_CHANNEL_NUM }; enum MTK_DRM_SAMPLERATE { MTK_DRM_SAMPLERATE_32K, MTK_DRM_SAMPLERATE_44K, MTK_DRM_SAMPLERATE_48K, MTK_DRM_SAMPLERATE_96K, MTK_DRM_SAMPLERATE_192K, MTK_DRM_SAMPLERATE_NUM }; enum MTK_DRM_BITWIDTH { MTK_DRM_BITWIDTH_16, MTK_DRM_BITWIDTH_24 = 2, MTK_DRM_BITWIDTH_NUM = 2 }; enum mtk_mmsys_id { MMSYS_MT2701 = 0x2701, MMSYS_MT2712 = 0x2712, MMSYS_MT8173 = 0x8173, MMSYS_MT6779 = 0x6779, MMSYS_MT6885 = 0x6885, MMSYS_MT6983 = 0x6983, MMSYS_MT6985 = 0x6985, MMSYS_MT6873 = 0x6873, MMSYS_MT6853 = 0x6853, MMSYS_MT6833 = 0x6833, MMSYS_MT6877 = 0x6877, MMSYS_MT6879 = 0x6879, MMSYS_MT6895 = 0x6895, MMSYS_MT6886 = 0x6886, MMSYS_MT6855 = 0x6855, MMSYS_MT6897 = 0x6897, MMSYS_MT6989 = 0x6989, MMSYS_MT6878 = 0x6878, MMSYS_MAX, }; #define MTK_DRM_COLOR_FORMAT_A_BIT (1 << MTK_DRM_COLOR_FORMAT_A) #define MTK_DRM_COLOR_FORMAT_R_BIT (1 << MTK_DRM_COLOR_FORMAT_R) #define MTK_DRM_COLOR_FORMAT_G_BIT (1 << MTK_DRM_COLOR_FORMAT_G) #define MTK_DRM_COLOR_FORMAT_B_BIT (1 << MTK_DRM_COLOR_FORMAT_B) #define MTK_DRM_COLOR_FORMAT_Y_BIT (1 << MTK_DRM_COLOR_FORMAT_Y) #define MTK_DRM_COLOR_FORMAT_U_BIT (1 << MTK_DRM_COLOR_FORMAT_U) #define MTK_DRM_COLOR_FORMAT_V_BIT (1 << MTK_DRM_COLOR_FORMAT_V) #define MTK_DRM_COLOR_FORMAT_S_BIT (1 << MTK_DRM_COLOR_FORMAT_S) #define MTK_DRM_COLOR_FORMAT_H_BIT (1 << MTK_DRM_COLOR_FORMAT_H) #define MTK_DRM_COLOR_FORMAT_M_BIT (1 << MTK_DRM_COLOR_FORMAT_M) #define MTK_DRM_DISP_CHIST_CHANNEL_COUNT 7 enum MTK_DRM_CHIST_COLOR_FORMT { MTK_DRM_COLOR_FORMAT_A, MTK_DRM_COLOR_FORMAT_R, MTK_DRM_COLOR_FORMAT_G, MTK_DRM_COLOR_FORMAT_B, MTK_DRM_COLOR_FORMAT_Y, MTK_DRM_COLOR_FORMAT_U, MTK_DRM_COLOR_FORMAT_V, MTK_DRM_COLOR_FORMAT_H, MTK_DRM_COLOR_FORMAT_S, MTK_DRM_COLOR_FORMAT_M, MTK_DRM_COLOR_FORMAT_MAX }; enum MTK_DRM_CHIST_CALLER { MTK_DRM_CHIST_CALLER_PQ, MTK_DRM_CHIST_CALLER_HWC, MTK_DRM_CHIST_CALLER_UNKONW }; enum MTK_DRM_DUMP_POINT { MTK_DRM_BEFORE_PQ, MTK_DRM_AFTER_PQ, MTK_DRM_DUMP_POINT_NUM, }; struct mtk_drm_disp_caps_info { unsigned int hw_ver; unsigned int disp_feature_flag; int lcm_degree; unsigned int rsz_in_max[2]; int lcm_color_mode; unsigned int max_luminance; unsigned int average_luminance; unsigned int min_luminance; /* for color histogram */ unsigned int color_format; unsigned int max_bin; unsigned int max_channel; /* Msync 2.0 */ unsigned int msync_level_num; }; enum MTK_CRTC_ABILITY { ABILITY_FBDC = BIT(0), ABILITY_EXT_LAYER = BIT(1), ABILITY_IDLEMGR = BIT(2), ABILITY_ESD_CHECK = BIT(3), ABILITY_PQ = BIT(4), ABILITY_RSZ = BIT(5), ABILITY_MML = BIT(6), ABILITY_WCG = BIT(7), ABILITY_PRE_TE = BIT(8), ABILITY_BW_MONITOR = BIT(9), ABILITY_CWB = BIT(10), ABILITY_MSYNC20 = BIT(11), ABILITY_DUAL_DISCRETE = BIT(12), ABILITY_PARTIAL_UPDATE = BIT(13), }; struct mtk_drm_wb_caps { bool support; bool rsz; bool rsz_crop; unsigned int rsz_out_min_w; unsigned int rsz_out_min_h; unsigned int rsz_out_max_w; unsigned int rsz_out_max_h; }; struct mtk_drm_crtc_caps { struct mtk_drm_wb_caps wb_caps[MTK_DRM_DUMP_POINT_NUM]; unsigned int crtc_ability; unsigned int ovl_csc_bit_number; }; struct drm_mtk_session_info { unsigned int session_id; unsigned int vsyncFPS; unsigned int physicalWidthUm; unsigned int physicalHeightUm; }; struct DISP_TDSHP_REG { uint32_t tdshp_softcoring_gain; uint32_t tdshp_gain_high; uint32_t tdshp_gain_mid; uint32_t tdshp_ink_sel; uint32_t tdshp_bypass_high; uint32_t tdshp_bypass_mid; uint32_t tdshp_en; uint32_t tdshp_limit_ratio; uint32_t tdshp_gain; uint32_t tdshp_coring_zero; uint32_t tdshp_coring_thr; uint32_t tdshp_coring_value; uint32_t tdshp_bound; uint32_t tdshp_limit; uint32_t tdshp_sat_proc; uint32_t tdshp_ac_lpf_coe; uint32_t tdshp_clip_thr; uint32_t tdshp_clip_ratio; uint32_t tdshp_clip_en; uint32_t tdshp_ylev_p048; uint32_t tdshp_ylev_p032; uint32_t tdshp_ylev_p016; uint32_t tdshp_ylev_p000; uint32_t tdshp_ylev_p112; uint32_t tdshp_ylev_p096; uint32_t tdshp_ylev_p080; uint32_t tdshp_ylev_p064; uint32_t tdshp_ylev_p176; uint32_t tdshp_ylev_p160; uint32_t tdshp_ylev_p144; uint32_t tdshp_ylev_p128; uint32_t tdshp_ylev_p240; uint32_t tdshp_ylev_p224; uint32_t tdshp_ylev_p208; uint32_t tdshp_ylev_p192; uint32_t tdshp_ylev_en; uint32_t tdshp_ylev_alpha; uint32_t tdshp_ylev_256; uint32_t pbc1_radius_r; uint32_t pbc1_theta_r; uint32_t pbc1_rslope_1; uint32_t pbc1_gain; uint32_t pbc1_lpf_en; uint32_t pbc1_en; uint32_t pbc1_lpf_gain; uint32_t pbc1_tslope; uint32_t pbc1_radius_c; uint32_t pbc1_theta_c; uint32_t pbc1_edge_slope; uint32_t pbc1_edge_thr; uint32_t pbc1_edge_en; uint32_t pbc1_conf_gain; uint32_t pbc1_rslope; uint32_t pbc2_radius_r; uint32_t pbc2_theta_r; uint32_t pbc2_rslope_1; uint32_t pbc2_gain; uint32_t pbc2_lpf_en; uint32_t pbc2_en; uint32_t pbc2_lpf_gain; uint32_t pbc2_tslope; uint32_t pbc2_radius_c; uint32_t pbc2_theta_c; uint32_t pbc2_edge_slope; uint32_t pbc2_edge_thr; uint32_t pbc2_edge_en; uint32_t pbc2_conf_gain; uint32_t pbc2_rslope; uint32_t pbc3_radius_r; uint32_t pbc3_theta_r; uint32_t pbc3_rslope_1; uint32_t pbc3_gain; uint32_t pbc3_lpf_en; uint32_t pbc3_en; uint32_t pbc3_lpf_gain; uint32_t pbc3_tslope; uint32_t pbc3_radius_c; uint32_t pbc3_theta_c; uint32_t pbc3_edge_slope; uint32_t pbc3_edge_thr; uint32_t pbc3_edge_en; uint32_t pbc3_conf_gain; uint32_t pbc3_rslope; uint32_t tdshp_mid_softlimit_ratio; uint32_t tdshp_mid_coring_zero; uint32_t tdshp_mid_coring_thr; uint32_t tdshp_mid_softcoring_gain; uint32_t tdshp_mid_coring_value; uint32_t tdshp_mid_bound; uint32_t tdshp_mid_limit; uint32_t tdshp_high_softlimit_ratio; uint32_t tdshp_high_coring_zero; uint32_t tdshp_high_coring_thr; uint32_t tdshp_high_softcoring_gain; uint32_t tdshp_high_coring_value; uint32_t tdshp_high_bound; uint32_t tdshp_high_limit; uint32_t edf_clip_ratio_inc; uint32_t edf_edge_gain; uint32_t edf_detail_gain; uint32_t edf_flat_gain; uint32_t edf_gain_en; uint32_t edf_edge_th; uint32_t edf_detail_fall_th; uint32_t edf_detail_rise_th; uint32_t edf_flat_th; uint32_t edf_edge_slope; uint32_t edf_detail_fall_slope; uint32_t edf_detail_rise_slope; uint32_t edf_flat_slope; uint32_t edf_edge_mono_slope; uint32_t edf_edge_mono_th; uint32_t edf_edge_mag_slope; uint32_t edf_edge_mag_th; uint32_t edf_edge_trend_flat_mag; uint32_t edf_edge_trend_slope; uint32_t edf_edge_trend_th; uint32_t edf_bld_wgt_mag; uint32_t edf_bld_wgt_mono; uint32_t edf_bld_wgt_trend; uint32_t tdshp_cboost_lmt_u; uint32_t tdshp_cboost_lmt_l; uint32_t tdshp_cboost_en; uint32_t tdshp_cboost_gain; uint32_t tdshp_cboost_yconst; uint32_t tdshp_cboost_yoffset_sel; uint32_t tdshp_cboost_yoffset; uint32_t tdshp_post_ylev_p048; uint32_t tdshp_post_ylev_p032; uint32_t tdshp_post_ylev_p016; uint32_t tdshp_post_ylev_p000; uint32_t tdshp_post_ylev_p112; uint32_t tdshp_post_ylev_p096; uint32_t tdshp_post_ylev_p080; uint32_t tdshp_post_ylev_p064; uint32_t tdshp_post_ylev_p176; uint32_t tdshp_post_ylev_p160; uint32_t tdshp_post_ylev_p144; uint32_t tdshp_post_ylev_p128; uint32_t tdshp_post_ylev_p240; uint32_t tdshp_post_ylev_p224; uint32_t tdshp_post_ylev_p208; uint32_t tdshp_post_ylev_p192; uint32_t tdshp_post_ylev_en; uint32_t tdshp_post_ylev_alpha; uint32_t tdshp_post_ylev_256; }; struct DISP_TDSHP_DISPLAY_SIZE { int width; int height; int lcm_width; int lcm_height; }; struct DISP_MDP_AAL_CLARITY_REG { // Bilateral uint32_t bilateral_impulse_noise_en; uint32_t dre_bilateral_detect_en; uint32_t bilateral_range_flt_slope; uint32_t bilateral_flt_en; uint32_t have_bilateral_filter; uint32_t dre_output_mode; // Bilateral Blending uint32_t dre_bilateral_activate_blending_A; uint32_t dre_bilateral_activate_blending_B; uint32_t dre_bilateral_activate_blending_C; uint32_t dre_bilateral_activate_blending_D; uint32_t dre_bilateral_activate_blending_wgt_gain; uint32_t dre_bilateral_blending_en; uint32_t dre_bilateral_blending_wgt; uint32_t dre_bilateral_blending_wgt_mode; uint32_t dre_bilateral_size_blending_wgt; // Filter 1 uint32_t bilateral_custom_range_flt1_0_0; uint32_t bilateral_custom_range_flt1_0_1; uint32_t bilateral_custom_range_flt1_0_2; uint32_t bilateral_custom_range_flt1_0_3; uint32_t bilateral_custom_range_flt1_0_4; uint32_t bilateral_custom_range_flt1_1_0; uint32_t bilateral_custom_range_flt1_1_1; uint32_t bilateral_custom_range_flt1_1_2; uint32_t bilateral_custom_range_flt1_1_3; uint32_t bilateral_custom_range_flt1_1_4; uint32_t bilateral_custom_range_flt1_2_0; uint32_t bilateral_custom_range_flt1_2_1; uint32_t bilateral_custom_range_flt1_2_2; uint32_t bilateral_custom_range_flt1_2_3; uint32_t bilateral_custom_range_flt1_2_4; // Filter 2 uint32_t bilateral_custom_range_flt2_0_0; uint32_t bilateral_custom_range_flt2_0_1; uint32_t bilateral_custom_range_flt2_0_2; uint32_t bilateral_custom_range_flt2_0_3; uint32_t bilateral_custom_range_flt2_0_4; uint32_t bilateral_custom_range_flt2_1_0; uint32_t bilateral_custom_range_flt2_1_1; uint32_t bilateral_custom_range_flt2_1_2; uint32_t bilateral_custom_range_flt2_1_3; uint32_t bilateral_custom_range_flt2_1_4; uint32_t bilateral_custom_range_flt2_2_0; uint32_t bilateral_custom_range_flt2_2_1; uint32_t bilateral_custom_range_flt2_2_2; uint32_t bilateral_custom_range_flt2_2_3; uint32_t bilateral_custom_range_flt2_2_4; // Bilateral Flt Config uint32_t bilateral_contrary_blending_wgt; uint32_t bilateral_custom_range_flt_gain; uint32_t bilateral_custom_range_flt_slope; uint32_t bilateral_range_flt_gain; uint32_t bilateral_size_blending_wgt; // Bilateral Frequency Blending uint32_t bilateral_contrary_blending_out_wgt; uint32_t bilateral_custom_range_flt1_out_wgt; uint32_t bilateral_custom_range_flt2_out_wgt; uint32_t bilateral_range_flt_out_wgt; uint32_t bilateral_size_blending_out_wgt; // Bilateral Region Protection uint32_t dre_bilateral_blending_region_protection_en; uint32_t dre_bilateral_region_protection_activate_A; uint32_t dre_bilateral_region_protection_activate_B; uint32_t dre_bilateral_region_protection_activate_C; uint32_t dre_bilateral_region_protection_activate_D; uint32_t dre_bilateral_region_protection_input_shift_bit; }; struct DISP_TDSHP_CLARITY_REG { // High & Mid Gain uint32_t tdshp_gain_high; uint32_t tdshp_gain_mid; // Mid-Band Vertical Filter uint32_t mid_coef_v_custom_range_flt_0_0; uint32_t mid_coef_v_custom_range_flt_0_1; uint32_t mid_coef_v_custom_range_flt_0_2; uint32_t mid_coef_v_custom_range_flt_0_3; uint32_t mid_coef_v_custom_range_flt_0_4; uint32_t mid_coef_v_custom_range_flt_1_0; uint32_t mid_coef_v_custom_range_flt_1_1; uint32_t mid_coef_v_custom_range_flt_1_2; uint32_t mid_coef_v_custom_range_flt_1_3; uint32_t mid_coef_v_custom_range_flt_1_4; uint32_t mid_coef_v_custom_range_flt_2_0; uint32_t mid_coef_v_custom_range_flt_2_1; uint32_t mid_coef_v_custom_range_flt_2_2; uint32_t mid_coef_v_custom_range_flt_2_3; uint32_t mid_coef_v_custom_range_flt_2_4; // Mid-Band Horizontal Filter uint32_t mid_coef_h_custom_range_flt_0_0; uint32_t mid_coef_h_custom_range_flt_0_1; uint32_t mid_coef_h_custom_range_flt_0_2; uint32_t mid_coef_h_custom_range_flt_0_3; uint32_t mid_coef_h_custom_range_flt_0_4; uint32_t mid_coef_h_custom_range_flt_1_0; uint32_t mid_coef_h_custom_range_flt_1_1; uint32_t mid_coef_h_custom_range_flt_1_2; uint32_t mid_coef_h_custom_range_flt_1_3; uint32_t mid_coef_h_custom_range_flt_1_4; uint32_t mid_coef_h_custom_range_flt_2_0; uint32_t mid_coef_h_custom_range_flt_2_1; uint32_t mid_coef_h_custom_range_flt_2_2; uint32_t mid_coef_h_custom_range_flt_2_3; uint32_t mid_coef_h_custom_range_flt_2_4; // High-Band Vertical Filter uint32_t high_coef_v_custom_range_flt_0_0; uint32_t high_coef_v_custom_range_flt_0_1; uint32_t high_coef_v_custom_range_flt_0_2; uint32_t high_coef_v_custom_range_flt_0_3; uint32_t high_coef_v_custom_range_flt_0_4; uint32_t high_coef_v_custom_range_flt_1_0; uint32_t high_coef_v_custom_range_flt_1_1; uint32_t high_coef_v_custom_range_flt_1_2; uint32_t high_coef_v_custom_range_flt_1_3; uint32_t high_coef_v_custom_range_flt_1_4; uint32_t high_coef_v_custom_range_flt_2_0; uint32_t high_coef_v_custom_range_flt_2_1; uint32_t high_coef_v_custom_range_flt_2_2; uint32_t high_coef_v_custom_range_flt_2_3; uint32_t high_coef_v_custom_range_flt_2_4; // High-Band Horizontal Filter uint32_t high_coef_h_custom_range_flt_0_0; uint32_t high_coef_h_custom_range_flt_0_1; uint32_t high_coef_h_custom_range_flt_0_2; uint32_t high_coef_h_custom_range_flt_0_3; uint32_t high_coef_h_custom_range_flt_0_4; uint32_t high_coef_h_custom_range_flt_1_0; uint32_t high_coef_h_custom_range_flt_1_1; uint32_t high_coef_h_custom_range_flt_1_2; uint32_t high_coef_h_custom_range_flt_1_3; uint32_t high_coef_h_custom_range_flt_1_4; uint32_t high_coef_h_custom_range_flt_2_0; uint32_t high_coef_h_custom_range_flt_2_1; uint32_t high_coef_h_custom_range_flt_2_2; uint32_t high_coef_h_custom_range_flt_2_3; uint32_t high_coef_h_custom_range_flt_2_4; // High-Band Right-Diagonal Filter uint32_t high_coef_rd_custom_range_flt_0_0; uint32_t high_coef_rd_custom_range_flt_0_1; uint32_t high_coef_rd_custom_range_flt_0_2; uint32_t high_coef_rd_custom_range_flt_0_3; uint32_t high_coef_rd_custom_range_flt_0_4; uint32_t high_coef_rd_custom_range_flt_1_0; uint32_t high_coef_rd_custom_range_flt_1_1; uint32_t high_coef_rd_custom_range_flt_1_2; uint32_t high_coef_rd_custom_range_flt_1_3; uint32_t high_coef_rd_custom_range_flt_1_4; uint32_t high_coef_rd_custom_range_flt_2_0; uint32_t high_coef_rd_custom_range_flt_2_1; uint32_t high_coef_rd_custom_range_flt_2_2; uint32_t high_coef_rd_custom_range_flt_2_3; uint32_t high_coef_rd_custom_range_flt_2_4; // High-Band Left-Diagonal Filter uint32_t high_coef_ld_custom_range_flt_0_0; uint32_t high_coef_ld_custom_range_flt_0_1; uint32_t high_coef_ld_custom_range_flt_0_2; uint32_t high_coef_ld_custom_range_flt_0_3; uint32_t high_coef_ld_custom_range_flt_0_4; uint32_t high_coef_ld_custom_range_flt_1_0; uint32_t high_coef_ld_custom_range_flt_1_1; uint32_t high_coef_ld_custom_range_flt_1_2; uint32_t high_coef_ld_custom_range_flt_1_3; uint32_t high_coef_ld_custom_range_flt_1_4; uint32_t high_coef_ld_custom_range_flt_2_0; uint32_t high_coef_ld_custom_range_flt_2_1; uint32_t high_coef_ld_custom_range_flt_2_2; uint32_t high_coef_ld_custom_range_flt_2_3; uint32_t high_coef_ld_custom_range_flt_2_4; // Active Parameters uint32_t mid_negative_offset; uint32_t mid_positive_offset; uint32_t high_negative_offset; uint32_t high_positive_offset; // Active Parameters Frequency D uint32_t D_active_parameter_N_gain; uint32_t D_active_parameter_N_offset; uint32_t D_active_parameter_P_gain; uint32_t D_active_parameter_P_offset; // Active Parameters Frequency H uint32_t High_active_parameter_N_gain; uint32_t High_active_parameter_N_offset; uint32_t High_active_parameter_P_gain; uint32_t High_active_parameter_P_offset; // Active Parameters Frequency L uint32_t L_active_parameter_N_gain; uint32_t L_active_parameter_N_offset; uint32_t L_active_parameter_P_gain; uint32_t L_active_parameter_P_offset; // Active Parameters Frequency M uint32_t Mid_active_parameter_N_gain; uint32_t Mid_active_parameter_N_offset; uint32_t Mid_active_parameter_P_gain; uint32_t Mid_active_parameter_P_offset; // Size Parameters uint32_t SIZE_PARA_BIG_HUGE; uint32_t SIZE_PARA_MEDIUM_BIG; uint32_t SIZE_PARA_SMALL_MEDIUM; // Final Size Adaptive Weight Huge uint32_t high_auto_adaptive_weight_HUGE; uint32_t high_size_adaptive_weight_HUGE; uint32_t Mid_auto_adaptive_weight_HUGE; uint32_t Mid_size_adaptive_weight_HUGE; // Final Size Adaptive Weight Big uint32_t high_auto_adaptive_weight_BIG; uint32_t high_size_adaptive_weight_BIG; uint32_t Mid_auto_adaptive_weight_BIG; uint32_t Mid_size_adaptive_weight_BIG; // Final Size Adaptive Weight Medium uint32_t high_auto_adaptive_weight_MEDIUM; uint32_t high_size_adaptive_weight_MEDIUM; uint32_t Mid_auto_adaptive_weight_MEDIUM; uint32_t Mid_size_adaptive_weight_MEDIUM; // Final Size Adaptive Weight Small uint32_t high_auto_adaptive_weight_SMALL; uint32_t high_size_adaptive_weight_SMALL; uint32_t Mid_auto_adaptive_weight_SMALL; uint32_t Mid_size_adaptive_weight_SMALL; // Config uint32_t FILTER_HIST_EN; uint32_t FREQ_EXTRACT_ENHANCE; // Frequency Weighting uint32_t freq_D_weighting; uint32_t freq_H_weighting; uint32_t freq_L_weighting; uint32_t freq_M_weighting; // Frequency Weighting Final uint32_t freq_D_final_weighting; uint32_t freq_L_final_weighting; uint32_t freq_M_final_weighting; uint32_t freq_WH_final_weighting; uint32_t SIZE_PARAMETER; // Luma Chroma Parameters uint32_t chroma_high_gain; uint32_t chroma_high_index; uint32_t chroma_low_gain; uint32_t chroma_low_index; uint32_t luma_high_gain; uint32_t luma_high_index; uint32_t luma_low_gain; uint32_t luma_low_index; uint32_t Chroma_adaptive_mode; uint32_t Chroma_shift; uint32_t Luma_adaptive_mode; uint32_t Luma_shift; // Base Black & White edges uint32_t class_0_positive_gain; uint32_t class_0_negative_gain; }; struct DISP_CLARITY_REG { struct DISP_MDP_AAL_CLARITY_REG mdp_aal_clarity_regs; struct DISP_TDSHP_CLARITY_REG disp_tdshp_clarity_regs; }; struct drm_mtk_channel_hist { unsigned int channel_id; enum MTK_DRM_CHIST_COLOR_FORMT color_format; unsigned int hist[256]; unsigned int bin_count; }; struct drm_mtk_chist_info { unsigned int present_fence; unsigned int device_id; enum MTK_DRM_CHIST_CALLER caller; unsigned int get_channel_count; struct drm_mtk_channel_hist channel_hist[MTK_DRM_DISP_CHIST_CHANNEL_COUNT]; unsigned int lcm_width; unsigned int lcm_height; }; struct drm_mtk_channel_config { bool enabled; enum MTK_DRM_CHIST_COLOR_FORMT color_format; unsigned int bin_count; unsigned int channel_id; unsigned int blk_width; unsigned int blk_height; unsigned int roi_start_x; unsigned int roi_start_y; unsigned int roi_end_x; unsigned int roi_end_y; }; struct drm_mtk_chist_caps { unsigned int device_id; unsigned int support_color; unsigned int lcm_width; unsigned int lcm_height; struct drm_mtk_channel_config chist_config[MTK_DRM_DISP_CHIST_CHANNEL_COUNT]; }; struct drm_mtk_chist_config { unsigned int device_id; unsigned int lcm_color_mode; unsigned int config_channel_count; enum MTK_DRM_CHIST_CALLER caller; struct drm_mtk_channel_config chist_config[MTK_DRM_DISP_CHIST_CHANNEL_COUNT]; }; struct drm_mtk_ccorr_caps { unsigned int ccorr_bit; unsigned int ccorr_number; unsigned int ccorr_linear;//1st byte:high 4 bit:CCORR1,low 4 bit:CCORR0 }; struct mtk_drm_pq_caps_info { struct drm_mtk_ccorr_caps ccorr_caps; }; struct mtk_drm_conn_caps { unsigned int lcm_degree; int lcm_color_mode; }; #define MAX_MODES 30 struct mtk_drm_connector_caps { struct mtk_drm_conn_caps conn_caps; unsigned int width_after_pq[MAX_MODES]; unsigned int height_after_pq[MAX_MODES]; }; enum SWITCH_MODE_DELAY { DELAY_INVAL = 0, DELAY_0, DELAY_1, DELAY_2, DELAY_3, DELAY_4, DELAY_5, DELAY_6, DELAY_7, DELAY_8, DELAY_9, DELAY_10, }; struct mtk_drm_mode_ext_info { unsigned int crtc_id; unsigned int mode_num; unsigned int *total_offset; unsigned int *real_te_duration; enum SWITCH_MODE_DELAY **switch_mode_delay; unsigned int idle_fps; }; struct DISP_AAL_ESS20_SPECT_PARAM{ unsigned int ELVSSPN; unsigned int ClarityGain; /* 10-bit ; [0,1023] */ unsigned int flag;// }; #define DRECOLOR_SGY_Y_ENTRY 5 #define DRECOLOR_SGY_HUE_NUM 20 #define DRECOLOR_LSP_CNT 8 struct DISP_AAL_DRECOLOR_REG { unsigned int sgy_en; unsigned int sgy_out_gain[DRECOLOR_SGY_Y_ENTRY][DRECOLOR_SGY_HUE_NUM]; unsigned int lsp_en; unsigned int lsp_out_setting[DRECOLOR_LSP_CNT]; }; struct DISP_AAL_DRECOLOR_PARAM { bool drecolor_sel; struct DISP_AAL_DRECOLOR_REG drecolor_reg; }; enum SET_BL_EXT_TYPE { SET_BACKLIGHT_LEVEL, SET_ELVSS_PN, ENABLE_DYN_ELVSS, DISABLE_DYN_ELVSS, }; enum MTK_DRM_ODDMR_CTL_CMD { MTK_DRM_ODDMR_OD_INIT = 0, MTK_DRM_ODDMR_OD_ENABLE = 1, MTK_DRM_ODDMR_OD_DISABLE = 2, MTK_DRM_ODDMR_DMR_INIT = 3, MTK_DRM_ODDMR_DMR_ENABLE = 4, MTK_DRM_ODDMR_DMR_DISABLE = 5, MTK_DRM_ODDMR_LOAD_PARAM = 6, MTK_DRM_ODDMR_OD_READ_SW_REG = 7, MTK_DRM_ODDMR_OD_WRITE_SW_REG = 8, MTK_DRM_ODDMR_OD_USER_GAIN = 9, MTK_DRM_ODDMR_REMAP_ENABLE = 10, MTK_DRM_ODDMR_REMAP_DISABLE = 11, MTK_DRM_ODDMR_REMAP_TARGET = 12, MTK_DRM_ODDMR_DBI_NORMAL_COUNTING_CTL = 13, MTK_DRM_ODDMR_DBI_IRDROP_ENABLE = 14, MTK_DRM_ODDMR_DBI_SET_GAIN_RATIO = 15, }; struct mtk_drm_oddmr_ctl { enum MTK_DRM_ODDMR_CTL_CMD cmd; uint32_t size; uint8_t *data; }; struct mtk_drm_oddmr_param { uint32_t head_id; uint32_t size; uint8_t *data; uint32_t checksum; }; //pq config common ioctl struct mtk_drm_pq_config_ctl { __u32 crtc_id; __u8 check_trigger; __u8 len; void *data; }; struct mtk_drm_pq_param { __u32 cmd; __u32 size; void *data; }; struct mtk_drm_pq_proxy_ctl { __u32 crtc_id; __u32 cmd; __u32 size; __u32 extra_size; void *data; void *extra_data; }; enum mtk_pq_module_type { MTK_DISP_PQ_COLOR, MTK_DISP_PQ_DITHER, MTK_DISP_PQ_CCORR, MTK_DISP_PQ_AAL, MTK_DISP_PQ_GAMMA, MTK_DISP_PQ_CHIST, MTK_DISP_PQ_C3D, MTK_DISP_PQ_TDSHP, MTK_DISP_PQ_DMR, MTK_DISP_PQ_DBI, MTK_DISP_VIRTUAL_TYPE, MTK_DISP_PQ_TYPE_MAX = 65535, }; enum mtk_pq_frame_cfg_cmd { PQ_CMD_INVALID, PQ_AAL_EVENTCTL, PQ_AAL_INIT_REG, PQ_AAL_SET_ESS20_SPECT_PARAM, PQ_AAL_SET_PARAM, PQ_AAL_INIT_DRE30, PQ_AAL_CLARITY_SET_REG, PQ_GAMMA_SET_GAMMALUT = 100, PQ_GAMMA_SET_12BIT_GAMMALUT, PQ_GAMMA_BYPASS_GAMMA, PQ_GAMMA_DISABLE_MUL_EN, PQ_CHIST_CONFIG = 200, PQ_COLOR_MUTEX_CONTROL = 300, PQ_COLOR_BYPASS, PQ_COLOR_SET_PQINDEX, PQ_COLOR_SET_PQPARAM, PQ_COLOR_WRITE_REG, PQ_COLOR_WRITE_SW_REG, PQ_COLOR_SET_COLOR_REG, PQ_COLOR_SET_WINDOW, PQ_COLOR_DRECOLOR_SET_PARAM, PQ_CCORR_EVENTCTL = 400, PQ_CCORR_SUPPORT_COLOR_MATRIX, PQ_CCORR_SET_CCORR, PQ_CCORR_AIBLD_CV_MODE, PQ_CCORR_SET_PQ_CAPS, PQ_C3D_EVENTCTL = 500, PQ_C3D_BYPASS, PQ_C3D_SET_LUT, PQ_TDSHP_SET_REG = 600, PQ_DITHER_SET_DITHER_PARAM = 700, PQ_DBI_LOAD_PARAM = 800, PQ_DBI_LOAD_TB, PQ_DBI_ENABLE, PQ_DBI_DISABLE, PQ_DBI_REMAP_TARGET, PQ_DBI_REMAP_CHG, PQ_DBI_REMAP_ENABLE, PQ_DBI_REMAP_DISABLE, PQ_DBI_SET_GAIN_RATIO, PQ_VIRTUAL_SET_PROPERTY = 900, PQ_VIRTUAL_CHECK_TRIGGER = 901, PQ_VIRTUAL_RELAY_ENGINES, /* Get cmd begin */ /* Notice: * Command for getting must be added after the PQ_GET_CMD_START. * Otherwise, the func of 'copy_to_user' will not be called. */ PQ_GET_CMD_START = 60000, PQ_AAL_GET_HIST, PQ_AAL_GET_SIZE, PQ_AAL_SET_TRIGGER_STATE, PQ_AAL_GET_BASE_VOLTAGE, PQ_CHIST_GET = 60100, PQ_COLOR_READ_REG = 60200, PQ_COLOR_READ_SW_REG, PQ_CCORR_GET_IRQ = 60300, PQ_CCORR_GET_PQ_CAPS, PQ_C3D_GET_IRQ = 60400, PQ_C3D_GET_IRQ_STATUS, PQ_C3D_GET_BIN_NUM, PQ_TDSHP_GET_SIZE = 60500, PQ_DMR_INIT = 60600, PQ_DMR_ENABLE, PQ_DMR_DISABLE, PQ_DBI_GET_HW_ID, PQ_DBI_GET_WIDTH, PQ_DBI_GET_HEIGHT, PQ_DBI_GET_DBV, PQ_DBI_GET_FPS, PQ_DBI_GET_SCP, PQ_VIRTUAL_GET_MASTER_INFO = 60700, PQ_VIRTUAL_GET_IRQ, PQ_VIRTUAL_WAIT_CRTC_READY, PQ_VIRTUAL_GET_PIXEL_TYPE_BY_FENCE, PQ_CMD_MAX = 65535, }; enum mtk_pq_relay_engine { MTK_DISP_PQ_COLOR_RELAY = 0x1, MTK_DISP_PQ_CCORR_RELAY = 0x2, MTK_DISP_PQ_C3D_RELAY = 0x4, MTK_DISP_PQ_TDSHP_RELAY = 0x8, MTK_DISP_PQ_AAL_RELAY = 0x10, MTK_DISP_PQ_DMDP_AAL_RELAY = 0x20, MTK_DISP_PQ_GAMMA_RELAY = 0x40, MTK_DISP_PQ_DITHER_RELAY = 0x80, MTK_DISP_PQ_CHIST_RELAY = 0x100, }; struct mtk_pq_relay_enable { bool enable; bool wait_hw_config_done; uint32_t relay_engines; }; enum mtk_pq_aal_eventctl { AAL_EVENT_EN = 0x1, AAL_EVENT_STOP = 0x2, }; struct mtk_hdmi_enable { bool enable; }; struct mtk_hdmi_info { unsigned int edid_sink_colorimetry; unsigned char edid_sink_rgb_color_bit; unsigned char edid_sink_ycbcr_color_bit; unsigned char ui1_sink_dc420_color_bit; unsigned short edid_sink_max_tmds_clock; unsigned short edid_sink_max_tmds_character_rate; unsigned char edid_sink_support_dynamic_hdr; unsigned char edid_sink_support_static_hdr; }; #define GET_PANELS_STR_LEN 64 #define MAX_CRTC_CNT 10 struct mtk_drm_panels_info { int connector_cnt; int default_connector_id; unsigned int *connector_obj_id; unsigned int **possible_crtc; char **panel_name; unsigned int *panel_id; }; struct DISP_PANEL_BASE_VOLTAGE{ unsigned char AnodeBase[MAX_FPS_PN]; unsigned char AnodeOffset[MAX_DBV_PN]; unsigned char ELVSSBase[MAX_DBV_PN]; bool flag; unsigned int DDICDbvPn; unsigned int DDICFpsPn; }; enum MTK_PANEL_SPR_MODE { MTK_PANEL_RGBG_BGRG_TYPE = 0, MTK_PANEL_BGRG_RGBG_TYPE, MTK_PANEL_RGBRGB_BGRBGR_TYPE, MTK_PANEL_BGRBGR_RGBRGB_TYPE, MTK_PANEL_RGBRGB_BRGBRG_TYPE, MTK_PANEL_BRGBRG_RGBRGB_TYPE, MTK_PANEL_EXT_TYPE, MTK_PANEL_SPR_OFF_TYPE = 0x1000, MTK_PANEL_INVALID_TYPE = 0xFFFF, }; struct mtk_pixel_type_fence { unsigned int fence_idx; unsigned int type; unsigned int secure; }; #define DRM_IOCTL_MTK_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GEM_CREATE, struct drm_mtk_gem_create) #define DRM_IOCTL_MTK_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GEM_MAP_OFFSET, struct drm_mtk_gem_map_off) #define DRM_IOCTL_MTK_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GEM_SUBMIT, struct drm_mtk_gem_submit) #define DRM_IOCTL_MTK_SESSION_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SESSION_CREATE, struct drm_mtk_session) #define DRM_IOCTL_MTK_SESSION_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SESSION_DESTROY, struct drm_mtk_session) #define DRM_IOCTL_MTK_LAYERING_RULE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_LAYERING_RULE, struct drm_mtk_layering_info) #define DRM_IOCTL_MTK_CRTC_GETFENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_CRTC_GETFENCE, struct drm_mtk_fence) #define DRM_IOCTL_MTK_CRTC_FENCE_REL DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_CRTC_FENCE_REL, struct drm_mtk_fence) #define DRM_IOCTL_MTK_CRTC_GETSFFENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_CRTC_GETSFFENCE, struct drm_mtk_fence) #define DRM_IOCTL_MTK_MML_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_MML_GEM_SUBMIT, struct mml_submit) #define DRM_IOCTL_MTK_SET_MSYNC_PARAMS DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_MSYNC_PARAMS, struct msync_parameter_table) #define DRM_IOCTL_MTK_GET_MSYNC_PARAMS DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_MSYNC_PARAMS, struct msync_parameter_table) #define DRM_IOCTL_MTK_FACTORY_LCM_AUTO_TEST DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_FACTORY_LCM_AUTO_TEST, int) #define DRM_IOCTL_MTK_DRM_SET_LEASE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_DRM_SET_LEASE_INFO, int) #define DRM_IOCTL_MTK_DRM_GET_LEASE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_DRM_GET_LEASE_INFO, int) #define DRM_IOCTL_MTK_WAIT_REPAINT DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_WAIT_REPAINT, unsigned int) #define DRM_IOCTL_MTK_GET_DISPLAY_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_DISPLAY_CAPS, struct mtk_drm_disp_caps_info) #define DRM_IOCTL_MTK_SET_DDP_MODE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_DDP_MODE, unsigned int) #define DRM_IOCTL_MTK_GET_SESSION_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_SESSION_INFO, struct drm_mtk_session_info) #define DRM_IOCTL_MTK_GET_MASTER_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_MASTER_INFO, int) #define DRM_IOCTL_MTK_SET_12BIT_GAMMALUT DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_12BIT_GAMMALUT, DISP_GAMMA_12BIT_LUT_T) #define DRM_IOCTL_MTK_PQ_PERSIST_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_PQ_PERSIST_PROPERTY, unsigned int [32]) #define DRM_IOCTL_MTK_SET_CCORR DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_CCORR, DRM_DISP_CCORR_COEF_T) #define DRM_IOCTL_MTK_CCORR_EVENTCTL DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_CCORR_EVENTCTL, unsigned int) #define DRM_IOCTL_MTK_AIBLD_CV_MODE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_AIBLD_CV_MODE, bool) #define DRM_IOCTL_MTK_CCORR_GET_IRQ DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_CCORR_GET_IRQ, unsigned int) #define DRM_IOCTL_MTK_SET_GAMMALUT DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_GAMMALUT, DISP_GAMMA_LUT_T) #define DRM_IOCTL_MTK_SET_PQPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_PQPARAM, DISP_PQ_PARAM) #define DRM_IOCTL_MTK_SET_PQINDEX DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_PQINDEX, DISPLAY_PQ_T) #define DRM_IOCTL_MTK_SET_COLOR_REG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_COLOR_REG, DISPLAY_COLOR_REG_T) #define DRM_IOCTL_MTK_MUTEX_CONTROL DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_MUTEX_CONTROL, unsigned int) #define DRM_IOCTL_MTK_READ_REG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_READ_REG, DISP_READ_REG) #define DRM_IOCTL_MTK_WRITE_REG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_WRITE_REG, DISP_WRITE_REG) #define DRM_IOCTL_MTK_BYPASS_COLOR DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_BYPASS_COLOR, unsigned int) #define DRM_IOCTL_MTK_PQ_SET_WINDOW DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_PQ_SET_WINDOW, DISP_PQ_WIN_PARAM) #define DRM_IOCTL_MTK_GET_LCM_INDEX DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_LCM_INDEX, unsigned int) #define DRM_IOCTL_MTK_GET_PANELS_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_PANELS_INFO, struct mtk_drm_panels_info) #define DRM_IOCTL_MTK_SUPPORT_COLOR_TRANSFORM DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SUPPORT_COLOR_TRANSFORM, struct DISP_COLOR_TRANSFORM) #define DRM_IOCTL_MTK_READ_SW_REG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_READ_SW_REG, DISP_READ_REG) #define DRM_IOCTL_MTK_WRITE_SW_REG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_WRITE_SW_REG, DISP_WRITE_REG) // for Display TDSHP #define DRM_IOCTL_MTK_SET_DISP_TDSHP_REG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_DISP_TDSHP_REG, struct DISP_TDSHP_REG) #define DRM_IOCTL_MTK_DISP_TDSHP_GET_SIZE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_DISP_TDSHP_GET_SIZE, struct DISP_TDSHP_DISPLAY_SIZE) // for Display Clarity #define DRM_IOCTL_MTK_DISP_CLARITY_SET_REG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_DISP_CLARITY_SET_REG, struct DISP_CLARITY_REG) #define DRM_IOCTL_MTK_C3D_GET_BIN_NUM DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_C3D_GET_BIN_NUM, unsigned int) #define DRM_IOCTL_MTK_C3D_GET_IRQ DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_C3D_GET_IRQ, unsigned int) #define DRM_IOCTL_MTK_C3D_EVENTCTL DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_C3D_EVENTCTL, unsigned int) #define DRM_IOCTL_MTK_C3D_SET_LUT DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_C3D_SET_LUT, struct DISP_C3D_LUT) #define DRM_IOCTL_MTK_SET_BYPASS_C3D DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_BYPASS_C3D, unsigned int) #define DRM_IOCTL_MTK_GET_CHIST DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_CHIST, struct drm_mtk_chist_info) #define DRM_IOCTL_MTK_GET_CHIST_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_CHIST_CAPS, struct drm_mtk_chist_caps) #define DRM_IOCTL_MTK_SET_CHIST_CONFIG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_CHIST_CONFIG, struct drm_mtk_chist_config) #define DRM_IOCTL_MTK_SET_DITHER_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_DITHER_PARAM, struct DISP_DITHER_PARAM) #define DRM_IOCTL_MTK_BYPASS_DISP_GAMMA DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_BYPASS_DISP_GAMMA, unsigned int) #define DRM_IOCTL_MTK_AAL_INIT_REG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_AAL_INIT_REG, DISP_AAL_INITREG) #define DRM_IOCTL_MTK_AAL_GET_HIST DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_AAL_GET_HIST, DISP_AAL_HIST) #define DRM_IOCTL_MTK_AAL_SET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_AAL_SET_PARAM, DISP_AAL_PARAM) #define DRM_IOCTL_MTK_AAL_EVENTCTL DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_AAL_EVENTCTL, unsigned int) #define DRM_IOCTL_MTK_AAL_INIT_DRE30 DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_AAL_INIT_DRE30, DISP_DRE30_INIT) #define DRM_IOCTL_MTK_AAL_GET_SIZE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_AAL_GET_SIZE, DISP_AAL_DISPLAY_SIZE) #define DRM_IOCTL_MTK_AAL_SET_TRIGGER_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_AAL_SET_TRIGGER_STATE, struct DISP_AAL_TRIG_STATE) #define DRM_IOCTL_MTK_SEC_HND_TO_GEM_HND DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SEC_HND_TO_GEM_HND, struct drm_mtk_sec_gem_hnd) #define DRM_IOCTL_MTK_HDMI_GET_DEV_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_HDMI_GET_DEV_INFO, struct mtk_dispif_info) #define DRM_IOCTL_MTK_HDMI_AUDIO_ENABLE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_HDMI_AUDIO_ENABLE, unsigned int) #define DRM_IOCTL_MTK_HDMI_AUDIO_CONFIG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_HDMI_AUDIO_CONFIG, unsigned int) #define DRM_IOCTL_MTK_HDMI_GET_CAPABILITY DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_HDMI_GET_CAPABILITY, unsigned int) #define DRM_IOCTL_MTK_CRTC_GETPQFENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_CRTC_GETPQFENCE, struct drm_mtk_fence) #define DRM_IOCTL_MTK_CRTC_RELEASEPQFENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_CRTC_RELEASEPQFENCE, struct drm_mtk_fence) #define DRM_IOCTL_MTK_DEBUG_LOG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_DEBUG_LOG, int) #define DRM_IOCTL_MTK_GET_PQ_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_PQ_CAPS, struct mtk_drm_pq_caps_info) #define DRM_IOCTL_MTK_SET_PQ_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_PQ_CAPS, struct mtk_drm_pq_caps_info) #define DRM_IOCTL_MTK_KICK_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_KICK_IDLE, unsigned int) #define DRM_IOCTL_MTK_GET_MODE_EXT_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_GET_MODE_EXT_INFO, struct mtk_drm_mode_ext_info) #define DRM_IOCTL_MTK_HWVSYNC_ON DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_HWVSYNC_ON, unsigned int) #define DRM_IOCTL_MTK_ODDMR_LOAD_PARAM DRM_IOWR(DRM_COMMAND_BASE + \ DRM_MTK_ODDMR_LOAD_PARAM, struct mtk_drm_oddmr_param) #define DRM_IOCTL_MTK_ODDMR_CTL DRM_IOWR(DRM_COMMAND_BASE + \ DRM_MTK_ODDMR_CTL, struct mtk_drm_oddmr_ctl) #define DRM_IOCTL_MTK_AAL_SET_ESS20_SPECT_PARAM DRM_IOWR(DRM_COMMAND_BASE + \ DRM_MTK_AAL_SET_ESS20_SPECT_PARAM, struct DISP_AAL_ESS20_SPECT_PARAM) #define DRM_IOCTL_MTK_SET_GAMMA_MUL_DISABLE DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_SET_GAMMA_MUL_DISABLE, bool) #define DRM_IOCTL_MTK_PQ_FRAME_CONFIG DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_PQ_FRAME_CONFIG, struct mtk_drm_pq_config_ctl) #define DRM_IOCTL_MTK_PQ_PROXY_IOCTL DRM_IOWR(DRM_COMMAND_BASE + DRM_MTK_PQ_PROXY_IOCTL, struct mtk_drm_pq_proxy_ctl) #define MTK_DRM_FORMAT_DIM fourcc_code('D', ' ', '0', '0') #define DRM_FORMAT_MOD_VENDOR_MTK 0x0A #define DRM_FORMAT_MOD_MTK_PREMULTIPLIED fourcc_mod_code(MTK, 1) #define DRM_FORMAT_MOD_MTK_SECURE fourcc_mod_code(MTK, 2) #endif