390 lines
16 KiB
C
390 lines
16 KiB
C
/*
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* Copyright (c) 2018, Alliance for Open Media. All rights reserved
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*
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* This source code is subject to the terms of the BSD 2 Clause License and
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* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
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* was not distributed with this source code in the LICENSE file, you can
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* obtain it at www.aomedia.org/license/software. If the Alliance for Open
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* Media Patent License 1.0 was not distributed with this source code in the
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* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
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*/
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#include <tmmintrin.h>
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#include "config/aom_config.h"
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#include "config/aom_dsp_rtcd.h"
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#include "aom_dsp/blend.h"
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#include "aom/aom_integer.h"
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#include "aom_dsp/x86/synonyms.h"
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#include "aom_dsp/x86/masked_sad_intrin_ssse3.h"
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static INLINE unsigned int masked_sad32xh_avx2(
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const uint8_t *src_ptr, int src_stride, const uint8_t *a_ptr, int a_stride,
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const uint8_t *b_ptr, int b_stride, const uint8_t *m_ptr, int m_stride,
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int width, int height) {
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int x, y;
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__m256i res = _mm256_setzero_si256();
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const __m256i mask_max = _mm256_set1_epi8((1 << AOM_BLEND_A64_ROUND_BITS));
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const __m256i round_scale =
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_mm256_set1_epi16(1 << (15 - AOM_BLEND_A64_ROUND_BITS));
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for (y = 0; y < height; y++) {
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for (x = 0; x < width; x += 32) {
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const __m256i src = _mm256_lddqu_si256((const __m256i *)&src_ptr[x]);
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const __m256i a = _mm256_lddqu_si256((const __m256i *)&a_ptr[x]);
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const __m256i b = _mm256_lddqu_si256((const __m256i *)&b_ptr[x]);
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const __m256i m = _mm256_lddqu_si256((const __m256i *)&m_ptr[x]);
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const __m256i m_inv = _mm256_sub_epi8(mask_max, m);
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// Calculate 16 predicted pixels.
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// Note that the maximum value of any entry of 'pred_l' or 'pred_r'
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// is 64 * 255, so we have plenty of space to add rounding constants.
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const __m256i data_l = _mm256_unpacklo_epi8(a, b);
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const __m256i mask_l = _mm256_unpacklo_epi8(m, m_inv);
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__m256i pred_l = _mm256_maddubs_epi16(data_l, mask_l);
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pred_l = _mm256_mulhrs_epi16(pred_l, round_scale);
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const __m256i data_r = _mm256_unpackhi_epi8(a, b);
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const __m256i mask_r = _mm256_unpackhi_epi8(m, m_inv);
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__m256i pred_r = _mm256_maddubs_epi16(data_r, mask_r);
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pred_r = _mm256_mulhrs_epi16(pred_r, round_scale);
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const __m256i pred = _mm256_packus_epi16(pred_l, pred_r);
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res = _mm256_add_epi32(res, _mm256_sad_epu8(pred, src));
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}
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src_ptr += src_stride;
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a_ptr += a_stride;
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b_ptr += b_stride;
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m_ptr += m_stride;
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}
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// At this point, we have two 32-bit partial SADs in lanes 0 and 2 of 'res'.
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res = _mm256_shuffle_epi32(res, 0xd8);
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res = _mm256_permute4x64_epi64(res, 0xd8);
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res = _mm256_hadd_epi32(res, res);
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res = _mm256_hadd_epi32(res, res);
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int32_t sad = _mm256_extract_epi32(res, 0);
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return sad;
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}
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static INLINE __m256i xx_loadu2_m128i(const void *hi, const void *lo) {
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__m128i a0 = _mm_lddqu_si128((const __m128i *)(lo));
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__m128i a1 = _mm_lddqu_si128((const __m128i *)(hi));
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__m256i a = _mm256_castsi128_si256(a0);
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return _mm256_inserti128_si256(a, a1, 1);
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}
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static INLINE unsigned int masked_sad16xh_avx2(
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const uint8_t *src_ptr, int src_stride, const uint8_t *a_ptr, int a_stride,
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const uint8_t *b_ptr, int b_stride, const uint8_t *m_ptr, int m_stride,
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int height) {
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int y;
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__m256i res = _mm256_setzero_si256();
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const __m256i mask_max = _mm256_set1_epi8((1 << AOM_BLEND_A64_ROUND_BITS));
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const __m256i round_scale =
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_mm256_set1_epi16(1 << (15 - AOM_BLEND_A64_ROUND_BITS));
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for (y = 0; y < height; y += 2) {
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const __m256i src = xx_loadu2_m128i(src_ptr + src_stride, src_ptr);
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const __m256i a = xx_loadu2_m128i(a_ptr + a_stride, a_ptr);
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const __m256i b = xx_loadu2_m128i(b_ptr + b_stride, b_ptr);
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const __m256i m = xx_loadu2_m128i(m_ptr + m_stride, m_ptr);
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const __m256i m_inv = _mm256_sub_epi8(mask_max, m);
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// Calculate 16 predicted pixels.
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// Note that the maximum value of any entry of 'pred_l' or 'pred_r'
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// is 64 * 255, so we have plenty of space to add rounding constants.
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const __m256i data_l = _mm256_unpacklo_epi8(a, b);
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const __m256i mask_l = _mm256_unpacklo_epi8(m, m_inv);
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__m256i pred_l = _mm256_maddubs_epi16(data_l, mask_l);
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pred_l = _mm256_mulhrs_epi16(pred_l, round_scale);
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const __m256i data_r = _mm256_unpackhi_epi8(a, b);
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const __m256i mask_r = _mm256_unpackhi_epi8(m, m_inv);
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__m256i pred_r = _mm256_maddubs_epi16(data_r, mask_r);
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pred_r = _mm256_mulhrs_epi16(pred_r, round_scale);
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const __m256i pred = _mm256_packus_epi16(pred_l, pred_r);
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res = _mm256_add_epi32(res, _mm256_sad_epu8(pred, src));
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src_ptr += src_stride << 1;
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a_ptr += a_stride << 1;
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b_ptr += b_stride << 1;
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m_ptr += m_stride << 1;
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}
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// At this point, we have two 32-bit partial SADs in lanes 0 and 2 of 'res'.
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res = _mm256_shuffle_epi32(res, 0xd8);
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res = _mm256_permute4x64_epi64(res, 0xd8);
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res = _mm256_hadd_epi32(res, res);
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res = _mm256_hadd_epi32(res, res);
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int32_t sad = _mm256_extract_epi32(res, 0);
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return sad;
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}
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static INLINE unsigned int aom_masked_sad_avx2(
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const uint8_t *src, int src_stride, const uint8_t *ref, int ref_stride,
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const uint8_t *second_pred, const uint8_t *msk, int msk_stride,
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int invert_mask, int m, int n) {
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unsigned int sad;
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if (!invert_mask) {
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switch (m) {
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case 4:
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sad = aom_masked_sad4xh_ssse3(src, src_stride, ref, ref_stride,
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second_pred, m, msk, msk_stride, n);
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break;
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case 8:
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sad = aom_masked_sad8xh_ssse3(src, src_stride, ref, ref_stride,
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second_pred, m, msk, msk_stride, n);
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break;
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case 16:
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sad = masked_sad16xh_avx2(src, src_stride, ref, ref_stride, second_pred,
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m, msk, msk_stride, n);
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break;
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default:
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sad = masked_sad32xh_avx2(src, src_stride, ref, ref_stride, second_pred,
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m, msk, msk_stride, m, n);
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break;
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}
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} else {
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switch (m) {
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case 4:
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sad = aom_masked_sad4xh_ssse3(src, src_stride, second_pred, m, ref,
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ref_stride, msk, msk_stride, n);
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break;
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case 8:
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sad = aom_masked_sad8xh_ssse3(src, src_stride, second_pred, m, ref,
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ref_stride, msk, msk_stride, n);
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break;
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case 16:
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sad = masked_sad16xh_avx2(src, src_stride, second_pred, m, ref,
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ref_stride, msk, msk_stride, n);
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break;
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default:
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sad = masked_sad32xh_avx2(src, src_stride, second_pred, m, ref,
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ref_stride, msk, msk_stride, m, n);
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break;
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}
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}
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return sad;
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}
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#define MASKSADMXN_AVX2(m, n) \
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unsigned int aom_masked_sad##m##x##n##_avx2( \
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const uint8_t *src, int src_stride, const uint8_t *ref, int ref_stride, \
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const uint8_t *second_pred, const uint8_t *msk, int msk_stride, \
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int invert_mask) { \
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return aom_masked_sad_avx2(src, src_stride, ref, ref_stride, second_pred, \
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msk, msk_stride, invert_mask, m, n); \
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}
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MASKSADMXN_AVX2(4, 4)
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MASKSADMXN_AVX2(4, 8)
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MASKSADMXN_AVX2(8, 4)
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MASKSADMXN_AVX2(8, 8)
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MASKSADMXN_AVX2(8, 16)
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MASKSADMXN_AVX2(16, 8)
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MASKSADMXN_AVX2(16, 16)
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MASKSADMXN_AVX2(16, 32)
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MASKSADMXN_AVX2(32, 16)
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MASKSADMXN_AVX2(32, 32)
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MASKSADMXN_AVX2(32, 64)
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MASKSADMXN_AVX2(64, 32)
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MASKSADMXN_AVX2(64, 64)
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MASKSADMXN_AVX2(64, 128)
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MASKSADMXN_AVX2(128, 64)
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MASKSADMXN_AVX2(128, 128)
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MASKSADMXN_AVX2(4, 16)
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MASKSADMXN_AVX2(16, 4)
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MASKSADMXN_AVX2(8, 32)
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MASKSADMXN_AVX2(32, 8)
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MASKSADMXN_AVX2(16, 64)
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MASKSADMXN_AVX2(64, 16)
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static INLINE unsigned int highbd_masked_sad8xh_avx2(
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const uint8_t *src8, int src_stride, const uint8_t *a8, int a_stride,
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const uint8_t *b8, int b_stride, const uint8_t *m_ptr, int m_stride,
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int height) {
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const uint16_t *src_ptr = CONVERT_TO_SHORTPTR(src8);
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const uint16_t *a_ptr = CONVERT_TO_SHORTPTR(a8);
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const uint16_t *b_ptr = CONVERT_TO_SHORTPTR(b8);
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int y;
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__m256i res = _mm256_setzero_si256();
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const __m256i mask_max = _mm256_set1_epi16((1 << AOM_BLEND_A64_ROUND_BITS));
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const __m256i round_const =
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_mm256_set1_epi32((1 << AOM_BLEND_A64_ROUND_BITS) >> 1);
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const __m256i one = _mm256_set1_epi16(1);
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for (y = 0; y < height; y += 2) {
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const __m256i src = xx_loadu2_m128i(src_ptr + src_stride, src_ptr);
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const __m256i a = xx_loadu2_m128i(a_ptr + a_stride, a_ptr);
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const __m256i b = xx_loadu2_m128i(b_ptr + b_stride, b_ptr);
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// Zero-extend mask to 16 bits
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const __m256i m = _mm256_cvtepu8_epi16(_mm_unpacklo_epi64(
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_mm_loadl_epi64((const __m128i *)(m_ptr)),
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_mm_loadl_epi64((const __m128i *)(m_ptr + m_stride))));
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const __m256i m_inv = _mm256_sub_epi16(mask_max, m);
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const __m256i data_l = _mm256_unpacklo_epi16(a, b);
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const __m256i mask_l = _mm256_unpacklo_epi16(m, m_inv);
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__m256i pred_l = _mm256_madd_epi16(data_l, mask_l);
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pred_l = _mm256_srai_epi32(_mm256_add_epi32(pred_l, round_const),
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AOM_BLEND_A64_ROUND_BITS);
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const __m256i data_r = _mm256_unpackhi_epi16(a, b);
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const __m256i mask_r = _mm256_unpackhi_epi16(m, m_inv);
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__m256i pred_r = _mm256_madd_epi16(data_r, mask_r);
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pred_r = _mm256_srai_epi32(_mm256_add_epi32(pred_r, round_const),
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AOM_BLEND_A64_ROUND_BITS);
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// Note: the maximum value in pred_l/r is (2^bd)-1 < 2^15,
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// so it is safe to do signed saturation here.
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const __m256i pred = _mm256_packs_epi32(pred_l, pred_r);
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// There is no 16-bit SAD instruction, so we have to synthesize
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// an 8-element SAD. We do this by storing 4 32-bit partial SADs,
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// and accumulating them at the end
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const __m256i diff = _mm256_abs_epi16(_mm256_sub_epi16(pred, src));
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res = _mm256_add_epi32(res, _mm256_madd_epi16(diff, one));
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src_ptr += src_stride << 1;
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a_ptr += a_stride << 1;
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b_ptr += b_stride << 1;
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m_ptr += m_stride << 1;
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}
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// At this point, we have four 32-bit partial SADs stored in 'res'.
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res = _mm256_hadd_epi32(res, res);
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res = _mm256_hadd_epi32(res, res);
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int sad = _mm256_extract_epi32(res, 0) + _mm256_extract_epi32(res, 4);
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return sad;
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}
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static INLINE unsigned int highbd_masked_sad16xh_avx2(
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const uint8_t *src8, int src_stride, const uint8_t *a8, int a_stride,
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const uint8_t *b8, int b_stride, const uint8_t *m_ptr, int m_stride,
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int width, int height) {
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const uint16_t *src_ptr = CONVERT_TO_SHORTPTR(src8);
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const uint16_t *a_ptr = CONVERT_TO_SHORTPTR(a8);
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const uint16_t *b_ptr = CONVERT_TO_SHORTPTR(b8);
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int x, y;
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__m256i res = _mm256_setzero_si256();
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const __m256i mask_max = _mm256_set1_epi16((1 << AOM_BLEND_A64_ROUND_BITS));
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const __m256i round_const =
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_mm256_set1_epi32((1 << AOM_BLEND_A64_ROUND_BITS) >> 1);
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const __m256i one = _mm256_set1_epi16(1);
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for (y = 0; y < height; y++) {
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for (x = 0; x < width; x += 16) {
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const __m256i src = _mm256_lddqu_si256((const __m256i *)&src_ptr[x]);
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const __m256i a = _mm256_lddqu_si256((const __m256i *)&a_ptr[x]);
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const __m256i b = _mm256_lddqu_si256((const __m256i *)&b_ptr[x]);
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// Zero-extend mask to 16 bits
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const __m256i m =
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_mm256_cvtepu8_epi16(_mm_lddqu_si128((const __m128i *)&m_ptr[x]));
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const __m256i m_inv = _mm256_sub_epi16(mask_max, m);
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const __m256i data_l = _mm256_unpacklo_epi16(a, b);
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const __m256i mask_l = _mm256_unpacklo_epi16(m, m_inv);
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__m256i pred_l = _mm256_madd_epi16(data_l, mask_l);
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pred_l = _mm256_srai_epi32(_mm256_add_epi32(pred_l, round_const),
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AOM_BLEND_A64_ROUND_BITS);
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const __m256i data_r = _mm256_unpackhi_epi16(a, b);
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const __m256i mask_r = _mm256_unpackhi_epi16(m, m_inv);
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__m256i pred_r = _mm256_madd_epi16(data_r, mask_r);
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pred_r = _mm256_srai_epi32(_mm256_add_epi32(pred_r, round_const),
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AOM_BLEND_A64_ROUND_BITS);
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// Note: the maximum value in pred_l/r is (2^bd)-1 < 2^15,
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// so it is safe to do signed saturation here.
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const __m256i pred = _mm256_packs_epi32(pred_l, pred_r);
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// There is no 16-bit SAD instruction, so we have to synthesize
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// an 8-element SAD. We do this by storing 4 32-bit partial SADs,
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// and accumulating them at the end
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const __m256i diff = _mm256_abs_epi16(_mm256_sub_epi16(pred, src));
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res = _mm256_add_epi32(res, _mm256_madd_epi16(diff, one));
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}
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src_ptr += src_stride;
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a_ptr += a_stride;
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b_ptr += b_stride;
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m_ptr += m_stride;
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}
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// At this point, we have four 32-bit partial SADs stored in 'res'.
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res = _mm256_hadd_epi32(res, res);
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res = _mm256_hadd_epi32(res, res);
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int sad = _mm256_extract_epi32(res, 0) + _mm256_extract_epi32(res, 4);
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return sad;
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}
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static INLINE unsigned int aom_highbd_masked_sad_avx2(
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const uint8_t *src, int src_stride, const uint8_t *ref, int ref_stride,
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const uint8_t *second_pred, const uint8_t *msk, int msk_stride,
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int invert_mask, int m, int n) {
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unsigned int sad;
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if (!invert_mask) {
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switch (m) {
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case 4:
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sad =
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aom_highbd_masked_sad4xh_ssse3(src, src_stride, ref, ref_stride,
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second_pred, m, msk, msk_stride, n);
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break;
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case 8:
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sad = highbd_masked_sad8xh_avx2(src, src_stride, ref, ref_stride,
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second_pred, m, msk, msk_stride, n);
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break;
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default:
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sad = highbd_masked_sad16xh_avx2(src, src_stride, ref, ref_stride,
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second_pred, m, msk, msk_stride, m, n);
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break;
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}
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} else {
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switch (m) {
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case 4:
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sad =
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aom_highbd_masked_sad4xh_ssse3(src, src_stride, second_pred, m, ref,
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ref_stride, msk, msk_stride, n);
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break;
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case 8:
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sad = highbd_masked_sad8xh_avx2(src, src_stride, second_pred, m, ref,
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ref_stride, msk, msk_stride, n);
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break;
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default:
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sad = highbd_masked_sad16xh_avx2(src, src_stride, second_pred, m, ref,
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ref_stride, msk, msk_stride, m, n);
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break;
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}
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}
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return sad;
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}
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#define HIGHBD_MASKSADMXN_AVX2(m, n) \
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unsigned int aom_highbd_masked_sad##m##x##n##_avx2( \
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const uint8_t *src8, int src_stride, const uint8_t *ref8, \
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int ref_stride, const uint8_t *second_pred8, const uint8_t *msk, \
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int msk_stride, int invert_mask) { \
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return aom_highbd_masked_sad_avx2(src8, src_stride, ref8, ref_stride, \
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second_pred8, msk, msk_stride, \
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invert_mask, m, n); \
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}
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HIGHBD_MASKSADMXN_AVX2(4, 4)
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HIGHBD_MASKSADMXN_AVX2(4, 8)
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HIGHBD_MASKSADMXN_AVX2(8, 4)
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HIGHBD_MASKSADMXN_AVX2(8, 8)
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HIGHBD_MASKSADMXN_AVX2(8, 16)
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HIGHBD_MASKSADMXN_AVX2(16, 8)
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HIGHBD_MASKSADMXN_AVX2(16, 16)
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HIGHBD_MASKSADMXN_AVX2(16, 32)
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HIGHBD_MASKSADMXN_AVX2(32, 16)
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HIGHBD_MASKSADMXN_AVX2(32, 32)
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HIGHBD_MASKSADMXN_AVX2(32, 64)
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HIGHBD_MASKSADMXN_AVX2(64, 32)
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HIGHBD_MASKSADMXN_AVX2(64, 64)
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HIGHBD_MASKSADMXN_AVX2(64, 128)
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HIGHBD_MASKSADMXN_AVX2(128, 64)
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HIGHBD_MASKSADMXN_AVX2(128, 128)
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HIGHBD_MASKSADMXN_AVX2(4, 16)
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HIGHBD_MASKSADMXN_AVX2(16, 4)
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HIGHBD_MASKSADMXN_AVX2(8, 32)
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HIGHBD_MASKSADMXN_AVX2(32, 8)
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HIGHBD_MASKSADMXN_AVX2(16, 64)
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HIGHBD_MASKSADMXN_AVX2(64, 16)
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