432 lines
11 KiB
C
432 lines
11 KiB
C
/**
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* Copyright (C) 2018 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions vand
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* limitations under the License.
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*/
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#ifndef DRM_ENVIROMENT_H
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#include <stdint.h>
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#include <unistd.h>
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enum drm_map_type {
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_DRM_FRAME_BUFFER = 0,
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_DRM_REGISTERS = 1,
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_DRM_SHM = 2,
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_DRM_AGP = 3,
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_DRM_SCATTER_GATHER = 4,
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_DRM_CONSISTENT = 5,
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};
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enum drm_map_flags {
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_DRM_RESTRICTED = 0x01,
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_DRM_READ_ONLY = 0x02,
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_DRM_LOCKED = 0x04,
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_DRM_KERNEL = 0x08,
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_DRM_WRITE_COMBINING = 0x10,
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_DRM_CONTAINS_LOCK = 0x20,
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_DRM_REMOVABLE = 0x40,
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_DRM_DRIVER = 0x80
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};
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enum host1x_class {
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HOST1X_CLASS_HOST1X = 0x1,
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HOST1X_CLASS_NVENC = 0x21,
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HOST1X_CLASS_VI = 0x30,
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HOST1X_CLASS_ISPA = 0x32,
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HOST1X_CLASS_ISPB = 0x34,
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HOST1X_CLASS_GR2D = 0x51,
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HOST1X_CLASS_GR2D_SB = 0x52,
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HOST1X_CLASS_VIC = 0x5D,
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HOST1X_CLASS_GR3D = 0x60,
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HOST1X_CLASS_NVJPG = 0xC0,
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HOST1X_CLASS_NVDEC = 0xF0,
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};
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struct drm_map {
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unsigned long offset;
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unsigned long size;
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enum drm_map_type type;
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enum drm_map_flags flags;
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void* handle;
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int mtrr;
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};
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struct drm_version {
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int version_major;
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int version_minor;
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int version_patchlevel;
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size_t name_len;
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char* name;
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size_t date_len;
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char* date;
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size_t desc_len;
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char* desc;
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};
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struct drm_buf_desc {
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int count;
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int size;
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int low_mark;
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int high_mark;
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enum {
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_DRM_PAGE_ALIGN = 0x01,
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_DRM_AGP_BUFFER = 0x02,
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_DRM_SG_BUFFER = 0x04,
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_DRM_FB_BUFFER = 0x08,
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_DRM_PCI_BUFFER_RO = 0x10
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} flags;
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unsigned long agp_start;
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};
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struct drm_buf_info {
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int count;
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struct drm_buf_desc* list;
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};
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struct drm_buf_free {
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int count;
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int* list;
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};
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struct drm_nouveau_gem_info {
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uint32_t handle;
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uint32_t domain;
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uint64_t size;
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uint64_t offset;
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uint64_t map_handle;
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uint32_t tile_mode;
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uint32_t tile_flags;
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};
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struct drm_nouveau_gem_map {
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uint32_t handle;
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uint32_t domain;
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uint64_t offset;
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uint64_t delta;
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uint64_t length;
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uint32_t tile_mode;
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uint32_t tile_flags;
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};
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struct drm_nouveau_gem_unmap {
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uint32_t handle;
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uint32_t pad;
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uint64_t offset;
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uint64_t delta;
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uint64_t length;
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};
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struct drm_nouveau_gem_new {
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struct drm_nouveau_gem_info info;
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uint32_t channel_hint;
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uint32_t align;
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};
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struct drm_nouveau_gem_pushbuf {
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uint32_t channel;
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uint32_t nr_buffers;
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uint64_t buffers;
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uint32_t nr_relocs;
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uint32_t nr_push;
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uint64_t relocs;
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uint64_t push;
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uint32_t suffix0;
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uint32_t suffix1;
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uint64_t vram_available;
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uint64_t gart_available;
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};
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struct drm_nouveau_gem_pushbuf_bo_presumed {
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uint32_t valid;
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uint32_t domain;
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uint64_t offset;
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};
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struct drm_nouveau_gem_pushbuf_bo {
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uint64_t user_priv;
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uint32_t handle;
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uint32_t read_domains;
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uint32_t write_domains;
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uint32_t valid_domains;
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struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
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};
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struct drm_nouveau_channel_alloc {
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uint32_t fb_ctxdma_handle;
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uint32_t tt_ctxdma_handle;
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int channel;
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uint32_t pushbuf_domains;
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uint32_t notifier_handle;
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struct {
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uint32_t handle;
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uint32_t grclass;
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} subchan[8];
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uint32_t nr_subchan;
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};
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#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
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#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
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#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
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#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
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#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
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#define DRM_COMMAND_BASE 0x40
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#define DRM_COMMAND_END 0xA0
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#define DRM_NOUVEAU_GETPARAM 0x00
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#define DRM_NOUVEAU_SETPARAM 0x01
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#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
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#define DRM_NOUVEAU_CHANNEL_FREE 0x03
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#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
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#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
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#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
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#define DRM_NOUVEAU_NVIF 0x07
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#define DRM_NOUVEAU_GEM_NEW 0x40
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#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
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#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
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#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
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#define DRM_NOUVEAU_GEM_INFO 0x44
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#define DRM_NOUVEAU_STAGING_IOCTL 0x50
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#define DRM_NOUVEAU_GEM_SET_TILING (DRM_NOUVEAU_STAGING_IOCTL + 0x0)
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#define DRM_NOUVEAU_GEM_PUSHBUF_2 (DRM_NOUVEAU_STAGING_IOCTL + 0x1)
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#define DRM_NOUVEAU_GEM_SET_INFO (DRM_NOUVEAU_STAGING_IOCTL + 0x2)
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#define DRM_NOUVEAU_GEM_AS_ALLOC (DRM_NOUVEAU_STAGING_IOCTL + 0x3)
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#define DRM_NOUVEAU_GEM_AS_FREE (DRM_NOUVEAU_STAGING_IOCTL + 0x4)
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#define DRM_NOUVEAU_GEM_SET_ERROR_NOTIFIER (DRM_NOUVEAU_STAGING_IOCTL + 0x5)
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#define DRM_NOUVEAU_GEM_MAP (DRM_NOUVEAU_STAGING_IOCTL + 0x6)
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#define DRM_NOUVEAU_GEM_UNMAP (DRM_NOUVEAU_STAGING_IOCTL + 0x7)
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#define DRM_IOCTL_BASE 'd'
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#define DRM_IOR(nr, type) _IOR(DRM_IOCTL_BASE, nr, type)
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#define DRM_IOW(nr, type) _IOW(DRM_IOCTL_BASE, nr, type)
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#define DRM_IOWR(nr, type) _IOWR(DRM_IOCTL_BASE, nr, type)
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#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
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#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
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#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
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#define DRM_IOCTL_FREE_BUFS DRM_IOW(0x1a, struct drm_buf_free)
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#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
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#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
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#define DRM_IOCTL_NOUVEAU_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_MAP, struct drm_nouveau_gem_map)
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#define DRM_IOCTL_NOUVEAU_GEM_UNMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_UNMAP, struct drm_nouveau_gem_unmap)
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#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
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#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
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#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
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#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
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struct drm_tegra_gem_create {
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__u64 size;
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__u32 flags;
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__u32 handle;
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};
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struct drm_tegra_gem_mmap {
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__u32 handle;
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__u32 offset;
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};
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struct drm_tegra_syncpt_read {
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__u32 id;
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__u32 value;
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};
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struct drm_tegra_syncpt_incr {
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__u32 id;
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__u32 pad;
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};
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struct drm_tegra_syncpt_wait {
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__u32 id;
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__u32 thresh;
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__u32 timeout;
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__u32 value;
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};
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#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
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struct drm_tegra_open_channel {
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__u32 client;
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__u32 pad;
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__u64 context;
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};
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struct drm_tegra_close_channel {
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__u64 context;
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};
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struct drm_tegra_get_syncpt {
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__u64 context;
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__u32 index;
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__u32 id;
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};
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struct drm_tegra_get_syncpt_base {
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__u64 context;
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__u32 syncpt;
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__u32 id;
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};
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struct drm_tegra_syncpt {
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__u32 id;
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__u32 incrs;
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};
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struct drm_tegra_cmdbuf {
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__u32 handle;
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__u32 offset;
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__u32 words;
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__u32 pad;
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};
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struct drm_tegra_reloc {
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struct {
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__u32 handle;
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__u32 offset;
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} cmdbuf;
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struct {
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__u32 handle;
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__u32 offset;
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} target;
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__u32 shift;
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__u32 pad;
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};
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struct drm_tegra_waitchk {
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__u32 handle;
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__u32 offset;
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__u32 syncpt;
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__u32 thresh;
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};
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struct drm_tegra_submit {
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__u64 context;
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__u32 num_syncpts;
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__u32 num_cmdbufs;
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__u32 num_relocs;
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__u32 num_waitchks;
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__u32 waitchk_mask;
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__u32 timeout;
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__u64 syncpts;
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__u64 cmdbufs;
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__u64 relocs;
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__u64 waitchks;
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__u32 fence;
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__u32 reserved0;
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__u64 fences;
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__u32 reserved1[2];
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};
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#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
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#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
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#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
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struct drm_tegra_gem_set_tiling {
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__u32 handle;
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__u32 mode;
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__u32 value;
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__u32 pad;
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};
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struct drm_tegra_gem_get_tiling {
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__u32 handle;
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__u32 mode;
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__u32 value;
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__u32 pad;
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};
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#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
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#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
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struct drm_tegra_gem_set_flags {
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__u32 handle;
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__u32 flags;
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};
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struct drm_tegra_gem_get_flags {
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__u32 handle;
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__u32 flags;
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};
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enum request_type {
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DRM_TEGRA_REQ_TYPE_CLK_HZ = 0,
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DRM_TEGRA_REQ_TYPE_BW_KBPS,
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};
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struct drm_tegra_get_clk_rate {
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__u32 id;
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__u32 type;
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__u64 data;
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};
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struct drm_tegra_set_clk_rate {
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__u32 id;
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__u32 type;
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__u64 data;
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};
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struct drm_tegra_constraint {
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__u64 context;
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__u32 index;
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__u32 type;
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__u32 rate;
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__u32 pad;
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};
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struct drm_tegra_keepon {
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__u64 context;
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};
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#define DRM_TEGRA_GEM_CREATE 0x00
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#define DRM_TEGRA_GEM_MMAP 0x01
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#define DRM_TEGRA_SYNCPT_READ 0x02
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#define DRM_TEGRA_SYNCPT_INCR 0x03
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#define DRM_TEGRA_SYNCPT_WAIT 0x04
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#define DRM_TEGRA_OPEN_CHANNEL 0x05
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#define DRM_TEGRA_CLOSE_CHANNEL 0x06
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#define DRM_TEGRA_GET_SYNCPT 0x07
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#define DRM_TEGRA_SUBMIT 0x08
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#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
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#define DRM_TEGRA_GEM_SET_TILING 0x0a
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#define DRM_TEGRA_GEM_GET_TILING 0x0b
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#define DRM_TEGRA_GEM_SET_FLAGS 0x0c
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#define DRM_TEGRA_GEM_GET_FLAGS 0x0d
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#define DRM_TEGRA_GET_CLK_RATE 0x0e
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#define DRM_TEGRA_SET_CLK_RATE 0x0f
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#define DRM_TEGRA_START_KEEPON 0x10
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#define DRM_TEGRA_STOP_KEEPON 0x11
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#define DRM_TEGRA_GET_CLK_CONSTRAINT 0x12
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#define DRM_TEGRA_SET_CLK_CONSTRAINT 0x13
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#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
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#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
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#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
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#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
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#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
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#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
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#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
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#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
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#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
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#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
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#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
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#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
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#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
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#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
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#define DRM_IOCTL_TEGRA_GET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_CLK_RATE, struct drm_tegra_get_clk_rate)
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#define DRM_IOCTL_TEGRA_SET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SET_CLK_RATE, struct drm_tegra_set_clk_rate)
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#define DRM_IOCTL_TEGRA_START_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_START_KEEPON, struct drm_tegra_keepon)
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#define DRM_IOCTL_TEGRA_STOP_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_STOP_KEEPON, struct drm_tegra_keepon)
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#define DRM_IOCTL_TEGRA_GET_CLK_CONSTRAINT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_CLK_CONSTRAINT, struct drm_tegra_constraint)
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#define DRM_IOCTL_TEGRA_SET_CLK_CONSTRAINT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SET_CLK_CONSTRAINT, struct drm_tegra_constraint)
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#endif
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