137 lines
4.8 KiB
C
137 lines
4.8 KiB
C
#ifndef CMDQ_EVENT_COMMON
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#define CMDQ_EVENT_COMMON
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/* Define CMDQ events
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*
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* For hardware event must define in device tree.
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* For SW event assign event ID here directly.
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*
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* Note: event name must sync to cmdq_events table in cmdq_event_common.c
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*/
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enum CMDQ_EVENT_ENUM {
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/* MDP start frame */
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CMDQ_EVENT_MDP_RDMA0_SOF = 0,
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CMDQ_EVENT_MDP_RDMA1_SOF, /* 1 */
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CMDQ_EVENT_MDP_DSI0_TE_SOF, /* 2 */
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CMDQ_EVENT_MDP_DSI1_TE_SOF, /* 3 */
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CMDQ_EVENT_MDP_MVW_SOF, /* 4 */
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CMDQ_EVENT_MDP_TDSHP0_SOF, /* 5 */
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CMDQ_EVENT_MDP_TDSHP1_SOF, /* 6 */
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CMDQ_EVENT_MDP_WDMA_SOF, /* 7 */
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CMDQ_EVENT_MDP_WROT0_SOF, /* 8 */
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CMDQ_EVENT_MDP_WROT1_SOF, /* 9 */
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CMDQ_EVENT_MDP_CROP_SOF, /* 10 */
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/* Display start frame */
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CMDQ_EVENT_DISP_OVL0_SOF, /* 11 */
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CMDQ_EVENT_DISP_OVL1_SOF, /* 12 */
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CMDQ_EVENT_DISP_RDMA0_SOF, /* 13 */
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CMDQ_EVENT_DISP_RDMA1_SOF, /* 14 */
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CMDQ_EVENT_DISP_RDMA2_SOF, /* 15 */
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CMDQ_EVENT_DISP_WDMA0_SOF, /* 16 */
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CMDQ_EVENT_DISP_WDMA1_SOF, /* 17 */
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CMDQ_EVENT_DISP_COLOR0_SOF, /* 18 */
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CMDQ_EVENT_DISP_COLOR1_SOF, /* 19 */
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CMDQ_EVENT_DISP_AAL_SOF, /* 20 */
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CMDQ_EVENT_DISP_GAMMA_SOF, /* 21 */
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CMDQ_EVENT_DISP_UFOE_SOF, /* 22 */
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CMDQ_EVENT_DISP_PWM0_SOF, /* 23 */
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CMDQ_EVENT_DISP_PWM1_SOF, /* 24 */
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CMDQ_EVENT_DISP_OD_SOF, /* 25 */
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/* MDP frame done */
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CMDQ_EVENT_MDP_RDMA0_EOF, /* 26 */
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CMDQ_EVENT_MDP_RDMA1_EOF, /* 27 */
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CMDQ_EVENT_MDP_RSZ0_EOF, /* 28 */
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CMDQ_EVENT_MDP_RSZ1_EOF, /* 29 */
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CMDQ_EVENT_MDP_RSZ2_EOF, /* 30 */
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CMDQ_EVENT_MDP_TDSHP0_EOF, /* 31 */
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CMDQ_EVENT_MDP_TDSHP1_EOF, /* 32 */
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CMDQ_EVENT_MDP_WDMA_EOF, /* 33 */
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CMDQ_EVENT_MDP_WROT0_W_EOF, /* 34 */
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CMDQ_EVENT_MDP_WROT0_R_EOF, /* 35 */
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CMDQ_EVENT_MDP_WROT1_W_EOF, /* 36 */
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CMDQ_EVENT_MDP_WROT1_R_EOF, /* 37 */
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CMDQ_EVENT_MDP_CROP_EOF, /* 38 */
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/* Display frame done */
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CMDQ_EVENT_DISP_OVL0_EOF, /* 39 */
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CMDQ_EVENT_DISP_OVL1_EOF, /* 40 */
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CMDQ_EVENT_DISP_RDMA0_EOF, /* 41 */
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CMDQ_EVENT_DISP_RDMA1_EOF, /* 42 */
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CMDQ_EVENT_DISP_RDMA2_EOF, /* 43 */
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CMDQ_EVENT_DISP_WDMA0_EOF, /* 44 */
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CMDQ_EVENT_DISP_WDMA1_EOF, /* 45 */
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CMDQ_EVENT_DISP_COLOR0_EOF, /* 46 */
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CMDQ_EVENT_DISP_COLOR1_EOF, /* 47 */
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CMDQ_EVENT_DISP_AAL_EOF, /* 48 */
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CMDQ_EVENT_DISP_GAMMA_EOF, /* 49 */
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CMDQ_EVENT_DISP_UFOE_EOF, /* 50 */
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CMDQ_EVENT_DISP_DPI0_EOF, /* 51 */
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/* Mutex frame done */
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CMDQ_EVENT_MUTEX0_STREAM_EOF = 53,
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CMDQ_EVENT_MUTEX1_STREAM_EOF, /* 54 */
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CMDQ_EVENT_MUTEX2_STREAM_EOF, /* 55 */
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CMDQ_EVENT_MUTEX3_STREAM_EOF, /* 56 */
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CMDQ_EVENT_MUTEX4_STREAM_EOF, /* 57 */
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CMDQ_EVENT_MUTEX5_STREAM_EOF, /* 58 */
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CMDQ_EVENT_MUTEX6_STREAM_EOF, /* 59 */
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CMDQ_EVENT_MUTEX7_STREAM_EOF, /* 60 */
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CMDQ_EVENT_MUTEX8_STREAM_EOF, /* 61 */
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CMDQ_EVENT_MUTEX9_STREAM_EOF, /* 62 */
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/* DpFramework via CMDQ_IOCTL_LOCK_MUTEX */
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/* Display underrun */
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CMDQ_EVENT_DISP_RDMA0_UNDERRUN, /* 63 */
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CMDQ_EVENT_DISP_RDMA1_UNDERRUN, /* 64 */
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CMDQ_EVENT_DISP_RDMA2_UNDERRUN, /* 65 */
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/* ISP frame done */
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CMDQ_EVENT_ISP_PASS2_2_EOF = 129,
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CMDQ_EVENT_ISP_PASS2_1_EOF, /* 130 */
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CMDQ_EVENT_ISP_PASS2_0_EOF, /* 131 */
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CMDQ_EVENT_ISP_PASS1_1_EOF, /* 132 */
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CMDQ_EVENT_ISP_PASS1_0_EOF, /* 133 */
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/* Engine events */
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CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE, /* 134 */
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CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE, /* 135 */
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CMDQ_EVENT_ISP_SENINF_CAM1_2_3_FULL, /* 136 */
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CMDQ_EVENT_ISP_SENINF_CAM0_FULL, /* 137 */
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/* JPEG frame done */
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CMDQ_EVENT_JPEG_ENC_PASS2_EOF = 257,
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CMDQ_EVENT_JPEG_ENC_PASS1_EOF, /* 258 */
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CMDQ_EVENT_JPEG_DEC_EOF, /* 259 */
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CMDQ_MAX_HW_EVENT_COUNT, /* 260 */
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/* Keep this at the end of HW events */
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/* SW Sync Tokens (Pre-defined) */
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CMDQ_SYNC_TOKEN_CONFIG_DIRTY, /* 261 */
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/* Config thread notify trigger thread */
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CMDQ_SYNC_TOKEN_STREAM_EOF, /* 262 */
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/* Trigger thread notify config thread */
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/* ESD check state. Trigger thread will be blocked until the check finishes. */
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CMDQ_SYNC_TOKEN_ESD_EOF, /* 263 */
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CMDQ_SYNC_TOKEN_CABC_EOF, /* 264 */
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/* check CABC setup finish */
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/* Block Trigger thread until the path freeze finishes */
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CMDQ_SYNC_TOKEN_FREEZE_EOF, /* 265 */
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/* Pass-2 notifies VENC frame is ready to be encoded */
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CMDQ_SYNC_TOKEN_VENC_INPUT_READY = 270,
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/* VENC notifies Pass-2 encoding completion so next frame may start */
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CMDQ_SYNC_TOKEN_VENC_EOF, /* 271 */
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/* Notify normal CMDQ there are some secure task done */
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CMDQ_SYNC_SECURE_THR_EOF = 299,
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/* SW Sync Tokens (User-defined) */
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CMDQ_SYNC_TOKEN_USER_0, /* 300 */
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/* SW-defined sync token */
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CMDQ_SYNC_TOKEN_USER_1, /* 301 */
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/* GPR access tokens (for HW register backup) */
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/* There are 15 32-bit GPR, 3 GPR form a set (64-bit for address, 32-bit for value) */
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CMDQ_SYNC_TOKEN_GPR_SET_0 = 400,
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CMDQ_SYNC_TOKEN_GPR_SET_1 = 401,
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CMDQ_SYNC_TOKEN_GPR_SET_2 = 402,
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CMDQ_SYNC_TOKEN_GPR_SET_3 = 403,
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CMDQ_SYNC_TOKEN_GPR_SET_4 = 404,
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CMDQ_SYNC_TOKEN_MAX = 0x1FF,
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CMDQ_SYNC_TOKEN_INVALID = -1,
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};
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#endif |