34 lines
1.4 KiB
Plaintext
34 lines
1.4 KiB
Plaintext
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// --------------------------------------------------------------------
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// Copyright (c) 2013 by Lattice Semiconductor Corporation
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// --------------------------------------------------------------------
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code for use
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// in synthesis for any Lattice programmable logic product. Other
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// use of this code, including the selling or duplication of any
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// portion is strictly prohibited.
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//
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// Disclaimer:
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//
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// This VHDL or Verilog source code is intended as a design reference
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// which illustrates how these types of functions can be implemented.
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// It is the user's responsibility to verify their design for
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// consistency and functionality through the use of formal
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// verification methods. Lattice Semiconductor provides no warranty
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// regarding the use or functionality of this code.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// -------------------------------------------------------------------- |