werunplugged/unplugged-vendor
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
ebc759d833
unplugged-vendor/kernel-4.19/arch/arm64/boot/dts/mediatek/mt6785.dts

6017 lines
143 KiB
Plaintext
Raw Normal View History

Initial commit: AOSP 12 vendor with modifications for Unplugged OS
2025-10-06 13:59:42 +00:00
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
/dts-v1/;
#include <dt-bindings/clock/mt6785-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mmc/mt6785-msdc.h>
#include <dt-bindings/pinctrl/mt6785-pinfunc.h>
#include <dt-bindings/memory/mt6785-larb-port.h>
#include <dt-bindings/gce/mt6785-gce.h>
#include <dt-bindings/iio/mt635x-auxadc.h>
#include <dt-bindings/mfd/mt6359-irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/soc/mediatek,boot-mode.h>
#include <dt-bindings/reset/ti-syscon.h>
#include <generated/autoconf.h>
/ {
model = "MT6785";
compatible = "mediatek,MT6785";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
/* chosen */
chosen: chosen {
bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram \
vmalloc=400M slub_debug=OFZPU swiotlb=noforce \
cgroup.memory=nosocket,nokmem \
firmware_class.path=/vendor/firmware \
page_owner=on loop.max_part=7";
kaslr-seed = <0 0>;
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp0 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <600000>;
};
opp1 {
opp-hz = /bits/ 64 <774000000>;
opp-microvolt = <675000>;
};
opp2 {
opp-hz = /bits/ 64 <875000000>;
opp-microvolt = <700000>;
};
opp3 {
opp-hz = /bits/ 64 <975000000>;
opp-microvolt = <725000>;
};
opp4 {
opp-hz = /bits/ 64 <1075000000>;
opp-microvolt = <750000>;
};
opp5 {
opp-hz = /bits/ 64 <1175000000>;
opp-microvolt = <775000>;
};
opp6 {
opp-hz = /bits/ 64 <1275000000>;
opp-microvolt = <800000>;
};
opp7 {
opp-hz = /bits/ 64 <1375000000>;
opp-microvolt = <825000>;
};
opp8 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <856250>;
};
opp9 {
opp-hz = /bits/ 64 <1618000000>;
opp-microvolt = <875000>;
};
opp10 {
opp-hz = /bits/ 64 <1666000000>;
opp-microvolt = <900000>;
};
opp11 {
opp-hz = /bits/ 64 <1733000000>;
opp-microvolt = <925000>;
};
opp12 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <950000>;
};
opp13 {
opp-hz = /bits/ 64 <1866000000>;
opp-microvolt = <981250>;
};
opp14 {
opp-hz = /bits/ 64 <1933000000>;
opp-microvolt = <1006250>;
};
opp15 {
opp-hz = /bits/ 64 <2000000000>;
opp-microvolt = <1031250>;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp0 {
opp-hz = /bits/ 64 <774000000>;
opp-microvolt = <675000>;
};
opp1 {
opp-hz = /bits/ 64 <835000000>;
opp-microvolt = <693750>;
};
opp2 {
opp-hz = /bits/ 64 <919000000>;
opp-microvolt = <718750>;
};
opp3 {
opp-hz = /bits/ 64 <1002000000>;
opp-microvolt = <743750>;
};
opp4 {
opp-hz = /bits/ 64 <1085000000>;
opp-microvolt = <775000>;
};
opp5 {
opp-hz = /bits/ 64 <1169000000>;
opp-microvolt = <800000>;
};
opp6 {
opp-hz = /bits/ 64 <1308000000>;
opp-microvolt = <843750>;
};
opp7 {
opp-hz = /bits/ 64 <1419000000>;
opp-microvolt = <875000>;
};
opp8 {
opp-hz = /bits/ 64 <1530000000>;
opp-microvolt = <912500>;
};
opp9 {
opp-hz = /bits/ 64 <1670000000>;
opp-microvolt = <956250>;
};
opp10 {
opp-hz = /bits/ 64 <1733000000>;
opp-microvolt = <981250>;
};
opp11 {
opp-hz = /bits/ 64 <1796000000>;
opp-microvolt = <1012500>;
};
opp12 {
opp-hz = /bits/ 64 <1860000000>;
opp-microvolt = <1037500>;
};
opp13 {
opp-hz = /bits/ 64 <1907000000>;
opp-microvolt = <1056250>;
};
opp14 {
opp-hz = /bits/ 64 <1955000000>;
opp-microvolt = <1081250>;
};
opp15 {
opp-hz = /bits/ 64 <2002000000>;
opp-microvolt = <1100000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@000 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0000>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
capacity-dmips-mhz = <284>;
cpu-idle-states = <&standby &mcdi_cpu &mcdi_cluster>,
<&idledram &idlesyspll &idlebus26m &suspend>;
};
cpu1: cpu@001 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0100>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
capacity-dmips-mhz = <284>;
cpu-idle-states = <&standby &mcdi_cpu &mcdi_cluster>,
<&idledram &idlesyspll &idlebus26m &suspend>;
};
cpu2: cpu@002 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0200>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
capacity-dmips-mhz = <284>;
cpu-idle-states = <&standby &mcdi_cpu &mcdi_cluster>,
<&idledram &idlesyspll &idlebus26m &suspend>;
};
cpu3: cpu@003 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0300>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
capacity-dmips-mhz = <284>;
cpu-idle-states = <&standby &mcdi_cpu &mcdi_cluster>,
<&idledram &idlesyspll &idlebus26m &suspend>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0400>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
capacity-dmips-mhz = <284>;
cpu-idle-states = <&standby &mcdi_cpu &mcdi_cluster>,
<&idledram &idlesyspll &idlebus26m &suspend>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0500>;
enable-method = "psci";
clock-frequency = <1701000000>;
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <85>;
capacity-dmips-mhz = <284>;
cpu-idle-states = <&standby &mcdi_cpu &mcdi_cluster>,
<&idledram &idlesyspll &idlebus26m &suspend>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a75";
reg = <0x0600>;
enable-method = "psci";
clock-frequency = <2171000000>;
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <275>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&standby &mcdi_cpu &mcdi_cluster>,
<&idledram &idlesyspll &idlebus26m &suspend>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a75";
reg = <0x0700>;
enable-method = "psci";
clock-frequency = <2171000000>;
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <275>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&standby &mcdi_cpu &mcdi_cluster>,
<&idledram &idlesyspll &idlebus26m &suspend>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
core4 {
cpu = <&cpu4>;
};
core5 {
cpu = <&cpu5>;
};
doe_dvfs_cl0: doe {
};
};
cluster1 {
core0 {
cpu = <&cpu6>;
};
core1 {
cpu = <&cpu7>;
};
doe_dvfs_cl1: doe {
};
};
};
idle-states {
entry-method = "arm,psci";
standby: standby {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00000001>;
entry-latency-us = <600>;
exit-latency-us = <600>;
min-residency-us = <1200>;
};
mcdi_cpu: mcdi-cpu {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x00010001>;
entry-latency-us = <600>;
exit-latency-us = <600>;
min-residency-us = <1200>;
};
mcdi_cluster: mcdi-cluster {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010001>;
entry-latency-us = <600>;
exit-latency-us = <600>;
min-residency-us = <1200>;
};
idledram: idledram {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010002>;
entry-latency-us = <800>;
exit-latency-us = <1000>;
min-residency-us = <2000>;
status = "okay";
};
idlesyspll: idlesyspll {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010003>;
entry-latency-us = <800>;
exit-latency-us = <1000>;
min-residency-us = <2000>;
status = "okay";
};
idlebus26m: idlebus26m {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010004>;
entry-latency-us = <800>;
exit-latency-us = <1000>;
min-residency-us = <2000>;
status = "okay";
};
suspend: suspend {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01010005>;
entry-latency-us = <800>;
exit-latency-us = <1000>;
min-residency-us = <2000>;
status = "okay";
};
};
};
cache_parity {
compatible = "mediatek,mt6785-cache-parity";
reg = <0 0x0c530000 0 0x10000>;
irq_config = <0 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
<1 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
<2 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
<3 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
<4 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
<5 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
<6 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
<7 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
<1024 0xc8c0 0x01000000 0xc8c0 12 0xc8c8 0x00000001>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
};
lastbus@10001000 {
compatible = "mediatek,lastbus-v1";
reg = <0 0x10001000 0 0x1000>,
<0 0x10003000 0 0x1000>;
};
scp_infra: scp_infra@10001000 {
compatible = "mediatek,scpinfra";
reg = <0 0x10001000 0 0x1000>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
dsu-pmu-0 {
compatible = "arm,dsu-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
memory {
device_type = "memory";
reg = <0 0x40000000 0 0x3e605000>;
};
/* Trustonic Mobicore SW IRQ number 121 = 32 + 89 */
mobicore {
compatible = "trustonic,mobicore";
interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
};
/* Microtrust SW IRQ number 91(123) ~ 95(127) & 331(363) */
utos {
compatible = "microtrust,utos";
interrupts = <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
};
utos_tester {
compatible = "microtrust,tester-v1";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ssmr_cma_mem: ssmr-reserved-cma_memory {
compatible = "shared-dma-pool";
reusable;
size = <0 0x10000000>;
alignment = <0 0x1000000>;
alloc-range = <0 0xc0000000 0 0x10000000>;
};
reserve-memory-sspm_share {
compatible = "mediatek,reserve-memory-sspm_share";
no-map;
status = "okay";
#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
size = <0 0x110000>; /* 1M + 64K */
#else
size = <0 0x510000>; /* 5M + 64K */
#endif
alignment = <0 0x10000>;
alloc-ranges = <0 0x40000000 0 0x60000000>;
};
reserve-memory-scp_share {
compatible = "mediatek,reserve-memory-scp_share";
no-map;
size = <0 0x00320000>;
alignment = <0 0x1000000>;
alloc-ranges = <0 0x40000000 0 0x50000000>;
};
ion-carveout-heap {
compatible = "mediatek,ion-carveout-heap";
no-map;
size = <0 0xc000>;
alignment = <0 0x1000>;
alloc-ranges = <0 0x40000000 0 0x80000000>;
};
consys_mem: consys-reserve-memory {
compatible = "mediatek,consys-reserve-memory";
no-map;
size = <0 0x400000>;
alignment = <0 0x1000000>;
alloc-ranges = <0 0x40000000 0 0x80000000>;
};
wifi_mem: wifi-reserve-memory {
compatible = "shared-dma-pool";
no-map;
size = <0 0x300000>;
alignment = <0 0x1000000>;
alloc-ranges = <0 0x40000000 0 0x80000000>;
};
reserve-memory-adsp_share {
compatible = "mediatek,reserve-memory-adsp_share";
no-map;
size = <0 0x1000000>;
alignment = <0 0x1000>;
alloc-ranges = <0 0x40000000 0 0x40000000>;
};
};
cpu_dbgapb: cpu_dbgapb@0e010000 {
compatible = "mediatek,hw_dbg";
num = <8>;
reg = <0 0x0e010000 0 0x1000>,
<0 0x0e110000 0 0x1000>,
<0 0x0e210000 0 0x1000>,
<0 0x0e310000 0 0x1000>,
<0 0x0e410000 0 0x1000>,
<0 0x0e510000 0 0x1000>,
<0 0x0e610000 0 0x1000>,
<0 0x0e710000 0 0x1000>;
};
gic: interrupt-controller {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
#redistributor-regions = <1>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x40000>, // distributor
<0 0x0c040000 0 0x200000>,// redistributor
<0 0x0c53a650 0 0x50>; // INT_POL
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
sysirq: intpol-controller@0 {
compatible = "mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x0c53a650 0 0x50>;
};
clocks {
clk_null: clk_null {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
clk26m: clk26m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clk13m: clk13m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <13000000>;
};
clk32k: clk32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
};
};
topckgen: topckgen@10000000 {
compatible = "mediatek,topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg_ao: clock-reset-controller@10001000 {
compatible = "mediatek,common-infracfg_ao",
"mediatek,infracfg_ao",
"mediatek,mt6785-infracfg_ao", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
infracfg_rst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits = <
/* 0: ufs: hci_rst */
0x130 15 0x134 15 0 0
(ASSERT_SET | DEASSERT_SET | STATUS_NONE)
/* 1: ufs: unipro_rst */
0x140 7 0x144 7 0 0
(ASSERT_SET | DEASSERT_SET | STATUS_NONE)
/* 2: ufs: crypto_rst */
0x150 21 0x154 21 0 0
(ASSERT_SET | DEASSERT_SET | STATUS_NONE)
>;
};
};
efuse: efuse@11c10000 {
compatible = "mediatek,devinfo";
reg = <0 0x11c10000 0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
efuse_segment: segment@78 {
reg = <0x78 0x4>;
};
};
scpsys: scpsys@10001000 {
compatible = "mediatek,scpsys";
reg = <0 0x10001000 0 0x1000>,
<0 0x10006000 0 0x1000>,
<0 0x1020e000 0 0x1000>,
<0 0x10000000 0 0x1000>,
<0 0x14019000 0 0x1000>;
#clock-cells = <1>;
};
scp_clk_ctrl: scp_clk_ctrl@105c4000 {
compatible = "mediatek,scp_clk_ctrl";
reg = <0 0x105c4000 0 0x1000>;
};
scp_gpio: scp_gpio@10005000 {
compatible = "mediatek,scp_gpio", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
scp_dvfs {
compatible = "mediatek,scp_dvfs";
clocks = <&topckgen TOP_MUX_SCP>,
<&clk26m>,
<&topckgen TOP_MAINPLL_D2_D2>,
<&topckgen TOP_MAINPLL_D2_D4>,
<&topckgen TOP_MAINPLL_D3>,
<&topckgen TOP_UNIVPLL_D3>,
<&topckgen TOP_MAINPLL_D5>,
<&topckgen TOP_MAINPLL_D3_D2>,
<&topckgen TOP_OSC2_D3>;
clock-names = "clk_mux",
"clk_pll_0",
"clk_pll_1",
"clk_pll_2",
"clk_pll_3",
"clk_pll_4",
"clk_pll_5",
"clk_pll_6",
"clk_pll_7";
vsram_chk_gpio = <&pio 200 0x0>;
dvfsrc-opp-num = <6>;
dvfs-opp =
/*vcore vsram uv rc spm freq mux*/
< 575000 800000 0xff 0x0 0x0 110 1>,
< 600000 800000 0xff 0x0 0x0 130 1>,
< 650000 850000 0xff 0x0 0x1 165 2>,
< 650000 850000 0xff 0x0 0x1 218 5>,
< 700000 850000 0xff 0x1 0x12 330 2>,
< 800000 900000 0xff 0x2 0x28 416 4>;
sshub-vcore-supply = <&mt_pmic_vcore_sshub_buck_reg>;
sshub-vsram-supply = <&mt_pmic_vsram_others_sshub_ldo_reg>;
gpio = <&gpio 1>;
gpio-feature = "gpio-mode";
gpio-feature-cfg = <1>;
gpio-mode-reg = <0x430 0x7 8 1>;
};
infracfg_ao_mem@10002000 {
compatible = "mediatek,infracfg_ao_mem";
reg = <0 0x10002000 0 0x1000>;
};
iocfg_rm: iocfg_rm@11c20000 {
compatible = "mediatek,iocfg_rm";
reg = <0 0x11c20000 0 0x1000>;
};
iocfg_br: iocfg_br@11d10000 {
compatible = "mediatek,iocfg_br";
reg = <0 0x11d10000 0 0x1000>;
};
iocfg_bl: iocfg_bl@11e20000 {
compatible = "mediatek,iocfg_bl";
reg = <0 0x11e20000 0 0x1000>;
};
iocfg_lb: iocfg_lb@11e70000 {
compatible = "mediatek,iocfg_lb";
reg = <0 0x11e70000 0 0x1000>;
};
iocfg_rt: iocfg_rt@11ea0000 {
compatible = "mediatek,iocfg_rt";
reg = <0 0x11ea0000 0 0x1000>;
};
iocfg_lt: iocfg_lt@11f20000 {
compatible = "mediatek,iocfg_lt";
reg = <0 0x11f20000 0 0x1000>;
};
iocfg_tl: iocfg_tl@11f30000 {
compatible = "mediatek,iocfg_tl";
reg = <0 0x11f30000 0 0x1000>;
};
pericfg@10003000 {
compatible = "mediatek,pericfg";
reg = <0 0x10003000 0 0x1000>;
};
gpio: gpio@10005000 {
compatible = "mediatek,gpio", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
pio: pinctrl {
compatible = "mediatek,mt6785-pinctrl";
reg_bases = <&gpio>,
<&iocfg_rm>,
<&iocfg_br>,
<&iocfg_bl>,
<&iocfg_lb>,
<&iocfg_rt>,
<&iocfg_lt>,
<&iocfg_tl>;
reg_base_eint = <&eint>;
pins-are-numbered;
gpio-controller;
gpio-ranges = <&pio 0 0 210>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <4>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
};
sleep:sleep@10006000 {
compatible = "mediatek,sleep";
reg = <0 0x10006000 0 0x1000>;
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_LOW>;
};
md32pcm@10006a00 {
compatible = "mediatek,md32pcm";
reg = <0 0x10006a00 0 0x1000>;
};
md32pcm_sram@1001e000 {
compatible = "mediatek,md32pcm_sram";
reg = <0 0x1001e000 0 0x1000>;
};
toprgu:toprgu@10007000 {
compatible = "mediatek,mt6877-wdt",
"mediatek,mt6589-wdt",
"mediatek,toprgu",
"syscon", "simple-mfd";
reg = <0 0x10007000 0 0x1000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
mediatek,rg_dfd_timeout = <0xa0>;
#reset-cells = <1>;
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x24>;
mask = <0xf>;
mode-charger = <BOOT_CHARGER>;
mode-recovery = <BOOT_RECOVERY>;
mode-bootloader = <BOOT_BOOTLOADER>;
mode-dm-verity-dev-corrupt = <BOOT_DM_VERITY>;
mode-kpoc = <BOOT_KPOC>;
mode-ddr-reserve = <BOOT_DDR_RSVD>;
mode-meta = <BOOT_META>;
mode-rpmbpk = <BOOT_RPMBPK>;
};
};
rsvd@10009000 {
compatible = "mediatek,rsvd";
reg = <0 0x10009000 0 0x1000>;
};
hacc@1000a000 {
compatible = "mediatek,hacc";
reg = <0 0x1000a000 0 0x1000>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_LOW>;
};
eint: eint@1000b000 {
compatible = "mediatek,eint";
reg = <0 0x1000b000 0 0x1000>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
};
apmixed: apmixed@1000c000 {
compatible = "mediatek,apmixed", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
fhctl@1000ce00 {
compatible = "mediatek,fhctl";
reg = <0 0x1000ce00 0 0x1000>;
};
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt6785-pwrap";
reg = <0 0x1000d000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "spi", "wrap";
main_pmic: mt6359-pmic {
compatible = "mediatek,mt6359-pmic";
interrupt-parent = <&pio>;
interrupts = <193 IRQ_TYPE_LEVEL_HIGH 193 0>;
status = "okay";
};
};
pwraph: pwraphal@ {
compatible = "mediatek,pwraph";
mediatek,pwrap-regmap = <&pwrap>;
};
pwrap_mpu@1000d000 {
compatible = "mediatek,pwrap_mpu";
reg = <0 0x1000d000 0 0x1000>;
};
pwrap_p2p@105cb000 {
compatible = "mediatek,pwrap_p2p";
reg = <0 0x105cb000 0 0x1000>;
};
pwrap_md32@10448000 {
compatible = "mediatek,pwrap_md32";
reg = <0 0x10448000 0 0x1000>;
};
devapc_ao_mm@1000e000 {
compatible = "mediatek,devapc_ao_mm";
reg = <0 0x1000e000 0 0x1000>;
};
sleep_reg_md@1000f000 {
compatible = "mediatek,sleep_reg_md";
reg = <0 0x1000f000 0 0x1000>;
};
keypad: kp@10010000 {
compatible = "mediatek,kp";
reg = <0 0x10010000 0 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_FALLING>;
clocks = <&clk26m>;
clock-names = "kpd";
mediatek,boot_mode = <1>;
};
topmisc@10011000 {
compatible = "mediatek,topmisc";
reg = <0 0x10011000 0 0x1000>;
};
dvfsrc: dvfsrc@10012000 {
compatible = "mediatek,dvfsrc";
reg = <0 0x10012000 0 0x1000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
};
apcldmain_ao@10014000 {
compatible = "mediatek,apcldmain_ao";
reg = <0 0x10014000 0 0x1000>;
};
dpmaif:dpmaif@10014000 {
compatible = "mediatek,dpmaif";
reg = <0 0x10014000 0 0x1000>, /*AO_UL*/
<0 0x10014400 0 0x1000>, /*AO_DL*/
<0 0x1022D000 0 0x1000>, /*PD_UL*/
<0 0x1022D100 0 0x1000>, /*PD_DL*/
<0 0x1022D400 0 0x1000>, /*PD_MISC*/
<0 0x1022C000 0 0x1000>, /*PD_MD_MISC*/
<0 0x1022E000 0 0x1000>; /*SRAM*/
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; /*199+32=231*/
mediatek,dpmaif_capability = <6>;
clocks = <&infracfg_ao INFRACFG_AO_DPMAIF_CK>;
clock-names = "infra-dpmaif-clk";
};
ccifdriver:ccifdriver@10209000 {
compatible = "mediatek,ccci_ccif";
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
mediatek,sram_size = <512>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_CCIF_AP_CG>,
<&infracfg_ao INFRACFG_AO_CCIF_MD_CG>,
<&infracfg_ao INFRACFG_AO_CCIF1_AP_CG>,
<&infracfg_ao INFRACFG_AO_CCIF1_MD_CG>,
<&infracfg_ao INFRACFG_AO_CCIF2_AP_CG>,
<&infracfg_ao INFRACFG_AO_CCIF2_MD_CG>,
<&infracfg_ao INFRACFG_AO_CCIF4_MD_CG>;
clock-names = "infra-ccif-ap",
"infra-ccif-md",
"infra-ccif1-ap",
"infra-ccif1-md",
"infra-ccif2-ap",
"infra-ccif2-md",
"infra-ccif4-md",
"infra-ccif5-md";
};
mddriver:mddriver {
compatible = "mediatek,mddriver";
mediatek,mdhif_type = <6>; /* bit0~3: CLDMA|CCIF|DPMAIF */
mediatek,md_id = <0>;
mediatek,ap_plat_info = <6785>;
mediatek,md_generation = <6295>;
mediatek,offset_apon_md1 = <0x1c24>;
mediatek,cldma_capability = <6>;
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_FALLING>, /*MDWDT*/
<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>, /*CCIF0 GIC Interrupt ID 196-32*/
<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>; /*CCIF0 GIC Interrupt ID 197-32*/
clocks = <&scpsys SCP_SYS_MD1>;
clock-names = "scp-sys-md1-main";
ccci-infracfg = <&infracfg_ao>;
};
radio_md_cfg:radio_md_cfg {
compatible = "mediatek,radio_md_cfg";
};
md_auxadc:md_auxadc {
compatible = "mediatek,md_auxadc";
io-channels = <&auxadc 2>;
io-channel-names = "md-channel";
};
apcldmaout_ao@10014400 {
compatible = "mediatek,apcldmaout_ao";
reg = <0 0x10014400 0 0x1000>;
};
apcldmamisc_ao@10014800 {
compatible = "mediatek,apcldmamisc_ao";
reg = <0 0x10014800 0 0x1000>;
};
devapc_mpu_ao@10015000 {
compatible = "mediatek,devapc_mpu_ao";
reg = <0 0x10015000 0 0x1000>;
};
aes_top0@10016000 {
compatible = "mediatek,aes_top0";
reg = <0 0x10016000 0 0x1000>;
};
chipid@08000000 {
compatible = "mediatek,chipid";
reg = <0 0x08000000 0 0x0004>,
<0 0x08000004 0 0x0004>,
<0 0x08000008 0 0x0004>,
<0 0x0800000c 0 0x0004>;
};
systimer: systimer@10017000 {
compatible = "mediatek,mt6768-timer",
"mediatek,mt6765-timer",
"mediatek,sys_timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk13m>;
};
timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <13000000>;
};
scp@10500000 {
compatible = "mediatek,scp";
status = "okay";
reg = <0 0x10500000 0 0xc0000>,
<0 0x105c0000 0 0x3000>,
<0 0x105c4000 0 0x1000>,
<0 0x105d4000 0 0x6000>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
core_1 = "enable";
scp_sramSize = <0x000c0000>;
scp_mpuRegionId = <7>;
scp_feature_tbl = <0 5>, /* vow */
<1 356>, /* dsp */
<2 62>, /* sensor */
<3 47>, /* mp3 */
<4 26>, /* flp */
<5 0>, /* rtos */
<6 200>, /* speaker */
<7 0>, /* vcore */
<8 120>, /* barge in */
<9 10>, /* vow dump */
<10 43>, /* vow vendor_m */
<11 43>, /* vow vendor_a */
<12 22>; /* vow vendor_g */
scp_mem_key = "mediatek,reserve-memory-scp_share";
scp_mem_tbl =
#ifdef CONFIG_MTK_VOW_SUPPORT
#if defined(CONFIG_MTK_VOW_AMAZON_SUPPORT) || defined(CONFIG_MTK_VOW_GVA_SUPPORT)
<0 0x49200>, /* vow */
#else
<0 0x38200>, /* vow */
#endif
#endif
<1 0x100000>, /* sensor */
<3 0x001000>, /* flp */
<4 0x180000>, /* logger */
<5 0x19000>, /* audio ipi */
<8 0x5A00>; /* bargin */
};
modem_temp_share@10018000 {
compatible = "mediatek,modem_temp_share";
reg = <0 0x10018000 0 0x1000>;
};
devapc_ao_md@10019000 {
compatible = "mediatek,devapc_ao_md";
reg = <0 0x10019000 0 0x1000>;
};
mbist_ao@10013000 {
compatible = "mediatek,mbist_ao";
reg = <0 0x10013000 0 0x1000>;
};
security_ao@1001a000 {
compatible = "mediatek,security_ao";
reg = <0 0x1001a000 0 0x1000>;
};
topckgen_ao@1001b000 {
compatible = "mediatek,topckgen_ao";
reg = <0 0x1001b000 0 0x1000>;
};
devapc_ao_infra_peri@1001c000 {
compatible = "mediatek,devapc_ao_infra_peri";
reg = <0 0x1001c000 0 0x1000>;
};
device_mpu_low@1021a000 {
compatible = "mediatek,device_mpu_low";
reg = <0 0x1021a000 0 0x1000>;
prot-base = <0x0 0x40000000>;
prot-size = <0x4 0x00000000>;
page-size = <0x200000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
};
device_mpu_low_acp@1021b000 {
compatible = "mediatek,device_mpu_low_acp";
reg = <0 0x1021b000 0 0x1000>;
};
infracfg_mem@1021c000 {
compatible = "mediatek,infracfg_mem";
reg = <0 0x1021c000 0 0x1000>;
};
#ifdef CONFIG_MTK_IOMMU_V2
iommu0: m4u@10220000 {
cell-index = <0>;
compatible = "mediatek,iommu_v0";
reg = <0 0x10220000 0 0x1000>;
mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2>,
<&smi_larb3 &smi_larb4 &smi_larb5>,
<&smi_larb6>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
#iommu-cells = <1>;
};
iommu1: m4u@1024f000 {
cell-index = <1>;
compatible = "mediatek,iommu_v0";
reg = <0 0x1024f000 0 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
#iommu-cells = <1>;
};
iommu0_sec: m4u@10224000 {
cell-index = <0>;
compatible = "mediatek,sec_m4u0";
reg = <0 0x10224000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
};
ion: iommu {
compatible = "mediatek,ion";
iommus = <&iommu0 M4U_PORT_DISP_RDMA0>;
};
pseudo_m4u {
compatible = "mediatek,mt-pseudo_m4u";
iommus = <&iommu0 M4U_PORT_DISP_RDMA0>;
};
pseudo_m4u-larb0 {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <0>;
iommus = <&iommu0 M4U_PORT_DISP_POSTMASK0>,
<&iommu0 M4U_PORT_DISP_OVL0_HDR>,
<&iommu0 M4U_PORT_DISP_OVL1_HDR>,
<&iommu0 M4U_PORT_DISP_OVL0>,
<&iommu0 M4U_PORT_DISP_OVL1>,
<&iommu0 M4U_PORT_DISP_PVRIC0>,
<&iommu0 M4U_PORT_DISP_RDMA0>,
<&iommu0 M4U_PORT_DISP_WDMA0>,
<&iommu0 M4U_PORT_DISP_FAKE0>;
/* larb0 -MMSYS-9 */
};
pseudo_m4u-larb1 {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <1>;
iommus = <&iommu0 M4U_PORT_DISP_OVL0_2L_HDR>,
<&iommu0 M4U_PORT_DISP_OVL1_2L_HDR>,
<&iommu0 M4U_PORT_DISP_OVL0_2L>,
<&iommu0 M4U_PORT_DISP_OVL1_2L>,
<&iommu0 M4U_PORT_DISP_RDMA1>,
<&iommu0 M4U_PORT_MDP_PVRIC0>,
<&iommu0 M4U_PORT_MDP_PVRIC1>,
<&iommu0 M4U_PORT_MDP_RDMA0>,
<&iommu0 M4U_PORT_MDP_RDMA1>,
<&iommu0 M4U_PORT_MDP_WROT0_R>,
<&iommu0 M4U_PORT_MDP_WROT0_W>,
<&iommu0 M4U_PORT_MDP_WROT1_R>,
<&iommu0 M4U_PORT_MDP_WROT1_W>,
<&iommu0 M4U_PORT_DISP_FAKE1>;
/* larb1-MMSYS-14 */
};
pseudo_m4u-larb2 {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <2>;
iommus = <&iommu0 M4U_PORT_HW_VDEC_MC_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_UFO_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_PP_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_PRED_RD_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_PRED_WR_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_PPWRAP_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_TILE_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_VLD_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_VLD2_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_AVC_MV_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_UFO_ENC_EXT>,
<&iommu0 M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT>;
/* larb2-VDEC-12 */
};
pseudo_m4u-larb3 {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <3>;
iommus = <&iommu0 M4U_PORT_VENC_RCPU>,
<&iommu0 M4U_PORT_VENC_REC>,
<&iommu0 M4U_PORT_VENC_BSDMA>,
<&iommu0 M4U_PORT_VENC_SV_COMV>,
<&iommu0 M4U_PORT_VENC_RD_COMV>,
<&iommu0 M4U_PORT_VENC_NBM_RDMA>,
<&iommu0 M4U_PORT_VENC_NBM_RDMA_LITE>,
<&iommu0 M4U_PORT_JPGENC_Y_RDMA>,
<&iommu0 M4U_PORT_JPGENC_C_RDMA>,
<&iommu0 M4U_PORT_JPGENC_Q_TABLE>,
<&iommu0 M4U_PORT_JPGENC_BSDMA>,
<&iommu0 M4U_PORT_JPGDEC_WDMA>,
<&iommu0 M4U_PORT_JPGDEC_BSDMA>,
<&iommu0 M4U_PORT_VENC_NBM_WDMA>,
<&iommu0 M4U_PORT_VENC_NBM_WDMA_LITE>,
<&iommu0 M4U_PORT_VENC_CUR_LUMA>,
<&iommu0 M4U_PORT_VENC_CUR_CHROMA>,
<&iommu0 M4U_PORT_VENC_REF_LUMA>,
<&iommu0 M4U_PORT_VENC_REF_CHROMA>;
/* larb3-VENC-19 */
};
pseudo_m4u-larb5 {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <5>;
iommus = <&iommu0 M4U_PORT_IMGI>,
<&iommu0 M4U_PORT_IMG2O>,
<&iommu0 M4U_PORT_IMG3O>,
<&iommu0 M4U_PORT_VIPI>,
<&iommu0 M4U_PORT_LCEI>,
<&iommu0 M4U_PORT_SMXI>,
<&iommu0 M4U_PORT_SMXO>,
<&iommu0 M4U_PORT_WPE0_RDMA1>,
<&iommu0 M4U_PORT_WPE0_RDMA0>,
<&iommu0 M4U_PORT_WPE0_WDMA>,
<&iommu0 M4U_PORT_FDVT_RDB>,
<&iommu0 M4U_PORT_FDVT_WRA>,
<&iommu0 M4U_PORT_FDVT_RDA>,
<&iommu0 M4U_PORT_WPE1_RDMA0>,
<&iommu0 M4U_PORT_WPE1_RDMA1>,
<&iommu0 M4U_PORT_WPE1_WDMA>,
<&iommu0 M4U_PORT_DPE_RDMA>,
<&iommu0 M4U_PORT_DPE_WDMA>,
<&iommu0 M4U_PORT_MFB_RDMA0>,
<&iommu0 M4U_PORT_MFB_RDMA1>,
<&iommu0 M4U_PORT_MFB_WDMA>,
<&iommu0 M4U_PORT_RSC_RDMA0>,
<&iommu0 M4U_PORT_RSC_WDMA>,
<&iommu0 M4U_PORT_OWE_RDMA>,
<&iommu0 M4U_PORT_OWE_WDMA>,
<&iommu0 M4U_PORT_FDVT_WRB>;
/* larb5-IMG-26 */
};
pseudo_m4u-larb6 {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <6>;
iommus = <&iommu0 M4U_PORT_IMGO>,
<&iommu0 M4U_PORT_RRZO>,
<&iommu0 M4U_PORT_AAO>,
<&iommu0 M4U_PORT_AFO>,
<&iommu0 M4U_PORT_LSCI_0>,
<&iommu0 M4U_PORT_LSCI_1>,
<&iommu0 M4U_PORT_PDO>,
<&iommu0 M4U_PORT_BPCI>,
<&iommu0 M4U_PORT_LSCO>,
<&iommu0 M4U_PORT_AFO_1>,
<&iommu0 M4U_PORT_PSO>,
<&iommu0 M4U_PORT_LSCI_2>,
<&iommu0 M4U_PORT_SOCO>,
<&iommu0 M4U_PORT_SOC1>,
<&iommu0 M4U_PORT_SOC2>,
<&iommu0 M4U_PORT_CCUI>,
<&iommu0 M4U_PORT_CCUO>,
<&iommu0 M4U_PORT_UFEO>,
<&iommu0 M4U_PORT_RAWI_A>,
<&iommu0 M4U_PORT_RSSO_A>,
<&iommu0 M4U_PORT_CCUG>,
<&iommu0 M4U_PORT_PDI>,
<&iommu0 M4U_PORT_FLKO>,
<&iommu0 M4U_PORT_LMVO>,
<&iommu0 M4U_PORT_UFGO>,
<&iommu0 M4U_PORT_SPARE>,
<&iommu0 M4U_PORT_SPARE_2>,
<&iommu0 M4U_PORT_SPARE_3>,
<&iommu0 M4U_PORT_SPARE_4>,
<&iommu0 M4U_PORT_SPARE_5>,
<&iommu0 FAKE_ENGINE>;
/* larb6-IMG-31 */
};
pseudo_m4u-ccu {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <M4U_LARB_CCU>;
iommus = <&iommu0 M4U_PORT_CCU0>,
<&iommu0 M4U_PORT_CCU1>;
};
pseudo_m4u-apu {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <M4U_LARB_APU>;
iommus = <&iommu1 M4U_PORT_VPU>;
};
pseudo_m4u-apu-data {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <APU_PSEUDO_LARBID_DATA>;
iommus = <&iommu1 M4U_PORT_VPU_DATA>;
};
pseudo_m4u-misc {
compatible = "mediatek,mt-pseudo_m4u-port";
mediatek,larbid = <MISC_PSEUDO_LARBID_DISP>;
iommus = <&iommu0 M4U_PORT_DISP_FAKE0>;
};
#elif CONFIG_MTK_M4U
m4u@10220000 {
cell-index = <0>;
compatible = "mediatek,mm_m4u";
reg = <0 0x10220000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
#iommu-cells = <1>;
};
iommu0_bank1: m4u@10221000 {
cell-index = <0>;
compatible = "mediatek,bank1_m4u0";
reg = <0 0x10221000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
};
iommu0_bank2: m4u@10222000 {
cell-index = <0>;
compatible = "mediatek,bank2_m4u0";
reg = <0 0x10222000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
};
iommu0_bank3: m4u@10223000 {
cell-index = <0>;
compatible = "mediatek,bank3_m4u0";
reg = <0 0x10223000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
};
m4u@10224000 {
cell-index = <2>;
compatible = "mediatek,sec_m4u";
reg = <0 0x10224000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
};
m4u@1024f000 {
cell-index = <1>;
compatible = "mediatek,vpu_m4u";
reg = <0 0x1024f000 0 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
};
iommu1_bank1: m4u@10250000 {
cell-index = <1>;
compatible = "mediatek,bank1_m4u1";
reg = <0 0x10250000 0 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
};
iommu1_bank2: m4u@10251000 {
cell-index = <1>;
compatible = "mediatek,bank2_m4u1";
reg = <0 0x10251000 0 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
};
iommu1_bank3: m4u@10252000 {
cell-index = <1>;
compatible = "mediatek,bank3_m4u1";
reg = <0 0x10252000 0 0x1000>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
};
m4u@10253000 {
cell-index = <3>;
compatible = "mediatek,sec_vpu_m4u";
reg = <0 0x10253000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
};
#endif
scp_cfgreg@105c0000 {
compatible = "mediatek,scp_cfgreg";
reg = <0 0x105c0000 0 0x1000>;
};
scp_mad@105c1000 {
compatible = "mediatek,scp_mad";
reg = <0 0x105c1000 0 0x1000>;
};
scp_intc@105c2000 {
compatible = "mediatek,scp_intc";
reg = <0 0x105c2000 0 0x1000>;
};
scp_timer@105c3000 {
compatible = "mediatek,scp_timer";
reg = <0 0x105c3000 0 0x1000>;
};
scp_i2c0@105c5000 {
compatible = "mediatek,scp_i2c0";
reg = <0 0x105c5000 0 0x1000>;
};
scp_i2c1@105c6000 {
compatible = "mediatek,scp_i2c1";
reg = <0 0x105c6000 0 0x1000>;
};
scp_i2c2@105c7000 {
compatible = "mediatek,scp_i2c2";
reg = <0 0x105c7000 0 0x1000>;
};
scp_gpio@105c8000 {
compatible = "mediatek,scp_gpio";
reg = <0 0x105c8000 0 0x1000>;
};
scp_uart@105c9000 {
compatible = "mediatek,scp_uart";
reg = <0 0x105c9000 0 0x1000>;
};
scp_cirq_eint@105ca000 {
compatible = "mediatek,scp_cirq_eint";
reg = <0 0x105ca000 0 0x1000>;
};
scp_dma@105cd000 {
compatible = "mediatek,scp_dma";
reg = <0 0x105cd000 0 0x1000>;
};
scp_uart1@105ce000 {
compatible = "mediatek,scp_uart1";
reg = <0 0x105ce000 0 0x1000>;
};
scp_spi0@105cf000 {
compatible = "mediatek,scp_spi0";
reg = <0 0x105cf000 0 0x1000>;
};
scp_spi1@105d0000 {
compatible = "mediatek,scp_spi1";
reg = <0 0x105d0000 0 0x1000>;
};
scp_spi2@105d1000 {
compatible = "mediatek,scp_spi2";
reg = <0 0x105d1000 0 0x1000>;
};
dbgapb@0d000000 {
compatible = "mediatek,dbgapb";
reg = <0 0x0d000000 0 0x1000>;
};
mcucci@0c510000 {
compatible = "mediatek,mcucci";
reg = <0 0x0c510000 0 0x1000>;
};
mcdi:mcdi@0011b000 {
compatible = "mediatek,mt6785-mcdi";
mediatek,enabled = <1>;
reg = <0 0x0011b000 0 0x800>,
<0 0x0c53a000 0 0x1000>;
};
qos@0011bb80 {
compatible = "mediatek,qos-2.0";
reg = <0 0x0011bb80 0 0x80>;
};
mcusys_par_wrap@0c530000 {
compatible = "mediatek,mcusys_par_wrap";
reg = <0 0x0c530000 0 0x1000>;
};
mcucfg_mp0_counter@0c530000 {
compatible = "mediatek,mcucfg_mp0_counter";
reg = <0 0x0c530000 0 0x10000>;
};
dcm: dcm {
compatible = "mediatek,dcm";
};
mcucfg: mcucfg@0c530000 {
compatible = "mediatek,mcucfg";
reg = <0 0x0c530000 0 0x10000>;
};
mp_cpusys_top@0c538000 {
compatible = "mediatek,mp_cpusys_top";
reg = <0 0x0c538000 0 0x1000>;
};
cpccfg_reg@0c53a800 {
compatible = "mediatek,cpccfg_reg";
reg = <0 0x0c53a800 0 0x1000>;
};
cpcdbg_reg@0c53ab00 {
compatible = "mediatek,cpcdbg_reg";
reg = <0 0x0c53ab00 0 0x1000>;
};
cpcspmc_reg@0c53a700 {
compatible = "mediatek,cpcspmc_reg";
reg = <0 0x0c53a700 0 0x1000>;
};
infracfg@1020e000 {
compatible = "mediatek,infracfg";
reg = <0 0x1020e000 0 0x1000>;
};
sramrom@10214000 {
compatible = "mediatek,sramrom";
reg = <0 0x10214000 0 0x1000>;
};
emi:emi@10219000 {
compatible = "mediatek,emi";
reg = <0 0x10219000 0 0x1000>, /* CEN EMI */
<0 0x10226000 0 0x1000>, /* MPU */
<0 0x10235000 0 0x1000>, /* CH0 EMI */
<0 0x10245000 0 0x1000>, /* CH1 EMI */
<0 0x1020e000 0 0x1000>; /* dbg0 */
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>;
/* 0: golden setting, 1: on, 2: off, DCM */
emi_dcm = <0>;
};
device_mpu@1021a000 {
compatible = "mediatek,device_mpu";
reg = <0 0x1021a000 0 0x1000>;
};
sys_cirq@10204000 {
compatible = "mediatek,sys_cirq";
reg = <0 0x10204000 0 0x1000>;
mediatek,cirq_num = <277>;
mediatek,spi_start_offset = <64>;
sw_reset = <1>;
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_LOW>;
};
devapc@10207000 {
compatible = "mediatek,mt6785-devapc";
reg = <0 0x10207000 0 0x1000>,
<0 0x1000e000 0 0x1000>,
<0 0x10033000 0 0x1000>,
<0 0x0011a000 0 0x1000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_DEVICE_APC_CG>;
clock-names = "devapc-infra-clock";
};
bus_dbg@10208000 {
compatible = "mediatek,bus_dbg-v2";
reg = <0 0x10208000 0 0x1000>,
<0 0x10001000 0 0x1000>;
mediatek,bus_dbg_con_offset = <0x2fc>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
};
ap_ccif0@10209000 {
compatible = "mediatek,ap_ccif0";
reg = <0 0x10209000 0 0x1000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>;
};
md_ccif0@1020a000 {
compatible = "mediatek,md_ccif0";
reg = <0 0x1020a000 0 0x1000>;
};
ap_ccif1@1020b000 {
compatible = "mediatek,ap_ccif1";
reg = <0 0x1020b000 0 0x1000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>;
};
md_ccif1@1020c000 {
compatible = "mediatek,md_ccif1";
reg = <0 0x1020c000 0 0x1000>;
};
ap_ccif2@1023c000 {
compatible = "mediatek,ap_ccif2";
reg = <0 0x1023c000 0 0x1000>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>;
};
md_ccif2@1023d000 {
compatible = "mediatek,md_ccif2";
reg = <0 0x1023d000 0 0x1000>;
};
ap_ccif3@1023e000 {
compatible = "mediatek,ap_ccif3";
reg = <0 0x1023e000 0 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
};
md_ccif3@1023f000 {
compatible = "mediatek,md_ccif3";
reg = <0 0x1023f000 0 0x1000>;
};
ap_ccif4@1024c000 {
compatible = "mediatek,ap_ccif4";
reg = <0 0x1024c000 0 0x1000>;
};
md_ccif4@1024d000 {
compatible = "mediatek,md_ccif4";
reg = <0 0x1024d000 0 0x1000>;
};
infra_mbist@1020d000 {
compatible = "mediatek,infra_mbist";
reg = <0 0x1020d000 0 0x1000>;
};
hwrng: hwrng {
compatible = "mediatek,mt67xx-rng";
};
dxcc_sec@10210000 {
compatible = "mediatek,dxcc_sec";
reg = <0 0x10210000 0 0x1000>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
};
smi_common_ao@10211000 {
compatible = "mediatek,smi_common_ao";
reg = <0 0x10211000 0 0x1000>;
};
cq_dma@10212000 {
compatible = "mediatek,mt-cqdma-v1";
reg = <0 0x10212000 0 0x80>,
<0 0x10212080 0 0x80>,
<0 0x10212100 0 0x80>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
nr_channel = <3>;
clocks = <&infracfg_ao INFRACFG_AO_CQ_DMA_CG>;
clock-names = "cqdma";
};
#if 0
mm_iommu@10220000 {
compatible = "mediatek,mm_iommu";
reg = <0 0x10220000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
};
mm_iommu_bank1@10221000 {
compatible = "mediatek,mm_iommu_bank1";
reg = <0 0x10221000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
};
mm_iommu_bank2@10222000 {
compatible = "mediatek,mm_iommu_bank2";
reg = <0 0x10222000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
};
mm_iommu_bank3@10223000 {
compatible = "mediatek,mm_iommu_bank3";
reg = <0 0x10223000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
};
mm_iommu_bank4@10224000 {
compatible = "mediatek,mm_iommu_bank4";
reg = <0 0x10224000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
};
vpu_iommu@1024f000 {
compatible = "mediatek,vpu_iommu";
reg = <0 0x1024f000 0 0x1000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
};
vpu_iommu_bank1@10250000 {
compatible = "mediatek,vpu_iommu_bank1";
reg = <0 0x10250000 0 0x1000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
};
vpu_iommu_bank2@10251000 {
compatible = "mediatek,vpu_iommu_bank2";
reg = <0 0x10251000 0 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
};
vpu_iommu_bank3@10252000 {
compatible = "mediatek,vpu_iommu_bank3";
reg = <0 0x10252000 0 0x1000>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
};
vpu_iommu_bank4@10253000 {
compatible = "mediatek,vpu_iommu_bank4";
reg = <0 0x10253000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
};
#endif
mm_vpu_m0_smi_common@10254000 {
compatible = "mediatek,mm_vpu_m0_smi_common";
reg = <0 0x10254000 0 0x1000>;
};
mm_vpu_m1_smi_common@10255000 {
compatible = "mediatek,mm_vpu_m1_smi_common";
reg = <0 0x10255000 0 0x1000>;
};
axi2acp_smi_common@10256000 {
compatible = "mediatek,axi2acp_smi_common";
reg = <0 0x10256000 0 0x1000>;
};
mipi_tx0@11e50000 {
compatible = "mediatek,mipi_tx0";
reg = <0 0x11e50000 0 0x1000>;
};
mipi_tx1@10216000 {
compatible = "mediatek,mipi_tx1";
reg = <0 0x10216000 0 0x1000>;
};
mipi_rx_ana_csi0a@11c80000 {
compatible = "mediatek,mipi_rx_ana_csi0a";
reg = <0 0x11c80000 0 0x1000>;
};
mipi_rx_ana_csi0b@11c81000 {
compatible = "mediatek,mipi_rx_ana_csi0b";
reg = <0 0x11c81000 0 0x1000>;
};
mipi_rx_ana_csi1a@11c82000 {
compatible = "mediatek,mipi_rx_ana_csi1a";
reg = <0 0x11c82000 0 0x1000>;
};
mipi_rx_ana_csi1b@11c83000 {
compatible = "mediatek,mipi_rx_ana_csi1b";
reg = <0 0x11c83000 0 0x1000>;
};
mipi_rx_ana_csi2a@11c84000 {
compatible = "mediatek,mipi_rx_ana_csi2a";
reg = <0 0x11c84000 0 0x1000>;
};
mipi_rx_ana_csi2b@11c85000 {
compatible = "mediatek,mipi_rx_ana_csi2b";
reg = <0 0x11c85000 0 0x1000>;
};
apcldmain@1021b000 {
compatible = "mediatek,apcldmain";
reg = <0 0x1021b000 0 0x1000>;
};
apcldmaout@1021b400 {
compatible = "mediatek,apcldmaout";
reg = <0 0x1021b400 0 0x1000>;
};
apcldmamisc@1021b800 {
compatible = "mediatek,apcldmamisc";
reg = <0 0x1021b800 0 0x1000>;
};
mdcldmain@1021c000 {
compatible = "mediatek,mdcldmain";
reg = <0 0x1021c000 0 0x1000>;
};
mdcldmaout@1021c400 {
compatible = "mediatek,mdcldmaout";
reg = <0 0x1021c400 0 0x1000>;
};
mdcldmamisc@1021c800 {
compatible = "mediatek,mdcldmamisc";
reg = <0 0x1021c800 0 0x1000>;
};
infra_md@1021d000 {
compatible = "mediatek,infra_md";
reg = <0 0x1021d000 0 0x1000>;
};
infra_md_cfg@1021d000 {
compatible = "mediatek,infra_md_cfg";
reg = <0 0x1021d000 0 0x1000>;
};
bpi_bsi_slv0@1021e000 {
compatible = "mediatek,bpi_bsi_slv0";
reg = <0 0x1021e000 0 0x1000>;
};
bpi_bsi_slv1@1021f000 {
compatible = "mediatek,bpi_bsi_slv1";
reg = <0 0x1021f000 0 0x1000>;
};
bpi_bsi_slv2@10225000 {
compatible = "mediatek,bpi_bsi_slv2";
reg = <0 0x10225000 0 0x1000>;
};
emi_mpu@10226000 {
compatible = "mediatek,emi_mpu";
reg = <0 0x10226000 0 0x1000>;
};
dvfsp@10227000 {
compatible = "mediatek,dvfsp";
reg = <0 0x10227000 0 0x1000>;
};
dvfsp: dvfsp@0011bc00 {
compatible = "mediatek,mt6785-dvfsp";
reg = <0 0x0011bc00 0 0x1400>,
<0 0x0011bc00 0 0x1400>;
state = <1>;
imax_state = <2>;
change_flag = <0>;
little-rise-time = <1000>;
little-down-time = <750>;
big-rise-time = <1000>;
big-down-time = <750>;
L-table = <2000 96 1 1
1933 92 1 1
1866 88 1 1
1800 83 1 1
1733 80 1 1
1666 75 1 1
1548 71 1 1
1475 66 2 1
1375 64 2 1
1275 58 2 1
1175 54 2 1
1075 49 2 1
999 46 2 1
925 43 2 1
850 40 2 1
774 38 2 1 >;
B-table = <2200 100 1 1
2133 96 1 1
2066 92 1 1
2000 88 1 1
1933 84 1 1
1866 80 1 1
1800 75 1 1
1651 70 1 1
1503 64 1 1
1414 61 2 1
1295 57 2 1
1176 53 2 1
1087 49 2 1
998 46 2 1
909 43 2 1
850 40 2 1 >;
CCI-table = <1400 96 2 1
1353 92 2 1
1306 88 2 1
1260 84 2 1
1190 78 2 1
1155 75 2 1
1120 71 2 1
984 64 2 1
917 62 2 1
827 58 2 1
737 54 2 2
669 51 2 2
579 47 2 2
512 44 2 2
445 41 2 2
400 38 2 2 >;
};
mt_cpufreq: mt_cpufreq {
compatible = "mediatek,mt-cpufreq";
};
gce@10228000 {
compatible = "mediatek,gce";
reg = <0 0x10228000 0 0x4000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
disp_mutex_reg = <0x14016000 0x1000>;
g3d_config_base = <0x13000000 0 0xffff0000>;
mmsys_config_base = <0x14000000 1 0xffff0000>;
disp_dither_base = <0x14010000 2 0xffff0000>;
mm_na_base = <0x14020000 3 0xffff0000>;
imgsys_base = <0x15020000 4 0xffff0000>;
vdec_gcon_base = <0x18800000 5 0xffff0000>;
venc_gcon_base = <0x18810000 6 0xffff0000>;
conn_peri_base = <0x18820000 7 0xffff0000>;
topckgen_base = <0x18830000 8 0xffff0000>;
kp_base = <0x18840000 9 0xffff0000>;
scp_sram_base = <0x10000000 10 0xffff0000>;
infra_na3_base = <0x10010000 11 0xffff0000>;
infra_na4_base = <0x10020000 12 0xffff0000>;
scp_base = <0x10030000 13 0xffff0000>;
mcucfg_base = <0x10040000 14 0xffff0000>;
gcpu_base = <0x10050000 15 0xffff0000>;
usb0_base = <0x10200000 16 0xffff0000>;
usb_sif_base = <0x10280000 17 0xffff0000>;
audio_base = <0x17000000 18 0xffff0000>;
vdec_base = <0x17010000 19 0xffff0000>;
msdc2_base = <0x17020000 20 0xffff0000>;
vdec1_base = <0x17030000 21 0xffff0000>;
msdc3_base = <0x18000000 22 0xffff0000>;
ap_dma_base = <0x18010000 23 0xffff0000>;
gce_base = <0x18020000 24 0xffff0000>;
vdec2_base = <0x18040000 25 0xffff0000>;
vdec3_base = <0x18050000 26 0xffff0000>;
camsys_base = <0x18080000 27 0xffff0000>;
camsys1_base = <0x180a0000 28 0xffff0000>;
camsys2_base = <0x180b0000 29 0xffff0000>;
pwm_sw_base = <0x1100e000 99 0xffff0000>;
mipitx0_base = <0x11e50000 99 0xffff0000>;
disp_rdma0_sof = <0>;
disp_rdma1_sof = <1>;
mdp_rdma0_sof = <2>;
mdp_rdma1_sof = <3>;
mdp_rsz0_sof = <4>;
mdp_rsz1_sof = <5>;
mdp_tdshp_sof = <6>;
mdp_wrot0_sof = <7>;
mdp_wrot1_sof = <8>;
disp_ovl0_sof = <9>;
disp_2l_ovl0_sof = <10>;
disp_2l_ovl1_sof = <11>;
disp_wdma0_sof = <12>;
disp_color0_sof = <13>;
disp_ccorr0_sof = <14>;
disp_aal0_sof = <15>;
disp_gamma0_sof = <16>;
disp_dither0_sof = <17>;
disp_pwm0_sof = <18>;
disp_dsi0_sof = <19>;
disp_dpi0_sof = <20>;
disp_postmask0_sof = <21>;
disp_rsz0_sof = <22>;
mdp_aal_sof = <23>;
mdp_ccorr_sof = <24>;
disp_dbi0_sof = <25>;
isp_relay_sof = <26>;
ipu_relay_sof = <27>;
disp_rdma0_frame_done = <28>;
disp_rdma1_frame_done = <29>;
mdp_rdma0_frame_done = <30>;
mdp_rdma1_frame_done = <31>;
mdp_rsz0_frame_done = <32>;
mdp_rsz1_frame_done = <33>;
mdp_tdshp_frame_done = <34>;
mdp_wrot0_write_frame_done = <35>;
mdp_wrot1_write_frame_done = <36>;
disp_ovl0_frame_done = <37>;
disp_2l_ovl0_frame_done = <38>;
disp_2l_ovl1_frame_done = <39>;
disp_wdma0_frame_done = <40>;
disp_color0_frame_done = <41>;
disp_ccorr0_frame_done = <42>;
disp_aal0_frame_done = <43>;
disp_gamma0_frame_done = <44>;
disp_dither0_frame_done = <45>;
disp_dsi0_frame_done = <46>;
disp_dpi0_frame_done = <47>;
disp_rsz0_frame_done = <49>;
mdp_aal_frame_done = <50>;
mdp_ccorr_frame_done = <51>;
disp_postmask0_frame_done = <52>;
stream_done_0 = <130>;
stream_done_1 = <131>;
stream_done_2 = <132>;
stream_done_3 = <133>;
stream_done_4 = <134>;
stream_done_5 = <135>;
stream_done_6 = <136>;
stream_done_7 = <137>;
stream_done_8 = <138>;
stream_done_9 = <139>;
stream_done_10 = <140>;
stream_done_11 = <141>;
buf_underrun_event_0 = <142>;
buf_underrun_event_1 = <143>;
buf_underrun_event_2 = <144>;
buf_underrun_event_3 = <145>;
dsi0_te_event = <146>;
dsi0_irq_event = <147>;
dsi0_done_event = <148>;
disp_postmask0_frame_rst_done_pulse = <150>;
disp_wdma0_rst_done = <151>;
mdp_wrot0_rst_done = <153>;
mdp_rdma0_rst_done = <154>;
disp_ovl0_frame_rst_done_pusle = <155>;
disp_ovl0_2l_frame_rst_done_pusle = <156>;
disp_ovl1_2l_frame_rst_done_pusle = <157>;
dip_cq_thread0_frame_done = <257>;
dip_cq_thread1_frame_done = <258>;
dip_cq_thread2_frame_done = <259>;
dip_cq_thread3_frame_done = <260>;
dip_cq_thread4_frame_done = <261>;
dip_cq_thread5_frame_done = <262>;
dip_cq_thread6_frame_done = <263>;
dip_cq_thread7_frame_done = <264>;
dip_cq_thread8_frame_done = <265>;
dip_cq_thread9_frame_done = <266>;
dip_cq_thread10_frame_done = <267>;
dip_cq_thread11_frame_done = <268>;
dip_cq_thread12_frame_done = <269>;
dip_cq_thread13_frame_done = <270>;
dip_cq_thread14_frame_done = <271>;
dip_cq_thread15_frame_done = <272>;
dip_cq_thread16_frame_done = <273>;
dip_cq_thread17_frame_done = <274>;
dip_cq_thread18_frame_done = <275>;
amd_frame_done = <276>;
dve_done = <277>;
wmfe_done = <278>;
rsc_frame_done = <279>;
mfb_done = <280>;
wpe_a_frame_done = <281>;
wpe_b_frame_done = <282>;
occ_done = <283>;
venc_cmdq_frame_done = <289>;
venc_cmdq_pause_done = <290>;
jpgenc_cmdq_done = <291>;
venc_cmdq_mb_done = <292>;
venc_cmdq_128byte_cnt_done = <293>;
isp_frame_done_a = <321>;
isp_frame_done_b = <322>;
camsv0_pass1_done = <323>;
camsv1_pass1_done = <324>;
camsv2_pass1_done = <325>;
tsf_done = <326>;
seninf_0_fifo_full = <327>;
seninf_1_fifo_full = <328>;
seninf_2_fifo_full = <329>;
seninf_3_fifo_full = <330>;
seninf_4_fifo_full = <331>;
seninf_5_fifo_full = <332>;
seninf_6_fifo_full = <333>;
seninf_7_fifo_full = <334>;
apu_gce_core0_event_0 = <353>;
apu_gce_core0_event_1 = <354>;
apu_gce_core0_event_2 = <355>;
apu_gce_core0_event_3 = <356>;
apu_gce_core1_event_0 = <385>;
apu_gce_core1_event_1 = <386>;
apu_gce_core1_event_2 = <387>;
apu_gce_core1_event_3 = <388>;
vdec_event_0 = <416>;
vdec_event_1 = <417>;
vdec_event_2 = <418>;
vdec_event_3 = <419>;
vdec_event_4 = <420>;
vdec_event_5 = <421>;
vdec_event_6 = <422>;
vdec_event_7 = <423>;
vdec_event_8 = <424>;
vdec_event_9 = <425>;
vdec_event_10 = <426>;
vdec_event_11 = <427>;
vdec_event_12 = <428>;
vdec_event_13 = <429>;
vdec_event_14 = <430>;
vdec_event_15 = <431>;
dsi0_te_from_infra = <898>;
mmsys_config = <&mmsys_config>;
mm_mutex = <&mm_mutex>;
mdp_rdma0 = <&mdp_rdma0>;
mdp_rdma1 = <&mdp_rdma1>;
mdp_rsz0 = <&mdp_rsz0>;
mdp_rsz1 = <&mdp_rsz1>;
mdp_wrot0 = <&mdp_wrot0>;
mdp_wrot1 = <&mdp_wrot1>;
mdp_tdshp0 = <&mdp_tdshp>;
mdp_aal0 = <&mdp_aal>;
mdp_hdr0 = <&mdp_hdr>;
mdp_color0 = <&disp_color0>;
smi_larb0 = <&smi_larb0>;
mediatek,mailbox-gce = <&gce_mbox>;
sram_share_cnt = <2>;
sram_share_engine = <21>, <22>;
sram_share_event = <710>, <711>;
// #if defined(CONFIG_MTK_MT6382_DBG)
thread_count = <56>;
// #else
// thread_count = <24>;
// #endif
secure_thread = <8 11>;
mboxes = <&gce_mbox 0 0 CMDQ_THR_PRIO_4>,
<&gce_mbox 1 0 CMDQ_THR_PRIO_4>,
<&gce_mbox 2 0 CMDQ_THR_PRIO_5>,
<&gce_mbox 3 0 CMDQ_THR_PRIO_4>,
<&gce_mbox 4 0 CMDQ_THR_PRIO_4>,
<&gce_mbox 5 0 CMDQ_THR_PRIO_4>,
<&gce_mbox 6 0 CMDQ_THR_PRIO_3>,
<&gce_mbox 7 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
<&gce_mbox_svp 8 0 CMDQ_THR_PRIO_4>,
<&gce_mbox_svp 9 0 CMDQ_THR_PRIO_4>,
<&gce_mbox_svp 10 0 CMDQ_THR_PRIO_1>,
<&gce_mbox_svp 11 0 CMDQ_THR_PRIO_1>,
#else
<&gce_mbox 8 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 9 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 10 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 11 0 CMDQ_THR_PRIO_1>,
#endif
<&gce_mbox 12 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 13 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 14 0 CMDQ_THR_PRIO_1>,
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
<&gce_mbox 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
#else
<&gce_mbox 15 0 CMDQ_THR_PRIO_1>,
#endif
<&gce_mbox 18 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 19 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 20 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 21 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 22 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 23 0 CMDQ_THR_PRIO_1>;
gce-cpr-range = <0 GCE_CPR_COUNT>;
clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>,
<&infracfg_ao INFRACFG_AO_GCE_26M_CG>;
clock-names = "GCE", "GCE_TIMER";
gce_mbox_bdg = <&gce_mbox_bdg>;
};
gce_mbox: gce_mbox@10228000 {
compatible = "mediatek,mt6785-gce";
reg = <0 0x10228000 0 0x4000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
#mbox-cells = <3>;
#gce-event-cells = <1>;
#gce-subsys-cells = <2>;
default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>,
<&infracfg_ao INFRACFG_AO_GCE_26M_CG>;
clock-names = "gce", "gce-timer";
};
gce_mbox_bdg: gce_mbox_bdg {
compatible = "mediatek,mailbox-gce-bdg";
#mbox-cells = <3>;
#gce-event-cells = <1>;
#gce-subsys-cells = <2>;
mboxes = <&gce_mbox_bdg 20 0 CMDQ_THR_PRIO_2>,
<&gce_mbox_bdg 21 0 CMDQ_THR_PRIO_1>;
};
cmdq-bdg-test {
compatible = "mediatek,cmdq-bdg-test";
mediatek,gce = <&gce_mbox_bdg>;
mboxes = <&gce_mbox_bdg 22 0 CMDQ_THR_PRIO_2>,
<&gce_mbox_bdg 23 0 CMDQ_THR_PRIO_1>;
token_user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
token_gpr_set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
};
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
gce_mbox_svp: gce_mbox_svp@10228000 {
compatible = "mediatek,mailbox-gce-svp";
reg = <0 0x10228000 0 0x4000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
#mbox-cells = <3>;
clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>,
<&infracfg_ao INFRACFG_AO_GCE_26M_CG>;
clock-names = "gce", "gce-timer";
};
#endif
chn0_emi@10235000 {
compatible = "mediatek,chn0_emi";
reg = <0 0x10235000 0 0x1000>;
};
dramc@10230000 {
compatible = "mediatek,dramc";
reg = <0 0x10230000 0 0x2000>,
<0 0x10240000 0 0x2000>,
<0 0x10234000 0 0x1000>,
<0 0x10244000 0 0x1000>,
<0 0x10238000 0 0x2000>,
<0 0x10248000 0 0x2000>,
<0 0x10236000 0 0x1000>,
<0 0x10246000 0 0x1000>;
};
chn1_emi@10245000 {
compatible = "mediatek,chn1_emi";
reg = <0 0x10245000 0 0x1000>;
};
fmem_smi@1024e000 {
compatible = "mediatek,fmem_smi";
reg = <0 0x1024e000 0 0x1000>;
};
gic@1024e000 {
compatible = "mediatek,gic";
reg = <0 0x1024e000 0 0x1000>;
};
sspm@10400000 {
compatible = "mediatek,sspm";
reg = <0 0x10400000 0 0x28000>,
<0 0x10440000 0 0x10000>,
<0 0x10450000 0 0x100>,
<0 0x10451000 0 0x8>,
<0 0x10460000 0 0x100>,
<0 0x10461000 0 0x8>,
<0 0x10470000 0 0x100>,
<0 0x10471000 0 0x8>,
<0 0x10480000 0 0x100>,
<0 0x10481000 0 0x8>,
<0 0x10490000 0 0x100>,
<0 0x10491000 0 0x8>;
reg-names = "sspm_base",
"cfgreg",
"mbox0_base",
"mbox0_ctrl",
"mbox1_base",
"mbox1_ctrl",
"mbox2_base",
"mbox2_ctrl",
"mbox3_base",
"mbox3_ctrl",
"mbox4_base",
"mbox4_ctrl";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipc",
"mbox0",
"mbox1",
"mbox2",
"mbox3",
"mbox4";
sspm_mem_key = "mediatek,reserve-memory-sspm_share";
sspm_mem_tbl = <0 0x100100>, /* logger header + log buffer */
<1 0x300>, /* PWRAP 768bytes*/
<2 0xc00>, /* PMIC 3K */
<3 0x1800>, /* UPD 6K */
<4 0x1000>, /* QOS 4K*/
<5 0x1800>, /* SWPM 6K*/
#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
#else
<6 0x400000>, /* MET 4M */
#endif
<7 0x9000>, /* SMI 36K */
<8 0x1000>; /* GPU 4K */
sspm_share_buffer_supported; /* share_buffer supported */
};
adsp_common: adsp_common@10600000 {
compatible = "mediatek,adsp_common";
reg = <0 0x10001000 0 0x1000>, /* infracfg_ao */
<0 0x10003000 0 0x1000>; /* pericfg */
clocks = <&infracfg_ao INFRACFG_AO_FADSP_CG>,
<&topckgen TOP_MUX_ADSP>,
<&clk26m>,
<&topckgen TOP_MMPLL_D4>,
<&topckgen TOP_ADSPPLL_D4>,
<&topckgen TOP_ADSPPLL_D6>;
clock-names = "clk_adsp_infra",
"clk_top_adsp_sel",
"clk_adsp_clk26m",
"clk_top_mmpll_d4",
"clk_top_adsppll_d4",
"clk_top_adsppll_d6";
adsp-rsv-ipidma-a = <0x200000>;
adsp-rsv-logger-a = <0x80000>;
adsp-rsv-dbg-dump-a = <0x80000>;
adsp-rsv-core-dump-a = <0x400>;
adsp-rsv-audio = <0x5c0000>;
};
adsp_core0: adsp_core0@10610000 {
compatible = "mediatek,adsp_core_0";
reg = <0 0x10600000 0 0x10000>, /* CFG */
<0 0x10630000 0 0x9000>, /* ITCM */
<0 0x10610000 0 0x8000>; /* DTCM */
system = <0 0x56000000 0 0x700000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
};
ap_dma@11000000 {
compatible = "mediatek,ap_dma";
reg = <0 0x11000000 0 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
};
auxadc: auxadc@11001000 {
compatible = "mediatek,mt6785-auxadc",
"mediatek,mt6765-auxadc";
reg = <0 0x11001000 0 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_FALLING>;
clocks = <&infracfg_ao INFRACFG_AO_AUXADC_CG>;
clock-names = "main";
#io-channel-cells = <1>;
/* Auxadc efuse calibration */
/* 1. Auxadc cali on/off bit shift */
mediatek,cali-en-bit = <20>;
/* 2. Auxadc cali ge bits shift */
mediatek,cali-ge-bit = <10>;
/* 3. Auxadc cali oe bits shift */
mediatek,cali-oe-bit = <0>;
/* 4. Auxadc cali efuse reg offset */
mediatek,cali-efuse-reg-offset = <0x1a8>;
nvmem = <&efuse>;
nvmem-names = "mtk_efuse";
#interconnect-cells = <1>;
};
apdma: dma-controller@11000880 {
compatible = "mediatek,mt6577-uart-dma";
reg = <0 0x11000880 0 0x80>,
<0 0x11000900 0 0x80>,
<0 0x11000980 0 0x80>,
<0 0x11000A00 0 0x80>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_LOW>;
dma-requests = <4>;
clocks = <&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "apdma";
#dma-cells = <1>;
dma-bits = <34>;
};
apuart0: serial@11002000 {
compatible = "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg_ao INFRACFG_AO_UART0_CG>;
clock-names = "baud", "bus";
dmas = <&apdma 0
&apdma 1>;
dma-names = "tx", "rx";
};
apuart1: serial@11003000 {
compatible = "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg_ao INFRACFG_AO_UART1_CG>;
clock-names = "baud", "bus";
dmas = <&apdma 2
&apdma 3>;
dma-names = "tx", "rx";
};
i2c_common: i2c_common {
compatible = "mediatek,i2c_common";
dma_support = /bits/ 8 <3>;
idvfs = /bits/ 8 <1>;
set_dt_div = /bits/ 8 <1>;
check_max_freq = /bits/ 8 <1>;
ver = /bits/ 8 <2>;
set_ltiming = /bits/ 8 <1>;
ext_time_config = /bits/ 16 <0x1801>;
cnt_constraint = /bits/ 8 <1>;
};
i2c0: i2c0@11007000 {
compatible = "mediatek,i2c";
id = <0>;
reg = <0 0x11007000 0 0x1000>,
<0 0x11000080 0 0x80>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
scl-gpio-id = <51>;
sda-gpio-id = <52>;
gpio_start = <0x11ea0000>;
mem_len = <0x1000>;
eh_cfg = <0x40>;
pu_cfg = <0xa0>;
rsel_cfg = <0x100>;
aed = <0x1a>;
};
i2c1: i2c1@11008000 {
compatible = "mediatek,i2c";
id = <1>;
reg = <0 0x11008000 0 0x1000>,
<0 0x11000100 0 0x80>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
scl-gpio-id = <61>;
sda-gpio-id = <62>;
gpio_start = <0x11e20000>;
mem_len = <0x1000>;
eh_cfg = <0x10>;
pu_cfg = <0x40>;
rsel_cfg = <0x60>;
aed = <0x1a>;
};
i2c2: i2c2@11009000 {
compatible = "mediatek,i2c";
id = <2>;
reg = <0 0x11009000 0 0x1000>,
<0 0x11000180 0 0x180>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
scl-gpio-id = <112>;
sda-gpio-id = <113>;
gpio_start = <0x11d10000>;
mem_len = <0x1000>;
eh_cfg = <0x30>;
pu_cfg = <0xa0>;
rsel_cfg = <0xd0>;
aed = <0x1a>;
ch_offset_default = <0x100>;
ch_offset_ccu = <0x200>;
};
i2c3: i2c3@1100f000 {
compatible = "mediatek,i2c";
id = <3>;
reg = <0 0x1100f000 0 0x1000>,
<0 0x11000300 0 0x80>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
scl-gpio-id = <55>;
sda-gpio-id = <56>;
gpio_start = <0x11ea0000>;
mem_len = <0x1000>;
eh_cfg = <0x40>;
pu_cfg = <0xa0>;
rsel_cfg = <0x100>;
aed = <0x1a>;
};
i2c4: i2c4@11011000 {
compatible = "mediatek,i2c";
id = <4>;
reg = <0 0x11011000 0 0x1000>,
<0 0x11000380 0 0x180>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
scl-gpio-id = <110>;
sda-gpio-id = <111>;
gpio_start = <0x11d10000>;
mem_len = <0x1000>;
eh_cfg = <0x30>;
pu_cfg = <0xa0>;
rsel_cfg = <0xd0>;
aed = <0x1a>;
ch_offset_default = <0x100>;
ch_offset_ccu = <0x200>;
};
i2c5: i2c5@11016000 {
compatible = "mediatek,i2c";
id = <5>;
reg = <0 0x11016000 0 0x1000>,
<0 0x11000500 0 0x80>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
scl-gpio-id = <28>;
sda-gpio-id = <29>;
gpio_start = <0x11f20000>;
mem_len = <0x1000>;
eh_cfg = <0x20>;
pu_cfg = <0x80>;
rsel_cfg = <0xc0>;
aed = <0x1a>;
};
i2c6: i2c6@11005000 {
compatible = "mediatek,i2c";
id = <6>;
reg = <0 0x11005000 0 0x1000>,
<0 0x11000580 0 0x100>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
scl-gpio-id = <45>;
sda-gpio-id = <46>;
gpio_start = <0x11ea0000>;
mem_len = <0x1000>;
eh_cfg = <0x40>;
pu_cfg = <0xa0>;
rsel_cfg = <0x100>;
aed = <0x1a>;
};
i2c7: i2c7@1101a000 {
compatible = "mediatek,i2c";
id = <7>;
reg = <0 0x1101a000 0 0x1000>,
<0 0x11000680 0 0x100>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
scl-gpio-id = <198>;
sda-gpio-id = <199>;
gpio_start = <0x11ea0000>;
mem_len = <0x1000>;
eh_cfg = <0x40>;
pu_cfg = <0xa0>;
rsel_cfg = <0x100>;
aed = <0x1a>;
ch_offset_default = <0x100>;
};
i2c8: i2c8@1101b000 {
compatible = "mediatek,i2c";
id = <8>;
reg = <0 0x1101b000 0 0x1000>,
<0 0x11000780 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
aed = <0x1a>;
};
i2c9: i2c9@11015000 {
compatible = "mediatek,i2c";
id = <9>;
reg = <0 0x11015000 0 0x1000>,
<0 0x11000800 0 0x80>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_I2C0_CG>,
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
clock-names = "main", "dma";
clock-div = <5>;
aed = <0x1a>;
};
pwm@11006000 {
compatible = "mediatek,pwm";
reg = <0 0x11006000 0 0x1000>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_PWM1_CG>,
<&infracfg_ao INFRACFG_AO_PWM2_CG>,
<&infracfg_ao INFRACFG_AO_PWM3_CG>,
<&infracfg_ao INFRACFG_AO_PWM4_CG>,
<&infracfg_ao INFRACFG_AO_PWM_HCLK_CG>,
<&infracfg_ao INFRACFG_AO_PWM_CG>;
clock-names = "PWM1-main",
"PWM2-main",
"PWM3-main",
"PWM4-main",
"PWM-HCLK-main",
"PWM-main";
};
spi0: spi0@1100a000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x1100a000 0 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MAINPLL_D5_D2>,
<&topckgen TOP_MUX_SPI>,
<&infracfg_ao INFRACFG_AO_SPI0_CG>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi1: spi1@11010000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11010000 0 0x1000>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MAINPLL_D5_D2>,
<&topckgen TOP_MUX_SPI>,
<&infracfg_ao INFRACFG_AO_SPI1_CG>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi2: spi2@11012000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11012000 0 0x1000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MAINPLL_D5_D2>,
<&topckgen TOP_MUX_SPI>,
<&infracfg_ao INFRACFG_AO_SPI2_CG>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi3: spi3@11013000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11013000 0 0x1000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MAINPLL_D5_D2>,
<&topckgen TOP_MUX_SPI>,
<&infracfg_ao INFRACFG_AO_SPI3_CG>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi4: spi4@11018000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x11018000 0 0x1000>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MAINPLL_D5_D2>,
<&topckgen TOP_MUX_SPI>,
<&infracfg_ao INFRACFG_AO_SPI4_CG>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi5: spi5@11019000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <1>;
reg = <0 0x11019000 0 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MAINPLL_D5_D2>,
<&topckgen TOP_MUX_SPI>,
<&infracfg_ao INFRACFG_AO_SPI5_CG>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi6: spi6@1101d000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x1101d000 0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MAINPLL_D5_D2>,
<&topckgen TOP_MUX_SPI>,
<&infracfg_ao INFRACFG_AO_SPI6_CG>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
spi7: spi7@1101e000 {
compatible = "mediatek,mt6765-spi";
mediatek,pad-select = <0>;
reg = <0 0x1101e000 0 0x1000>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MAINPLL_D5_D2>,
<&topckgen TOP_MUX_SPI>,
<&infracfg_ao INFRACFG_AO_SPI7_CG>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
};
therm_ctrl@1100b000 {
compatible = "mediatek,therm_ctrl";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_THERM_CG>;
clock-names = "therm-main";
};
tboard_thermistor1: thermal-sensor1 {
compatible = "mediatek,mtboard-thermistor1";
io-channels = <&auxadc 0>;
io-channel-names = "thermistor-ch0";
};
tboard_thermistor2: thermal-sensor2 {
compatible = "mediatek,mtboard-thermistor2";
io-channels = <&auxadc 1>;
io-channel-names = "thermistor-ch1";
};
drcc: drcc {
compatible = "mediatek,drcc";
state = <255>;
drcc0_Vref = <255>;
drcc1_Vref = <255>;
drcc2_Vref = <255>;
drcc3_Vref = <255>;
drcc4_Vref = <255>;
drcc5_Vref = <255>;
drcc6_Vref = <255>;
drcc7_Vref = <255>;
drcc0_Hwgatepct = <255>;
drcc1_Hwgatepct = <255>;
drcc2_Hwgatepct = <255>;
drcc3_Hwgatepct = <255>;
drcc4_Hwgatepct = <255>;
drcc5_Hwgatepct = <255>;
drcc6_Hwgatepct = <255>;
drcc7_Hwgatepct = <255>;
drcc0_Code = <255>;
drcc1_Code = <255>;
drcc2_Code = <255>;
drcc3_Code = <255>;
drcc4_Code = <255>;
drcc5_Code = <255>;
drcc6_Code = <255>;
drcc7_Code = <255>;
};
eem_fsm: eem_fsm@1100b000 {
compatible = "mediatek,eem_fsm";
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_LOW>;
eem-status = <1>;
eem-initmon-little = <0xf>;
eem-initmon-big = <0xf>;
eem-initmon-cci = <0xf>;
eem-initmon-gpu = <0xf>;
eem-clamp-little = <0>;
eem-clamp-big = <0>;
eem-clamp-cci = <0>;
eem-clamp-gpu = <0>;
eem-offset-little = <0xff>;
eem-offset-big = <0xff>;
eem-offset-cci = <0xff>;
eem-offset-gpu = <0xff>;
};
btif@1100c000 {
compatible = "mediatek,btif";
/*btif base*/
reg = <0 0x1100c000 0 0x1000>,
/*btif tx dma base*/
<0 0x11000b80 0 0x80>,
/*btif rx dma base*/
<0 0x11000c00 0 0x80>;
/*btif irq, IRQS_Sync ID, btif_irq_b*/
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>,
/*btif tx dma irq*/
<GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>,
/*btif rx dma irq*/
<GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_BTIF_CG>,
/*btif clock*/
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
/*ap dma clock*/
clock-names = "btifc","apdmac";
};
consys: consys@18002000 {
compatible = "mediatek,mt6785-consys";
#address-cells = <2>;
#size-cells = <2>;
/*CONN_MCU_CONFIG_BASE */
reg = <0 0x18002000 0 0x1000>,
/*TOP_RGU_BASE */
<0 0x10007000 0 0x0100>,
/*INFRACFG_AO_BASE */
<0 0x10001000 0 0x1000>,
/*SPM_BASE */
<0 0x10006000 0 0x1000>,
/*CONN_HIF_ON_BASE */
<0 0x18007000 0 0x1000>,
/*CONN_TOP_MISC_OFF_BASE */
<0 0x180b1000 0 0x1000>,
/*CONN_MCU_CFG_ON_BASE */
<0 0x180a3000 0 0x1000>,
/*CONN_MCU_CIRQ_BASE */
<0 0x180a5000 0 0x800>,
/*CONN_TOP_MISC_ON_BASE */
<0 0x180c1000 0 0x1000>,
/*CONN_HIF_PDMA_BASE */
<0 0x18004000 0 0x1000>,
/* INFRASYS_COMMON AP2MD_PCCIF4_BASE */
<0 0x1024c000 0 0x40>,
/*INFRA_AO_PERICFG_BASE */
<0 0x10003000 0 0x1000>;
/*BGF_EINT */
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_LOW>,
/*WDT_EINT */
<GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>,
/*conn2ap_sw_irq*/
<GIC_SPI 323 IRQ_TYPE_EDGE_RISING>;
clocks = <&scpsys SCP_SYS_CONN>,
<&infracfg_ao INFRACFG_AO_CCIF4_AP_CG>;
clock-names = "conn", "ccif";
memory-region = <&consys_mem>;
};
irtx@1100d000 {
compatible = "mediatek,irtx";
reg = <0 0x1100d000 0 0x1000>;
};
disp_pwm0@1100e000 {
compatible = "mediatek,disp_pwm0";
reg = <0 0x1100e000 0 0x1000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>;
};
i2c1_imm@11014000 {
compatible = "mediatek,i2c1_imm";
reg = <0 0x11014000 0 0x1000>;
};
imp_iic_wrap@11017000 {
compatible = "mediatek,imp_iic_wrap";
reg = <0 0x11017000 0 0x1000>;
};
dfd@10200b00 {
compatible = "mediatek,dfd";
reg = <0 0x10200b00 0 0x10000>;
mediatek,enabled = <1>;
mediatek,chain_length = <0xa7f8>;
mediatek,rg_dfd_timeout = <0xa0>;
mediatek,check_dfd_support = <1>;
mediatek,dfd_infra_base = <0x390>;
mediatek,dfd_ap_addr_offset = <24>;
mediatek,dfd_latch_offset = <0x48>;
};
dfd_cache: dfd_cache {
compatible = "mediatek,dfd_cache";
mediatek,enabled = <0>;
mediatek,l2c_trigger = <0>;
mediatek,rg_dfd_timeout = <0x3e80>;
};
ssusb: usb0@11201000 {
compatible = "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>,
<0 0x11203E00 0 0x100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "ssusb_mac";
phy-cells = <1>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>;
clocks = <&infracfg_ao INFRACFG_AO_USB_CG>,
<&infracfg_ao INFRACFG_AO_SSUSB_XHCI_CG>;
clock-names = "sys_ck", "ref_clk";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dr_mode = "otg";
mediatek,force-vbus = <1>;
mediatek,clk-mgr = <1>;
mediatek,spm-mgr = <1>;
maximum-speed = "high-speed";
usb-role-switch;
status = "okay";
cdp-block;
usb_host: xhci0@11200000 {
compatible = "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg_ao INFRACFG_AO_SSUSB_XHCI_CG>;
clock-names = "sys_ck";
status = "okay";
};
};
u3phy: usb-phy0@11e40000 {
compatible = "mediatek,generic-tphy-v2";
clocks = <&clk26m>;
clock-names = "u3phya_ref";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "okay";
u2port0: usb2-phy0@11e40000 {
reg = <0 0x11e40000 0 0x700>;
#phy-cells = <1>;
mediatek,eye-vrt = <6>; /* 0~7 */
mediatek,eye-term = <6>; /* 0~7 */
mediatek,eye-rev6 = <1>; /* 0~3 */
mediatek,eye-disc = <7>; /* 0~8 */
mediatek,host-eye-vrt = <6>; /* 0~7 */
mediatek,host-eye-term = <6>; /* 0~7 */
mediatek,host-eye-rev6 = <1>; /* 0~3 */
mediatek,host-eye-disc = <7>; /* 0~8 */
status = "okay";
};
u3port0: usb3-phy0@11e40700 {
reg = <0 0x11e40700 0 0x900>;
#phy-cells = <1>;
status = "okay";
};
};
extcon_usb: extcon_usb {
compatible = "mediatek,extcon-usb";
charger = <&mt6360_chg>;
dev-conn = <&ssusb>;
mediatek,bypss-typec-sink = <1>;
};
usb_boost_manager {
compatible = "mediatek,usb_boost";
boost_period = <0>;
};
audio: audio@11210000 {
compatible = "mediatek,audio", "syscon";
reg = <0 0x11210000 0 0x1000>;
#clock-cells = <1>;
};
afe: mt6785-afe-pcm@11210000 {
compatible = "mediatek,mt6785-sound";
reg = <0 0x11210000 0 0x1000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
clocks = <&audio AUDIO_AFE>,
<&audio AUDIO_DAC>,
<&audio AUDIO_DAC_PREDIS>,
<&audio AUDIO_ADC>,
<&audio AUDIO_PDN_ADDA6_ADC>,
<&audio AUDIO_22M>,
<&audio AUDIO_24M>,
<&audio AUDIO_APLL_TUNER>,
<&audio AUDIO_APLL2_TUNER>,
<&audio AUDIO_TDM>,
<&audio AUDIO_TML>,
<&audio AUDIO_NLE>,
<&audio AUDIO_DAC_HIRES>,
<&audio AUDIO_ADC_HIRES>,
<&audio AUDIO_ADC_HIRES_TML>,
<&audio AUDIO_ADDA6_ADC_HIRES>,
<&audio AUDIO_3RD_DAC>,
<&audio AUDIO_3RD_DAC_PREDIS>,
<&audio AUDIO_3RD_DAC_TML>,
<&audio AUDIO_3RD_DAC_HIRES>,
<&scpsys SCP_SYS_AUDIO>,
<&infracfg_ao INFRACFG_AO_AUDIO_CG>,
<&infracfg_ao INFRACFG_AO_AUDIO_26M_BCLK_CK>,
<&topckgen TOP_MUX_AUDIO>,
<&topckgen TOP_MUX_AUD_INTBUS>,
<&topckgen TOP_MAINPLL_D2_D4>,
<&topckgen TOP_MUX_AUD_1>,
<&topckgen TOP_APLL1_CK>,
<&topckgen TOP_MUX_AUD_2>,
<&topckgen TOP_APLL2_CK>,
<&topckgen TOP_MUX_AUD_ENG1>,
<&topckgen TOP_APLL1_D8>,
<&topckgen TOP_MUX_AUD_ENG2>,
<&topckgen TOP_APLL2_D8>,
<&topckgen TOP_I2S0_M_SEL>,
<&topckgen TOP_I2S1_M_SEL>,
<&topckgen TOP_I2S2_M_SEL>,
<&topckgen TOP_I2S3_M_SEL>,
<&topckgen TOP_I2S4_M_SEL>,
<&topckgen TOP_I2S5_M_SEL>,
<&topckgen TOP_APLL12_DIV0>,
<&topckgen TOP_APLL12_DIV1>,
<&topckgen TOP_APLL12_DIV2>,
<&topckgen TOP_APLL12_DIV3>,
<&topckgen TOP_APLL12_DIV4>,
<&topckgen TOP_APLL12_DIVB>,
<&topckgen TOP_APLL12_DIV5>,
<&topckgen TOP_MUX_AUDIO_H>,
<&clk26m>;
clock-names = "aud_afe_clk",
"aud_dac_clk",
"aud_dac_predis_clk",
"aud_adc_clk",
"aud_adda6_adc_clk",
"aud_apll22m_clk",
"aud_apll24m_clk",
"aud_apll1_tuner_clk",
"aud_apll2_tuner_clk",
"aud_tdm_clk",
"aud_tml_clk",
"aud_nle",
"aud_dac_hires_clk",
"aud_adc_hires_clk",
"aud_adc_hires_tml",
"aud_adda6_adc_hires_clk",
"aud_3rd_dac_clk",
"aud_3rd_dac_predis_clk",
"aud_3rd_dac_tml",
"aud_3rd_dac_hires_clk",
"scp_sys_audio",
"aud_infra_clk",
"mtkaif_26m_clk",
"top_mux_audio",
"top_mux_audio_int",
"top_mainpll_d2_d4",
"top_mux_aud_1",
"top_apll1_ck",
"top_mux_aud_2",
"top_apll2_ck",
"top_mux_aud_eng1",
"top_apll1_d8",
"top_mux_aud_eng2",
"top_apll2_d8",
"top_i2s0_m_sel",
"top_i2s1_m_sel",
"top_i2s2_m_sel",
"top_i2s3_m_sel",
"top_i2s4_m_sel",
"top_i2s5_m_sel",
"top_apll12_div0",
"top_apll12_div1",
"top_apll12_div2",
"top_apll12_div3",
"top_apll12_div4",
"top_apll12_divb",
"top_apll12_div5",
"top_mux_audio_h",
"top_clk26m_clk";
pinctrl-names = "aud_clk_mosi_off",
"aud_clk_mosi_on",
"aud_dat_mosi_off",
"aud_dat_mosi_on",
"aud_dat_miso_off",
"aud_dat_miso_on",
"vow_dat_miso_off",
"vow_dat_miso_on",
"vow_clk_miso_off",
"vow_clk_miso_on",
"aud_nle_mosi_off",
"aud_nle_mosi_on",
"aud_dat_miso2_off",
"aud_dat_miso2_on",
"aud_gpio_i2s0_off",
"aud_gpio_i2s0_on",
"aud_gpio_i2s1_off",
"aud_gpio_i2s1_on",
"aud_gpio_i2s2_off",
"aud_gpio_i2s2_on",
"aud_gpio_i2s3_off",
"aud_gpio_i2s3_on",
"aud_gpio_i2s5_off",
"aud_gpio_i2s5_on",
"aud_dat_mosi_ch34_off",
"aud_dat_mosi_ch34_on",
"aud_dat_miso_ch34_off",
"aud_dat_miso_ch34_on";
pinctrl-0 = <&aud_clk_mosi_off>;
pinctrl-1 = <&aud_clk_mosi_on>;
pinctrl-2 = <&aud_dat_mosi_off>;
pinctrl-3 = <&aud_dat_mosi_on>;
pinctrl-4 = <&aud_dat_miso_off>;
pinctrl-5 = <&aud_dat_miso_on>;
pinctrl-6 = <&vow_dat_miso_off>;
pinctrl-7 = <&vow_dat_miso_on>;
pinctrl-8 = <&vow_clk_miso_off>;
pinctrl-9 = <&vow_clk_miso_on>;
pinctrl-10 = <&aud_nle_mosi_off>;
pinctrl-11 = <&aud_nle_mosi_on>;
pinctrl-12 = <&aud_dat_miso2_off>;
pinctrl-13 = <&aud_dat_miso2_on>;
pinctrl-14 = <&aud_gpio_i2s0_off>;
pinctrl-15 = <&aud_gpio_i2s0_on>;
pinctrl-16 = <&aud_gpio_i2s1_off>;
pinctrl-17 = <&aud_gpio_i2s1_on>;
pinctrl-18 = <&aud_gpio_i2s2_off>;
pinctrl-19 = <&aud_gpio_i2s2_on>;
pinctrl-20 = <&aud_gpio_i2s3_off>;
pinctrl-21 = <&aud_gpio_i2s3_on>;
pinctrl-22 = <&aud_gpio_i2s5_off>;
pinctrl-23 = <&aud_gpio_i2s5_on>;
pinctrl-24 = <&aud_dat_mosi_ch34_off>;
pinctrl-25 = <&aud_dat_mosi_ch34_on>;
pinctrl-26 = <&aud_dat_miso_ch34_off>;
pinctrl-27 = <&aud_dat_miso_ch34_on>;
};
mt6359_snd: mt6359_snd {
compatible = "mediatek,mt6359-sound";
mediatek,pwrap-regmap = <&pwrap>;
nvmem = <&pmic_efuse>;
nvmem-names = "pmic-hp-efuse";
io-channels =
<&pmic_auxadc AUXADC_HPOFS_CAL>,
<&pmic_auxadc AUXADC_ACCDET>;
io-channel-names =
"pmic_hpofs_cal",
"pmic_accdet";
};
sound: sound {
compatible = "mediatek,mt6785-mt6359-sound";
mediatek,audio-codec = <&mt6359_snd>;
mediatek,platform = <&afe>;
mediatek,snd_audio_dsp = <&snd_audio_dsp>;
mtk_spk_i2s_out = <3>;
mtk_spk_i2s_in = <0>;
/* mtk_spk_i2s_mck = <3>; */
mediatek,speaker-codec {
sound-dai = <&speaker_amp>;
};
};
snd_scp_ultra: snd_scp_ultra {
compatible = "mediatek,snd_scp_ultra";
scp_ultra_dl_memif_id = <0x7>;
scp_ultra_ul_memif_id = <0xe>;
};
/* feature : $enable $dl_mem $ul_mem $ref_mem $size */
snd_audio_dsp: snd_audio_dsp {
compatible = "mediatek,snd_audio_dsp";
mtk_dsp_voip = <0x1 0x1 0xffffffff 0xffffffff 0x30000>;
mtk_dsp_primary = <0x0 0x0 0xffffffff 0xffffffff 0x30000>;
mtk_dsp_offload = <0x0 0x6 0xffffffff 0xffffffff 0x400000>;
mtk_dsp_deep = <0x0 0x3 0xffffffff 0xffffffff 0x30000>;
mtk_dsp_playback = <0x1 0x4 0xf 0x13 0x30000>;
mtk_dsp_music = <0x0 0xffffffff 0xffffffff 0xffffffff 0x0>;
mtk_dsp_capture1 = <0x1 0xffffffff 0xc 0x12 0x20000>;
mtk_dsp_a2dp = <0x0 0xffffffff 0xffffffff 0xffffffff 0x40000>;
mtk_dsp_dataprovider = <0x0 0xffffffff 0xf 0xffffffff 0x30000>;
mtk_dsp_call_final = <0x5 0x4 0xf 0x13 0x18000>;
mtk_dsp_fast = <0x0 0xffffffff 0xffffffff 0xffffffff 0x5000>;
mtk_dsp_ktv = <0x1 0x8 0x11 0xffffffff 0x10000>;
mtk_dsp_capture_raw = <0x1 0xffffffff 0xffffffff 0xffffffff 0x20000>;
mtk_dsp_ver = <0x0>;
swdsp_smartpa_process_enable = <0x5>;
mtk_dsp_mem_afe = <0x1 0x40000>; /* always enable */
};
audio_sram@11211000 {
compatible = "mediatek,audio_sram";
reg = <0 0x11211000 0 0x18000>;
prefer_mode = <1>;
mode_size = <0x12000 0x18000>;
block_size = <0x1000>;
};
mtk-btcvsd-snd@18050000 {
compatible = "mediatek,mtk-btcvsd-snd";
reg=<0 0x18050000 0 0x1000>, /*PKV_PHYSICAL_BASE*/
<0 0x18080000 0 0x10000>; /*SRAM_BANK2*/
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_LOW>;
mediatek,infracfg = <&infracfg_ao>;
/*INFRA MISC, conn_bt_cvsd_mask*/
/*cvsd_mcu_read, write, packet_indicator*/
mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>;
disable_write_silence = <0>;
};
mt_soc_playback_offload {
compatible = "mediatek,mt_soc_offload_common";
};
/*
msdc0: msdc@11230000 {
compatible = "mediatek,msdc";
reg = <0 0x11230000 0 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
};
*/
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
status = "disabled";
};
/*
msdc1: msdc@11240000{
compatible = "mediatek,msdc";
reg = <0 0x11240000 0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
};
*/
msdc1_top@11e10000 {
compatible = "mediatek,msdc1_top";
reg = <0 0x11e10000 0 0x1000>;
};
msdc0_top@11f50000 {
compatible = "mediatek,msdc0_top";
reg = <0 0x11f50000 0 0x1000>;
};
mmc0: mmc0@11230000 {
compatible = "mediatek,mt6785-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11f50000 0 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MUX_MSDC50_0>,
<&infracfg_ao INFRACFG_AO_MSDC0_CG>,
<&infracfg_ao INFRACFG_AO_MSDC0_SCK_CG>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
mmc1: mmc0@11240000 {
compatible = "mediatek,mt6785-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11e10000 0 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MUX_MSDC30_1>,
<&infracfg_ao INFRACFG_AO_MSDC1_CG>,
<&infracfg_ao INFRACFG_AO_MSDC1_SCK_CG>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
ufshci:ufshci@11270000 {
compatible = "mediatek,mt8183-ufshci";
reg = <0 0x11270000 0 0x2300>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
phys = <&ufsphy>;
clocks =
<&infracfg_ao INFRACFG_AO_UFS_CG>,
<&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
<&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>,
<&infracfg_ao INFRACFG_AO_AES_UFSFDE_CG>;
clock-names =
"ufs0-clock",
"ufs0-unipro-clk",
"ufs0-mp-clk",
"ufs0-aes-clk";
freq-table-hz =
<0 0>,
<0 0>,
<0 0>,
<0 0>;
vcc-supply = <&mt_pmic_vemc_ldo_reg>;
resets = <&infracfg_rst 0>, <&infracfg_rst 1>,
<&infracfg_rst 2>;
reset-names = "hci_rst", "unipro_rst", "crypto_rst";
/* Reference clock control mode */
/* SW mode: 0, Half-HW mode: 1, HW mode: 2 */
mediatek,refclk_ctrl = <1>;
};
ufsphy: phy@11fa0000 {
compatible = "mediatek,mt8183-ufsphy";
reg = <0 0x11fa0000 0 0xc000>;
#phy-cells = <0>;
};
ca9peri@10e00000 {
compatible = "mediatek,ca9peri";
reg = <0 0x10e00000 0 0x1000>;
};
l2c@10f00000 {
compatible = "mediatek,l2c";
reg = <0 0x10f00000 0 0x1000>;
};
efusec@11c10000 {
compatible = "mediatek,efusec";
reg = <0 0x11c10000 0 0x1000>;
};
mfgcfg: mfgcfg@13fbf000 {
compatible = "mediatek,mfgcfg", "syscon";
reg = <0 0x13fbf000 0 0x1000>;
#clock-cells = <1>;
};
mali@13040000 {
compatible =
"mediatek,mali", "arm,mali-valhall";
reg = <0 0x13040000 0 0x10000>;
interrupts =
<GIC_SPI 309 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_LOW>;
interrupt-names =
"GPU",
"MMU",
"JOB",
"EVENT",
"PWR";
ged-supply = <&ged>;
};
gpufreq: gpufreq {
compatible = "mediatek,mt6785-gpufreq";
clocks =
<&topckgen TOP_MUX_MFG>,
<&topckgen TOP_MFGPLL_CK>, /* mfgpll_ck(270MHz) */
<&topckgen TOP_MAINPLL_D5>, /* mainpll_d5(218.4MHz) */
<&mfgcfg MFGCFG_BG3D>,
<&scpsys SCP_SYS_MFG0>, /* MFG_ASYNC */
<&scpsys SCP_SYS_MFG1>, /* MFG_TOP */
<&scpsys SCP_SYS_MFG2>, /* SHADER_0 */
<&scpsys SCP_SYS_MFG3>, /* SHADER_1 */
<&scpsys SCP_SYS_MFG4>, /* SHADER_2 */
<&scpsys SCP_SYS_MFG5>; /* SHADER_3 */
clock-names =
"clk_mux",
"clk_main_parent",
"clk_sub_parent",
"subsys_mfg_cg",
"mtcmos_mfg_async",
"mtcmos_mfg",
"mtcmos_mfg_core0",
"mtcmos_mfg_core1",
"mtcmos_mfg_core2",
"mtcmos_mfg_core3";
nvmem-cells = <&efuse_segment>;
nvmem-cell-names = "efuse_segment_cell";
};
ged: ged {
compatible = "mediatek,ged";
gpufreq-supply = <&gpufreq>;
};
mali_tb@13fbd000 {
compatible = "mediatek,mali_tb";
reg = <0 0x13fbd000 0 0x1000>;
};
mfg_dfp_60@13020000 {
compatible = "mediatek,mfg_dfp_60";
reg = <0 0x13020000 0 0x1000>;
};
mfg_tb@13fbff00 {
compatible = "mediatek,mfg_tb";
reg = <0 0x13fbff00 0 0x1000>;
};
mmsys_config: mmsys_config@14000000 {
compatible = "mediatek,mmsys_config", "syscon";
reg = <0 0x14000000 0 0x1000>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clocks = <&mmsys_config MMSYS_MDP_DL_TXCK>,
<&mmsys_config MMSYS_MDP_DL_RX_CK>,
<&mmsys_config MMSYS_IPU_DL_TXCK>,
<&mmsys_config MMSYS_IPU_DL_RX_CK>;
clock-names = "CAM_MDP_TX",
"CAM_MDP_RX",
"CAM_MDP2_TX",
"CAM_MDP2_RX";
};
mdp_rdma0: mdp_rdma0@14001000 {
compatible = "mediatek,mdp_rdma0";
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys_config MMSYS_MDP_RDMA0>;
clock-names = "MDP_RDMA0";
};
mdp_rdma1: mdp_rdma1@14002000 {
compatible = "mediatek,mdp_rdma1";
reg = <0 0x14002000 0 0x1000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys_config MMSYS_MDP_RDMA1>;
clock-names = "MDP_RDMA1";
};
mdp_rsz0: mdp_rsz0@14003000 {
compatible = "mediatek,mdp_rsz0";
reg = <0 0x14003000 0 0x1000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys_config MMSYS_MDP_RSZ0>;
clock-names = "MDP_RSZ0";
};
mdp_rsz1: mdp_rsz1@14004000 {
compatible = "mediatek,mdp_rsz1";
reg = <0 0x14004000 0 0x1000>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys_config MMSYS_MDP_RSZ1>;
clock-names = "MDP_RSZ1";
};
mdp_wrot0: mdp_wrot0@14005000 {
compatible = "mediatek,mdp_wrot0";
reg = <0 0x14005000 0 0x1000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys_config MMSYS_MDP_WROT0>;
clock-names = "MDP_WROT0";
};
mdp_wdma0@14006000 {
compatible = "mediatek,mdp_wdma0";
reg = <0 0x14006000 0 0x1000>;
};
mdp_tdshp: mdp_tdshp0@14007000 {
compatible = "mediatek,mdp_tdshp0";
reg = <0 0x14007000 0 0x1000>;
clocks = <&mmsys_config MMSYS_MDP_TDSHP>;
clock-names = "MDP_TDSHP";
};
smi_common@14019000 {
compatible = "mediatek,smi_common";
reg = <0 0x14019000 0 0x1000>;
clocks = <&scpsys SCP_SYS_DIS>,
<&mmsys_config MMSYS_SMI_COMMON>;
clock-names = "scp-dis", "mm-common";
mediatek,smi-id = <8>;
mmsys_config = <&mmsys_config>;
};
smi_larb0: smi_larb0@14017000 {
compatible = "mediatek,smi_larb0", "mediatek,smi_larb";
reg = <0 0x14017000 0 0x1000>;
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_LOW>;
clocks = <&scpsys SCP_SYS_DIS>, <&mmsys_config MMSYS_SMI_LARB0>;
clock-names = "scp-dis", "mm-larb0";
mediatek,smi-id = <0>;
};
smi_larb1: smi_larb1@14018000 {
compatible = "mediatek,smi_larb1", "mediatek,smi_larb";
reg = <0 0x14018000 0 0x1000>;
clocks = <&scpsys SCP_SYS_DIS>, <&mmsys_config MMSYS_SMI_LARB1>;
clock-names = "scp-dis", "mm-larb1";
mediatek,smi-id = <1>;
};
mmdvfs_pmqos {
compatible = "mediatek,mmdvfs_pmqos";
larb_groups = <0 1 2 3 5 6 7>;
larb0 = <7 7 7 7 7 7 7 8 7>;
larb1 = <7 7 7 7 7 7 7 7 7 8 7 8 7 7>;
larb2 = <7 7 8 7 7 7 7 7 7 7 8 7>;
larb3 = <7 8 8 8 7 7 7 7 7 7 8 8 7 8 8 7
7 7 7>;
larb5 = <7 8 8 7 7 7 8 7 7 8 7 8 7 7
7 8 7 7 6 7 8 7 8 7 8 8>;
larb6 = <8 8 8 8 7 7 8 7 8 8 8 7 8 8 8 7
8 8 7 8 7 7 8 8 8 7 7 7 7 7 7>;
larb7 = <8 8 8 7 7>;
cam_larb = <6 10>; /* include SMI common CCU */
max_ostd_larb = <0 1>;
max_ostd = <40>;
comm_freq = "disp_freq";
mm_step0 = <560 1 0 7>;
mm_step1 = <450 1 0 8>;
mm_step2 = <315 1 0 11>;
cam_step0 = <560 1 1 7>;
cam_step1 = <416 1 1 9>;
cam_step2 = <315 1 1 11>;
img_step0 = <560 1 2 7>;
img_step1 = <364 1 2 10>;
img_step2 = <315 1 2 11>;
venc_step0 = <630 1 3 5>;
venc_step1 = <450 1 3 8>;
venc_step2 = <364 1 3 10>;
vdec_step0 = <624 1 4 6>;
vdec_step1 = <416 1 4 9>;
vdec_step2 = <312 1 4 12>;
/* fmeter_mux_ids: Mapping to mux sequence in clocks */
fmeter_mux_ids = <2 8 5 50 51>;
vopp_steps = <0 1 2>;
disp_freq = "mm_step0", "mm_step1", "mm_step2";
mdp_freq = "mm_step0", "mm_step1", "mm_step2";
cam_freq = "cam_step0","cam_step1","cam_step2";
img_freq = "img_step0","img_step1","img_step2";
vdec_freq = "vdec_step0","vdec_step1","vdec_step2";
venc_freq = "venc_step0","venc_step1","venc_step2";
clocks = <&topckgen TOP_MUX_MM>, /* 0 */
<&topckgen TOP_MUX_CAM>, /* 1 */
<&topckgen TOP_MUX_IMG>, /* 2 */
<&topckgen TOP_MUX_VENC>, /* 3 */
<&topckgen TOP_MUX_VDEC>, /* 4 */
<&topckgen TOP_MMPLL_D5>, /* 5 */
<&topckgen TOP_UNIVPLL_D2>, /* 6 */
<&topckgen TOP_TVDPLL_MAINPLL_D2_CK>, /* 7 */
<&topckgen TOP_MMPLL_D7>, /* 8 */
<&topckgen TOP_UNIVPLL_D3>, /* 9 */
<&topckgen TOP_MAINPLL_D3>, /* 10 */
<&topckgen TOP_MMPLL_D5_D2>, /* 11 */
<&topckgen TOP_UNIVPLL_D2_D2>; /* 12 */
clock-names = "MMDVFS_CLK_MUX_MM", /* 0 */
"MMDVFS_CLK_MUX_CAM", /* 1 */
"MMDVFS_CLK_MUX_IMG", /* 2 */
"MMDVFS_CLK_MUX_VENC", /* 3 */
"MMDVFS_CLK_MUX_VDEC", /* 4 */
"MMDVFS_CLK_MMPLL_D5", /* 5 */
"MMDVFS_CLK_UNIVPLL_D2", /* 6 */
"MMDVFS_CLK_TVDPLL_MAINPLL_D2_CK", /* 7 */
"MMDVFS_CLK_MMPLL_D7", /* 8 */
"MMDVFS_CLK_UNIVPLL_D3", /* 9 */
"MMDVFS_CLK_MAINPLL_D3", /* 10 */
"MMDVFS_CLK_MMPLL_D5_D2", /* 11 */
"MMDVFS_CLK_UNIVPLL_D2_D2"; /* 12 */
};
disp_rsz0@1401a000 {
compatible = "mediatek,disp_rsz0";
reg = <0 0x1401a000 0 0x1000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_LOW>;
};
mdp_aal: mdp_aal0@1401b000 {
compatible = "mediatek,mdp_aal0";
reg = <0 0x1401b000 0 0x1000>;
clocks = <&mmsys_config MMSYS_MDP_AAL>;
clock-names = "MDP_AAL";
};
mdp_hdr: mdp_hdr0@1401c000 {
compatible = "mediatek,mdp_hdr0";
reg = <0 0x1401c000 0 0x1000>;
clocks = <&mmsys_config MMSYS_MDP_HDR>;
clock-names = "MDP_HDR";
};
dbi0@1401d000 {
compatible = "mediatek,dbi0";
reg = <0 0x1401d000 0 0x1000>;
};
i2c@1401e000 {
compatible = "mediatek,i2c";
reg = <0 0x1401e000 0 0x1000>;
};
dsi1@1401f000 {
compatible = "mediatek,dsi1";
reg = <0 0x1401f000 0 0x1000>;
};
mdp_wrot1: mdp_wrot1@14020000 {
compatible = "mediatek,mdp_wrot1";
reg = <0 0x14020000 0 0x1000>;
clocks = <&mmsys_config MMSYS_MDP_WROT1>;
clock-names = "MDP_WROT1";
};
disp_postmask0@14021000 {
compatible = "mediatek,disp_postmask0";
reg = <0 0x14021000 0 0x1000>;
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_LOW>;
};
disp_mutex1@14030000 {
compatible = "mediatek,disp_mutex1";
reg = <0 0x14030000 0 0x1000>;
};
mdp_tdshp1@14031000 {
compatible = "mediatek,mdp_tdshp1";
reg = <0 0x14031000 0 0x1000>;
};
mdp_aal1@14032000 {
compatible = "mediatek,mdp_aal1";
reg = <0 0x14032000 0 0x1000>;
};
mdp_hdr1@14033000 {
compatible = "mediatek,mdp_hdr1";
reg = <0 0x14033000 0 0x1000>;
};
disp_color1@14040000 {
compatible = "mediatek,disp_color1";
reg = <0 0x14040000 0 0x1000>;
};
disp_ccorr1@14041000 {
compatible = "mediatek,disp_ccorr1";
reg = <0 0x14041000 0 0x1000>;
};
disp_aal1@14042000 {
compatible = "mediatek,disp_aal1";
reg = <0 0x14042000 0 0x1000>;
};
disp_gamma1@14043000 {
compatible = "mediatek,disp_gamma1";
reg = <0 0x14043000 0 0x1000>;
};
disp_dither1@14044000 {
compatible = "mediatek,disp_dither1";
reg = <0 0x14044000 0 0x1000>;
};
disp_rsz1@14045000 {
compatible = "mediatek,disp_rsz1";
reg = <0 0x14045000 0 0x1000>;
};
dbi1@14046000 {
compatible = "mediatek,dbi1";
reg = <0 0x14046000 0 0x1000>;
};
dpi1@14047000 {
compatible = "mediatek,dpi1";
reg = <0 0x14047000 0 0x1000>;
};
disp_pvric0@14050000 {
compatible = "mediatek,disp_pvric0";
reg = <0 0x14050000 0 0x1000>;
};
mdp_pvric0@14051000 {
compatible = "mediatek,mdp_pvric0";
reg = <0 0x14051000 0 0x1000>;
};
mdp_pvric1@14052000 {
compatible = "mediatek,mdp_pvric1";
reg = <0 0x14052000 0 0x1000>;
};
vcu: vcu@16000000 {
compatible = "mediatek-vcu";
mediatek,vcuid = <0>;
mediatek,vcuname = "vcu";
reg = <0 0x16000000 0 0x40000>, /* VDEC_BASE */
<0 0x17020000 0 0x10000>, /* VENC_BASE */
<0 0x19002000 0 0x1000>; /* VENC_LT */
#ifdef CONFIG_MTK_IOMMU_V2
iommus = <&iommu0 M4U_PORT_HW_VDEC_MC_EXT>;
#endif
mediatek,mailbox-gce = <&gce_mbox>;
mboxes = <&gce_mbox 16 0 CMDQ_THR_PRIO_1>,
<&gce_mbox 17 0 CMDQ_THR_PRIO_1>;
gce-event-names = "vdec_pic_start",
"vdec_decode_done",
"vdec_pause",
"vdec_dec_error",
"vdec_mc_busy_overflow_timeout",
"vdec_all_dram_req_done",
"vdec_ini_fetch_rdy",
"vdec_process_flag",
"vdec_search_start_code_done",
"vdec_ref_reorder_done",
"vdec_wp_tble_done",
"vdec_count_sram_clr_done",
"venc_eof",
"venc_cmdq_pause_done",
"venc_mb_done",
"venc_128B_cnt_done";
gce-events = <&gce_mbox CMDQ_EVENT_VDEC_EVENT_0>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_1>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_2>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_3>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_4>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_5>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_6>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_7>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_8>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_9>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_10>,
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_11>,
<&gce_mbox CMDQ_EVENT_VENC_EOF>,
<&gce_mbox CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE>,
<&gce_mbox CMDQ_EVENT_VENC_MB_DONE>,
<&gce_mbox CMDQ_EVENT_VENC_128BYTE_CNT_DONE>;
};
vcodec_dec: vcodec_dec@16000000 {
compatible = "mediatek,mt6785-vcodec-dec";
reg = <0 0x16000000 0 0x1000>, /* VDEC_SYS */
<0 0x16020000 0 0x400>, /* VDEC_VLD */
<0 0x16021000 0 0x1000>, /* VDEC_MC */
<0 0x16023000 0 0x1000>, /* VDEC_MV */
<0 0x16025000 0 0x1000>; /* VDEC_MISC */
#ifdef CONFIG_MTK_IOMMU_V2
iommus = <&iommu0 M4U_PORT_HW_VDEC_MC_EXT>;
#endif
mediatek,larb = <&smi_larb1>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_LOW>;
mediatek,vcu = <&vcu>;
clocks =
<&scpsys SCP_SYS_DIS>,
<&scpsys SCP_SYS_VDE>,
<&scpsys SCP_SYS_VEN>,
<&mmsys_config MMSYS_SMI_COMMON>,
<&mmsys_config MMSYS_GALS_COMM0>,
<&mmsys_config MMSYS_GALS_COMM1>,
<&vdec_gcon VDEC_VDEC>,
<&venc_gcon VENC_GCON_VENC>;
clock-names =
"MT_SCP_SYS_DIS",
"MT_SCP_SYS_VDE",
"MT_SCP_SYS_VEN",
"MT_CG_SMI_COMMON",
"MT_CG_GALS_COMM0",
"MT_CG_GALS_COMM1",
"MT_CG_VDEC",
"MT_CG_VENC";
#clock-cells = <1>;
};
vdec_gcon: vdec_gcon@16000000 {
compatible = "mediatek,vdec_gcon", "syscon";
reg = <0 0x16000000 0 0x1000>, /* VDEC_SYS */
<0 0x16020000 0 0x400>, /* VDEC_VLD */
<0 0x16025000 0 0x1000>; /* VDEC_MISC */
#clock-cells = <1>;
};
vdec_mbist@16001000 {
compatible = "mediatek,vdec_mbist";
reg = <0 0x16001000 0 0x1000>;
};
vdec@16020000 {
compatible = "mediatek,vdec";
reg = <0 0x16020000 0 0x1000>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_LOW>;
};
vld@16020000 {
compatible = "mediatek,vld";
reg = <0 0x16020000 0 0x1000>;
};
vld_top@16020800 {
compatible = "mediatek,vld_top";
reg = <0 0x16020800 0 0x1000>;
};
mc@16021000 {
compatible = "mediatek,mc";
reg = <0 0x16021000 0 0x1000>;
};
avc_vld@16022000 {
compatible = "mediatek,avc_vld";
reg = <0 0x16022000 0 0x1000>;
};
avc_mv@16023000 {
compatible = "mediatek,avc_mv";
reg = <0 0x16023000 0 0x1000>;
};
vdec_pp@16024000 {
compatible = "mediatek,vdec_pp";
reg = <0 0x16024000 0 0x1000>;
};
vdtop@16025000 {
compatible = "mediatek,vdtop";
reg = <0 0x16025000 0 0x1000>;
};
vp6@16026000 {
compatible = "mediatek,vp6";
reg = <0 0x16026000 0 0x1000>;
};
vld2@16026800 {
compatible = "mediatek,vld2";
reg = <0 0x16026800 0 0x1000>;
};
avs_vld@16027000 {
compatible = "mediatek,avs_vld";
reg = <0 0x16027000 0 0x1000>;
};
vp8_vld@16027800 {
compatible = "mediatek,vp8_vld";
reg = <0 0x16027800 0 0x1000>;
};
hevc_vld@16028000 {
compatible = "mediatek,hevc_vld";
reg = <0 0x16028000 0 0x1000>;
};
vp9_vld@16028400 {
compatible = "mediatek,vp9_vld";
reg = <0 0x16028400 0 0x1000>;
};
vdec_core0_vad@1602c000 {
compatible = "mediatek,vdec_core0_vad";
reg = <0 0x1602c000 0 0x1000>;
};
smi_larb2: smi_larb2@16010000 {
compatible = "mediatek,smi_larb2", "mediatek,smi_larb";
reg = <0 0x16010000 0 0x1000>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_LOW>;
clocks = <&scpsys SCP_SYS_VDE>, <&vdec_gcon VDEC_VDEC>;
clock-names = "scp-vde", "vdec-vdec";
mediatek,smi-id = <2>;
};
vcodec_enc: vcodec_enc@17000000 {
compatible = "mediatek,mt6785-vcodec-enc", "syscon";
reg = <0 0x17000000 0 0x1000>,
<0 0x17020000 0 0x1000>;
#ifdef CONFIG_MTK_IOMMU_V2
iommus = <&iommu0 M4U_PORT_HW_VDEC_MC_EXT>;
#endif
mediatek,larb = <&smi_larb4>;
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_LOW>;
mediatek,vcu = <&vcu>;
clocks =
<&scpsys SCP_SYS_DIS>,
<&scpsys SCP_SYS_VDE>,
<&scpsys SCP_SYS_VEN>,
<&mmsys_config MMSYS_SMI_COMMON>,
<&mmsys_config MMSYS_GALS_COMM0>,
<&mmsys_config MMSYS_GALS_COMM1>,
<&vdec_gcon VDEC_VDEC>,
<&venc_gcon VENC_GCON_VENC>;
clock-names =
"MT_SCP_SYS_DIS",
"MT_SCP_SYS_VDE",
"MT_SCP_SYS_VEN",
"MT_CG_SMI_COMMON",
"MT_CG_GALS_COMM0",
"MT_CG_GALS_COMM1",
"MT_CG_VDEC",
"MT_CG_VENC";
#clock-cells = <1>;
};
venc_gcon: venc_gcon@17000000 {
compatible = "mediatek,venc_gcon", "syscon";
reg = <0 0x17000000 0 0x1000>,
<0 0x17020000 0 0x1000>;
#clock-cells = <1>;
};
smi_larb3: smi_larb3@17010000 {
compatible = "mediatek,smi_larb3", "mediatek,smi_larb";
reg = <0 0x17010000 0 0x1000>;
interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_LOW>;
clocks = <&scpsys SCP_SYS_VEN>, <&venc_gcon VENC_GCON_VENC>,
<&venc_gcon VENC_GCON_JPGENC>;
clock-names = "scp-ven", "venc-venc", "venc-jpgenc";
mediatek,smi-id = <3>;
};
venc@17020000 {
compatible = "mediatek,venc";
reg = <0 0x17020000 0 0x2000>;
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_LOW>;
};
venc_jpg@17030000 {
compatible = "mediatek,venc_jpg";
reg = <0 0x17030000 0 0x10000>;
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_LOW>;
clocks =
<&venc_gcon VENC_GCON_JPGENC>;
clock-names =
"MT_CG_VENC_JPGENC";
cshot-spec = <368>;
};
mbist@17070000 {
compatible = "mediatek,mbist";
reg = <0 0x17070000 0 0x1000>;
};
mjc_config@12000000 {
compatible = "mediatek,mjc_config";
reg = <0 0x12000000 0 0x1000>;
};
mjc_top@12001000 {
compatible = "mediatek,mjc_top";
reg = <0 0x12001000 0 0x1000>;
};
imgsys1_dfp@1502e000 {
compatible = "mediatek,imgsys1_dfp";
reg = <0 0x1502e000 0 0x1000>;
};
imgsys: syscon@15020000 {
compatible = "mediatek,mt6785-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
imgsys_config: imgsys_config@15020000 {
compatible = "mediatek,imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
clocks =
<&imgsys IMG_LARB5>,
<&imgsys IMG_DIP>;
clock-names =
"DIP_CG_IMG_LARB5",
"DIP_CG_IMG_DIP";
};
imgsyscq@15020000 {
compatible = "mediatek,imgsyscq";
reg = <0 0x15020000 0 0x10>;
};
smi_larb4: smi_larb4@1502f000 {
compatible = "mediatek,smi_larb4", "mediatek,smi_larb";
reg = <0 0x1502f000 0 0x1000>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_LOW>;
clocks = <&scpsys SCP_SYS_ISP>, <&imgsys IMG_LARB4>;
clock-names = "scp-isp", "img-larb4";
mediatek,smi-id = <4>;
};
smi_larb5: smi_larb5@15021000 {
compatible = "mediatek,smi_larb5", "mediatek,smi_larb";
reg = <0 0x15021000 0 0x1000>;
interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_LOW>;
clocks = <&scpsys SCP_SYS_ISP>, <&imgsys IMG_LARB5>;
clock-names = "scp-isp", "img-larb5";
mediatek,smi-id = <5>;
};
dip1@15022000 {
compatible = "mediatek,dip1";
reg = <0 0x15022000 0 0x6000>;
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_LOW>;
};
dip2@15023000 {
compatible = "mediatek,dip2";
reg = <0 0x15023000 0 0x1000>;
};
dip3@15024000 {
compatible = "mediatek,dip3";
reg = <0 0x15024000 0 0x1000>;
};
dip4@15025000 {
compatible = "mediatek,dip4";
reg = <0 0x15025000 0 0x1000>;
};
dip5@15026000 {
compatible = "mediatek,dip5";
reg = <0 0x15026000 0 0x1000>;
};
dip6@15027000 {
compatible = "mediatek,dip6";
reg = <0 0x15027000 0 0x1000>;
};
dpe@15028000 {
compatible = "mediatek,dpe";
reg = <0 0x15028000 0 0x1000>;
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys IMG_DPE>;
clock-names = "DPE_CG_IMG_DPE";
};
dpe_dma@15028000 {
compatible = "mediatek,dpe_dma";
reg = <0 0x15028000 0 0x1000>;
};
rsc@15029000 {
compatible = "mediatek,rsc";
reg = <0 0x15029000 0 0x1000>;
interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys IMG_RSC>;
clock-names = "RSC_CLK_IMG_RSC";
};
wpe_a@1502a000 {
compatible = "mediatek,wpe_a";
reg = <0 0x1502a000 0 0x1000>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys IMG_WPE_A>;
clock-names = "WPE_CLK_IMG_WPE_A";
};
wpe_b@1502d000 {
compatible = "mediatek,wpe_b";
reg = <0 0x1502d000 0 0x1000>;
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys IMG_WPE_B>;
clock-names = "WPE_CLK_IMG_WPE_B";
};
fdvt@1502b000 {
compatible = "mediatek,fdvt";
reg = <0 0x1502b000 0 0x1000>;
interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys IMG_FDVT>;
clock-names = "FD_CLK_IMG_FDVT";
};
fdvt_dma@1502b000 {
compatible = "mediatek,fdvt_dma";
reg = <0 0x1502b000 0 0x1000>;
};
mfb@1502e000 {
compatible = "mediatek,mfb";
reg = <0 0x1502e000 0 0x1000>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys IMG_MFB>;
clock-names = "MFB_CLK_IMG_MFB";
};
owe@1502c000 {
compatible = "mediatek,owe";
reg = <0 0x1502c000 0 0x1000>;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys IMG_OWE>;
clock-names = "OWE_CLK_IMG_OWE";
};
owe_dma@1502c000 {
compatible = "mediatek,owe_dma";
reg = <0 0x1502c000 0 0x1000>;
};
eaf@1502d000 {
compatible = "mediatek,eaf";
reg = <0 0x1502d000 0 0x1000>;
};
eaf_dma@1502d000 {
compatible = "mediatek,eaf_dma";
reg = <0 0x1502d000 0 0x1000>;
};
imgsys1_vad@1502e000 {
compatible = "mediatek,imgsys1_vad";
reg = <0 0x1502e000 0 0x1000>;
};
smi_larb8: smi_larb8@15030000 {
compatible = "mediatek,smi_larb8";
reg = <0 0x15030000 0 0x1000>;
};
smi_larb9: smi_larb9@15031000 {
compatible = "mediatek,smi_larb9";
reg = <0 0x15031000 0 0x1000>;
};
smi_larb10: smi_larb10@15032000 {
compatible = "mediatek,smi_larb10";
reg = <0 0x15032000 0 0x1000>;
};
smi_larb11: smi_larb11@15033000 {
compatible = "mediatek,smi_larb11";
reg = <0 0x15033000 0 0x1000>;
};
wifi: wifi@18000000 {
compatible = "mediatek,wifi";
reg = <0 0x18000000 0 0x100000>;
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_LOW>;
memory-region = <&wifi_mem>;
};
ipu_conn@19000000 {
compatible = "mediatek,ipu_conn";
reg = <0 0x19000000 0 0x1000>;
};
ipu_vcore@19020000 {
compatible = "mediatek,ipu_vcore";
reg = <0 0x19020000 0 0x1000>;
};
apu_vcore: apu_vcore@19020000 {
compatible = "mediatek,apu_vcore", "syscon";
reg = <0 0x19020000 0 0x1000>;
#clock-cells = <1>;
};
apu_conn: apu_conn@19000000 {
compatible = "mediatek,apu_conn", "syscon";
reg = <0 0x19000000 0 0x1000>;
#clock-cells = <1>;
};
apu0: apu0@19180000 {
compatible = "mediatek,apu0", "syscon";
reg = <0 0x19180000 0 0x1000>;
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
};
apu1: apu1@19280000 {
compatible = "mediatek,apu1", "syscon";
reg = <0 0x19280000 0 0x1000>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
};
vpu_core0@0x19100000 {
compatible = "mediatek,vpu_core0";
reg = <0 0x19100000 0 0x94000>;
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen TOP_MUX_DSP>,
<&topckgen TOP_MUX_DSP1>,
<&topckgen TOP_MUX_DSP2>,
<&topckgen TOP_MUX_IPU_IF>,
<&apu0 APU0_JTAG_CG>,
<&apu0 APU0_AXI_M_CG>,
<&apu0 APU0_APU_CG>,
<&apu1 APU1_JTAG_CG>,
<&apu1 APU1_AXI_M_CG>,
<&apu1 APU1_APU_CG>,
<&apu_conn APU_CONN_APU_CG>,
<&apu_conn APU_CONN_AHB_CG>,
<&apu_conn APU_CONN_AXI_CG>,
<&apu_conn APU_CONN_ISP_CG>,
<&apu_conn APU_CONN_CAM_ADL_CG>,
<&apu_conn APU_CONN_IMG_ADL_CG>,
<&apu_conn APU_CONN_EMI_26M_CG>,
<&apu_conn APU_CONN_VPU_UDI_CG>,
<&apu_vcore APU_VCORE_AHB_CG>,
<&apu_vcore APU_VCORE_AXI_CG>,
<&apu_vcore APU_VCORE_ADL_CG>,
<&apu_vcore APU_VCORE_QOS_CG>,
<&clk26m>,
<&topckgen TOP_APUPLL_CK>,
<&topckgen TOP_UNIVPLL_D3_D8>,
<&topckgen TOP_UNIVPLL_D3_D4>,
<&topckgen TOP_MAINPLL_D2_D4>,
<&topckgen TOP_UNIVPLL_D3_D2>,
<&topckgen TOP_MAINPLL_D2_D2>,
<&topckgen TOP_UNIVPLL_D2_D2>,
<&topckgen TOP_MAINPLL_D3>,
<&topckgen TOP_UNIVPLL_D3>,
<&topckgen TOP_MMPLL_D7>,
<&topckgen TOP_MMPLL_D6>,
<&topckgen TOP_ADSPPLL_D5>,
<&topckgen TOP_TVDPLL_CK>,
<&topckgen TOP_UNIVPLL_D2>,
<&topckgen TOP_ADSPPLL_D4>,
<&topckgen TOP_MAINPLL_D2>,
<&topckgen TOP_MMPLL_D4>,
<&mmsys_config MMSYS_GALS_IPU2MM>,
<&mmsys_config MMSYS_GALS_IPU12MM>,
<&mmsys_config MMSYS_GALS_COMM1>,
<&mmsys_config MMSYS_GALS_COMM0>,
<&mmsys_config MMSYS_SMI_COMMON>,
<&mmsys_config MMSYS_IPU_DL_TXCK>,
<&mmsys_config MMSYS_IPU_DL_RX_CK>,
<&scpsys SCP_SYS_DIS>,
<&scpsys SCP_SYS_VPU_VCORE_DORMANT>,
<&scpsys SCP_SYS_VPU_VCORE_SHUTDOWN>,
<&scpsys SCP_SYS_VPU_CONN_DORMANT>,
<&scpsys SCP_SYS_VPU_CONN_SHUTDOWN>,
<&scpsys SCP_SYS_VPU_CORE0_DORMANT>,
<&scpsys SCP_SYS_VPU_CORE0_SHUTDOWN>,
<&scpsys SCP_SYS_VPU_CORE1_DORMANT>,
<&scpsys SCP_SYS_VPU_CORE1_SHUTDOWN>;
clock-names = "clk_top_dsp_sel",
"clk_top_dsp1_sel",
"clk_top_dsp2_sel",
"clk_top_ipu_if_sel",
"clk_apu_core0_jtag_cg",
"clk_apu_core0_axi_m_cg",
"clk_apu_core0_apu_cg",
"clk_apu_core1_jtag_cg",
"clk_apu_core1_axi_m_cg",
"clk_apu_core1_apu_cg",
"clk_apu_conn_apu_cg",
"clk_apu_conn_ahb_cg",
"clk_apu_conn_axi_cg",
"clk_apu_conn_isp_cg",
"clk_apu_conn_cam_adl_cg",
"clk_apu_conn_img_adl_cg",
"clk_apu_conn_emi_26m_cg",
"clk_apu_conn_vpu_udi_cg",
"clk_apu_vcore_ahb_cg",
"clk_apu_vcore_axi_cg",
"clk_apu_vcore_adl_cg",
"clk_apu_vcore_qos_cg",
"clk_top_clk26m",
"clk_top_apupll_ck",
"clk_top_univpll_d3_d8",
"clk_top_univpll_d3_d4",
"clk_top_mainpll_d2_d4",
"clk_top_univpll_d3_d2",
"clk_top_mainpll_d2_d2",
"clk_top_univpll_d2_d2",
"clk_top_mainpll_d3",
"clk_top_univpll_d3",
"clk_top_mmpll_d7",
"clk_top_mmpll_d6",
"clk_top_adsppll_d5",
"clk_top_tvdpll_ck",
"clk_top_univpll_d2",
"clk_top_adsppll_d4",
"clk_top_mainpll_d2",
"clk_top_mmpll_d4",
"clk_mmsys_gals_ipu2mm",
"clk_mmsys_gals_ipu12mm",
"clk_mmsys_gals_comm1",
"clk_mmsys_gals_comm0",
"clk_mmsys_smi_common",
"clk_mmsys_ipu_dl_txck",
"clk_mmsys_ipu_dl_rx_ck",
"mtcmos_dis",
"mtcmos_vpu_vcore_dormant",
"mtcmos_vpu_vcore_shutdown",
"mtcmos_vpu_conn_dormant",
"mtcmos_vpu_conn_shutdown",
"mtcmos_vpu_core0_dormant",
"mtcmos_vpu_core0_shutdown",
"mtcmos_vpu_core1_dormant",
"mtcmos_vpu_core1_shutdown";
};
vpu_core1@0x19200000 {
compatible = "mediatek,vpu_core1";
reg = <0 0x19200000 0 0x94000>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_LOW>;
};
apu_dvfs@19180000 {
compatible = "mediatek,apu_dvfs";
reg = <0 0x19180000 0 0x1000>;
};
camsys: camsys@1a000000 {
compatible = "mediatek,mt6785-camsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
camsys1: camsysisp@1a000000 {
compatible = "mediatek,camsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
/* Camera CCF */
clocks = <&scpsys SCP_SYS_DIS>,
<&scpsys SCP_SYS_ISP>,
<&scpsys SCP_SYS_CAM>,
<&camsys CAMSYS_CAM_CGPDN>,
<&camsys CAMSYS_CAMTG_CGPDN>,
<&camsys CAMSYS_CAMSV0_CGPDN>,
<&camsys CAMSYS_CAMSV1_CGPDN>;
clock-names = "ISP_SCP_SYS_DIS",
"ISP_SCP_SYS_ISP",
"ISP_SCP_SYS_CAM",
"CAMSYS_CAM_CGPDN",
"CAMSYS_CAMTG_CGPDN",
"CAMSYS_CAMSV0_CGPDN",
"CAMSYS_CAMSV1_CGPDN";
};
smi_larb6: smi_larb6@1a001000 {
compatible = "mediatek,smi_larb6", "mediatek,smi_larb";
reg = <0 0x1a001000 0 0x1000>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_LOW>;
clocks = <&scpsys SCP_SYS_CAM>, <&camsys CAMSYS_LARB6_CGPDN>;
clock-names = "scp-cam", "cam-larb6";
mediatek,smi-id = <6>;
};
smi_larb7: smi_larb7@1a002000 {
compatible = "mediatek,smi_larb7", "mediatek,smi_larb";
reg = <0 0x1a002000 0 0x1000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>;
clocks = <&scpsys SCP_SYS_CAM>, <&camsys CAMSYS_LARB7_CGPDN>;
clock-names = "scp-cam", "cam-larb7";
mediatek,smi-id = <7>;
};
cam1@1a003000 {
compatible = "mediatek,cam1";
reg = <0 0x1a003000 0 0x1000>;
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_LOW>;
};
cam2@1a004000 {
compatible = "mediatek,cam2";
reg = <0 0x1a004000 0 0x2000>;
interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_LOW>;
};
cam3@1a006000 {
compatible = "mediatek,cam3";
reg = <0 0x1a006000 0 0x2000>;
interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_LOW>;
};
cam4@1a008000 {
compatible = "mediatek,cam4";
reg = <0 0x1a008000 0 0x2000>;
interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_LOW>;
};
camsv1@1a050000 {
compatible = "mediatek,camsv1";
reg = <0 0x1a050000 0 0x1000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>;
};
camsv2@1a051000 {
compatible = "mediatek,camsv2";
reg = <0 0x1a051000 0 0x1000>;
interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>;
};
camsv3@1a052000 {
compatible = "mediatek,camsv3";
reg = <0 0x1a052000 0 0x1000>;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_LOW>;
};
camsv4@1a053000 {
compatible = "mediatek,camsv4";
reg = <0 0x1a053000 0 0x1000>;
interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_LOW>;
};
camsv5@1a054000 {
compatible = "mediatek,camsv5";
reg = <0 0x1a054000 0 0x1000>;
};
camsv6@1a055000 {
compatible = "mediatek,camsv6";
reg = <0 0x1a055000 0 0x1000>;
};
seninf1_csi2@1a040000 {
compatible = "mediatek,seninf1_csi2";
reg = <0 0x1a040000 0 0x1000>;
};
seninf2_csi2@1a041000 {
compatible = "mediatek,seninf2_csi2";
reg = <0 0x1a041000 0 0x1000>;
};
seninf3_csi2@1a042000 {
compatible = "mediatek,seninf3_csi2";
reg = <0 0x1a042000 0 0x1000>;
};
seninf4_csi2@1a043000 {
compatible = "mediatek,seninf4_csi2";
reg = <0 0x1a043000 0 0x1000>;
};
seninf5_csi2@1a044000 {
compatible = "mediatek,seninf5_csi2";
reg = <0 0x1a044000 0 0x1000>;
};
seninf6_csi2@1a045000 {
compatible = "mediatek,seninf6_csi2";
reg = <0 0x1a045000 0 0x1000>;
};
seninf1@1a040000 {
compatible = "mediatek,seninf1";
reg = <0 0x1a040000 0 0x1000>;
};
seninf2@1a041000 {
compatible = "mediatek,seninf2";
reg = <0 0x1a041000 0 0x1000>;
};
seninf3@1a042000 {
compatible = "mediatek,seninf3";
reg = <0 0x1a042000 0 0x1000>;
};
seninf4@1a043000 {
compatible = "mediatek,seninf4";
reg = <0 0x1a043000 0 0x1000>;
};
seninf5@1a044000 {
compatible = "mediatek,seninf5";
reg = <0 0x1a044000 0 0x1000>;
};
seninf_top@1a040000 {
compatible = "mediatek,seninf_top";
reg = <0 0x1a040000 0 0x1000>;
#if 0
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_LOW>;
#endif
clocks = <&scpsys SCP_SYS_DIS>,
<&scpsys SCP_SYS_CAM>,
<&camsys CAMSYS_SENINF_CGPDN>,
<&topckgen TOP_MUX_SENINF>,
<&topckgen TOP_MUX_SENINF1>,
<&topckgen TOP_MUX_SENINF2>,
<&topckgen TOP_MUX_CAMTG>,
<&topckgen TOP_MUX_CAMTG2>,
<&topckgen TOP_MUX_CAMTG3>,
<&topckgen TOP_MUX_CAMTG4>,
<&topckgen TOP_MUX_CAMTG5>,
<&clk26m>,
<&topckgen TOP_UNIVP_192M_D8>,
<&topckgen TOP_UNIVPLL_D3_D8>,
<&topckgen TOP_UNIVP_192M_D4>,
<&topckgen TOP_F26M_CK_D2>,
<&topckgen TOP_UNIVP_192M_D16>,
<&topckgen TOP_UNIVP_192M_D32>;
clock-names = "SCP_SYS_DIS",
"SCP_SYS_CAM",
"CAMSYS_SENINF_CGPDN",
"TOP_MUX_SENINF",
"TOP_MUX_SENINF1",
"TOP_MUX_SENINF2",
"TOP_MUX_CAMTG",
"TOP_MUX_CAMTG2",
"TOP_MUX_CAMTG3",
"TOP_MUX_CAMTG4",
"TOP_MUX_CAMTG5",
"TOP_CLK26M",
"TOP_UNIVP_192M_D8",
"TOP_UNIVPLL_D3_D8",
"TOP_UNIVP_192M_D4",
"TOP_F26M_CK_D2",
"TOP_UNIVP_192M_D16",
"TOP_UNIVP_192M_D32";
};
kd_camera_hw1:kd_camera_hw1@1a040000 {
compatible = "mediatek,imgsensor";
};
camera_af_hw_node: camera_af_hw_node {
compatible = "mediatek,camera_af_lens";
};
flashlight_core: flashlight_core {
compatible = "mediatek,flashlight_core";
};
flashlights_mt6360: flashlights_mt6360 {
compatible = "mediatek,flashlights_mt6360";
decouple = <0>;
channel@1 {
type = <0>;
ct = <0>;
part = <0>;
};
channel@2 {
type = <0>;
ct = <1>;
part = <0>;
};
};
ccu@1a0a0000 {
compatible = "mediatek,ccu";
reg = <0 0x1a0a1000 0 0x1000>;
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
clocks = <&camsys CAMSYS_CCU_CGPDN>,
<&mmsys_config MMSYS_GALS_CCU2MM>,
<&scpsys SCP_SYS_CAM>;
clock-names = "CCU_CLK_CAM_CCU",
"CCU_CLK_MMSYS_CCU",
"CAM_PWR";
#ifdef CONFIG_MTK_IOMMU_V2
iommus = <&iommu0 M4U_PORT_CCUG>;
#endif
};
/* ATF logger SW IRQ number 120 = 32 + 88 */
atf_logger {
compatible = "mediatek,atf_logger";
interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
};
/* AMMS SW IRQ number GIC:366 DTS:334*/
amms_control {
compatible = "mediatek,amms";
interrupts = <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>;
};
odm: odm {
compatible = "simple-bus";
/* reserved for overlay by odm */
};
memory_ssmr_features: memory-ssmr-features {
compatible = "mediatek,memory-ssmr-features";
svp-region-based-size = <0 0x10000000>;
iris-recognition-size = <0 0x10000000>;
2d_fr-size = <0 0x8000000>;
tui-size = <0 0x4000000>;
wfd-size = <0 0x4000000>;
prot-region-based-size = <0 0x8000000>;
ta-elf-size = <0 0x1000000>;
ta-stack-heap-size = <0 0x6000000>;
sdsp-tee-sharedmem-size = <0 0x1000000>;
sdsp-firmware-size = <0 0x1000000>;
};
ssmr {
compatible = "mediatek,trusted_mem";
memory-region = <&ssmr_cma_mem>;
};
alc@60000000 {
compatible = "mediatek,alc";
reg = <0 0x60000000 0 0x1000>;
};
md_config@80000000 {
compatible = "mediatek,md_config";
reg = <0 0x80000000 0 0x1000>;
};
md_uart0@80010000 {
compatible = "mediatek,md_uart0";
reg = <0 0x80010000 0 0x1000>;
};
md_p_dma@80020000 {
compatible = "mediatek,md_p_dma";
reg = <0 0x80020000 0 0x1000>;
};
md_gpt@80030000 {
compatible = "mediatek,md_gpt";
reg = <0 0x80030000 0 0x1000>;
};
simif1@80040000 {
compatible = "mediatek,simif1";
reg = <0 0x80040000 0 0x1000>;
};
simif2@80050000 {
compatible = "mediatek,simif2";
reg = <0 0x80050000 0 0x1000>;
};
md_peri_misc@80060000 {
compatible = "mediatek,md_peri_misc";
reg = <0 0x80060000 0 0x1000>;
};
md_cirq@f0070000 {
compatible = "mediatek,md_cirq";
reg = <0 0xf0070000 0 0x1000>;
};
md_debug1@80080000 {
compatible = "mediatek,md_debug1";
reg = <0 0x80080000 0 0x1000>;
};
md_debug2@80090000 {
compatible = "mediatek,md_debug2";
reg = <0 0x80090000 0 0x1000>;
};
md_debug3@800a0000 {
compatible = "mediatek,md_debug3";
reg = <0 0x800a0000 0 0x1000>;
};
mdpar_dbgmon@800b0000 {
compatible = "mediatek,mdpar_dbgmon";
reg = <0 0x800b0000 0 0x1000>;
};
md_peri_clk_ctl@800c0000 {
compatible = "mediatek,md_peri_clk_ctl";
reg = <0 0x800c0000 0 0x1000>;
};
md_topsm@f00d0000 {
compatible = "mediatek,md_topsm";
reg = <0 0xf00d0000 0 0x1000>;
};
md_ost@f00e0000 {
compatible = "mediatek,md_ost";
reg = <0 0xf00e0000 0 0x1000>;
};
md_rgu@f00f0000 {
compatible = "mediatek,md_rgu";
reg = <0 0xf00f0000 0 0x1000>;
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_FALLING>;
};
md_i2c@80100000 {
compatible = "mediatek,md_i2c";
reg = <0 0x80100000 0 0x1000>;
};
md_eint@80110000 {
compatible = "mediatek,md_eint";
reg = <0 0x80110000 0 0x1000>;
};
md_clkctl@80120000 {
compatible = "mediatek,md_clkctl";
reg = <0 0x80120000 0 0x1000>;
};
md_global_con_dcm@80130000 {
compatible = "mediatek,md_global_con_dcm";
reg = <0 0x80130000 0 0x1000>;
};
md_pll_mixedsys@80140000 {
compatible = "mediatek,md_pll_mixedsys";
reg = <0 0x80140000 0 0x1000>;
};
md_clksw@80150000 {
compatible = "mediatek,md_clksw";
reg = <0 0x80150000 0 0x1000>;
};
a7_ost@f0160000 {
compatible = "mediatek,a7_ost";
reg = <0 0xf0160000 0 0x1000>;
};
md_lite_gpt@80170000 {
compatible = "mediatek,md_lite_gpt";
reg = <0 0x80170000 0 0x1000>;
};
mdperi_mbist_config@801a0000 {
compatible = "mediatek,mdperi_mbist_config";
reg = <0 0x801a0000 0 0x1000>;
};
md_sdf_top@801b0000 {
compatible = "mediatek,md_sdf_top";
reg = <0 0x801b0000 0 0x1000>;
};
psmcu_misc@80200000 {
compatible = "mediatek,psmcu_misc";
reg = <0 0x80200000 0 0x1000>;
};
psmcu_busmon@80210000 {
compatible = "mediatek,psmcu_busmon";
reg = <0 0x80210000 0 0x1000>;
};
goodix_fp: fingerprint {
compatible = "mediatek,goodix-fp";
};
accdet: accdet {
compatible = "mediatek,pmic-accdet";
io-channels = <&pmic_auxadc AUXADC_ACCDET>;
io-channel-names = "pmic_accdet";
/* ACCDET GPIO standardization for AP EINT */
/*
*pinctrl-names = "default", "state_eint_as_int";
*pinctrl-0 = <&accdet_pins_default>;
*pinctrl-1 = <&accdet_pins_eint_as_int>;
*/
};
/*
*&pio {
* accdet_pins_default: accdetdefault {
* };
* accdet_pins_eint_as_int: accdeteint@0 {
* pins_cmd_dat {
* pinmux = <PINMUX_GPIO9__FUNC_GPIO9>;
* slew-rate = <0>;
* bias-disable;
* };
* };
*};
*/
mt6359_gauge {
compatible = "mediatek,mt6359_gauge";
bootmode = <&chosen>;
gauge_name = "gauge";
alias_name = "MT6359";
io-channels = <&pmic_auxadc AUXADC_BAT_TEMP>,
<&pmic_auxadc AUXADC_BATADC>,
<&pmic_auxadc AUXADC_VBIF>,
<&pmic_auxadc AUXADC_IMP>,
<&pmic_auxadc AUXADC_IMIX_R>;
io-channel-names = "pmic_battery_temp",
"pmic_battery_voltage",
"pmic_bif_voltage",
"pmic_ptim_voltage",
"pmic_ptim_r";
};
gauge_timer {
compatible = "mediatek,gauge_timer_service";
};
#if (CONFIG_MTK_GAUGE_VERSION == 30)
#include "mediatek/bat_setting/mt6785_battery_prop.dtsi"
#endif
mtkfb: mtkfb {
compatible = "mediatek,mtkfb";
};
dispsys {
compatible = "mediatek,dispsys";
mediatek,larb = <&smi_larb0 &smi_larb1>;
clocks = <&scpsys SCP_SYS_DIS>,
<&mmsys_config MMSYS_SMI_COMMON>,
<&mmsys_config MMSYS_SMI_LARB0>,
<&mmsys_config MMSYS_SMI_LARB1>,
<&mmsys_config MMSYS_GALS_COMM0>,
<&mmsys_config MMSYS_GALS_COMM1>,
<&mmsys_config MMSYS_DISP_OVL0>,
<&mmsys_config MMSYS_DISP_OVL0_2L>,
<&mmsys_config MMSYS_DISP_OVL1_2L>,
<&mmsys_config MMSYS_DISP_RDMA0>,
<&mmsys_config MMSYS_DISP_RDMA1>,
<&mmsys_config MMSYS_DISP_WDMA0>,
<&mmsys_config MMSYS_DISP_COLOR0>,
<&mmsys_config MMSYS_DISP_CCORR0>,
<&mmsys_config MMSYS_DISP_AAL0>,
<&mmsys_config MMSYS_DISP_GAMMA0>,
<&mmsys_config MMSYS_DISP_DITHER0>,
<&mmsys_config MMSYS_DSI0_MM_CK>,
<&mmsys_config MMSYS_DSI0_IF_CK>,
<&mmsys_config MMSYS_DPI_MM_CK>,
<&mmsys_config MMSYS_DPI_IF_CK>,
<&mmsys_config MMSYS_26M>,
<&mmsys_config MMSYS_DISP_RSZ>,
<&topckgen TOP_MUX_MM>,
<&topckgen TOP_MUX_DISP_PWM>,
<&infracfg_ao INFRACFG_AO_DISP_PWM_CG>,
<&clk26m>,
<&mmsys_config MMSYS_DISP_POSTMASK0>,
<&mmsys_config MMSYS_DISP_OVL_FBDC>,
<&topckgen TOP_UNIVPLL_D3_D2>,
<&topckgen TOP_UNIVPLL_D3_D4>,
<&topckgen TOP_OSC_D2>,
<&topckgen TOP_OSC_D4>,
<&topckgen TOP_OSC_D16>,
<&topckgen TOP_MUX_DPI0>,
<&topckgen TOP_TVDPLL_D2>,
<&topckgen TOP_TVDPLL_D4>,
<&topckgen TOP_TVDPLL_D8>,
<&topckgen TOP_TVDPLL_D16>,
<&topckgen TOP_TVDPLL_CK>,
<&apmixed APMIXED_MIPID0_26M>;
clock-names = "CLK_MM_MTCMOS",
"CLK_SMI_COMMON",
"CLK_SMI_LARB0",
"CLK_SMI_LARB1",
"CLK_GALS_COMM0",
"CLK_GALS_COMM1",
"CLK_DISP_OVL0",
"CLK_DISP_OVL0_2L",
"CLK_DISP_OVL1_2L",
"CLK_DISP_RDMA0",
"CLK_DISP_RDMA1",
"CLK_DISP_WDMA0",
"CLK_DISP_COLOR0",
"CLK_DISP_CCORR0",
"CLK_DISP_AAL0",
"CLK_DISP_GAMMA0",
"CLK_DISP_DITHER0",
"CLK_DSI0_MM_CK",
"CLK_DSI0_IF_CK",
"CLK_DPI_MM_CK",
"CLK_DPI_IF_CK",
"CLK_MM_26M",
"CLK_DISP_RSZ",
"CLK_MUX_MM",
"CLK_MUX_DISP_PWM",
"CLK_DISP_PWM",
"CLK_26M",
"CLK_DISP_POSTMASK",
"CLK_DISP_OVL_FBDC",
"CLK_UNIVPLL_D3_D2",
"CLK_UNIVPLL_D3_D4",
"CLK_OSC_D2",
"CLK_OSC_D4",
"CLK_OSC_D16",
"CLK_MUX_DPI0",
"CLK_TVDPLL_D2",
"CLK_TVDPLL_D4",
"CLK_TVDPLL_D8",
"CLK_TVDPLL_D16",
"CLK_TVDPLL_CK",
"CLK_MIPID0_26M";
};
dsi_te: dsi_te {
compatible = "mediatek, dsi_te-eint";
status = "disabled";
};
mt6382_nfc: mt6382_nfc {
compatible = "mediatek, mt6382_nfc-eint";
interrupt-parent = <&pio>;
interrupts = <25 IRQ_TYPE_EDGE_BOTH 25 0>;
mt6382_nfc_srclk = <&pio 25 0x0>;
status = "okay";
};
mtee_svp: mtee_svp {
compatible = "medaitek,svp";
};
/* svp end */
disp_ovl0@14008000 {
compatible = "mediatek,disp_ovl0";
reg = <0 0x14008000 0 0x1000>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
};
disp_ovl0_2l@14009000 {
compatible = "mediatek,disp_ovl0_2l";
reg = <0 0x14009000 0 0x1000>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>;
};
disp_ovl1_2l@1400a000 {
compatible = "mediatek,disp_ovl1_2l";
reg = <0 0x1400a000 0 0x1000>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_LOW>;
};
disp_rdma0@1400b000 {
compatible = "mediatek,disp_rdma0";
reg = <0 0x1400b000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
};
disp_rdma1@1400c000 {
compatible = "mediatek,disp_rdma1";
reg = <0 0x1400c000 0 0x1000>;
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_LOW>;
};
disp_wdma0@1400d000 {
compatible = "mediatek,disp_wdma0";
reg = <0 0x1400d000 0 0x1000>;
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_LOW>;
};
disp_color0: disp_color0@1400e000 {
compatible = "mediatek,disp_color0";
reg = <0 0x1400e000 0 0x1000>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys_config MMSYS_DISP_COLOR0>;
clock-names = "MDP_COLOR";
};
disp_ccorr0@1400f000 {
compatible = "mediatek,disp_ccorr0";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_LOW>;
};
disp_aal0@14010000 {
compatible = "mediatek,disp_aal0";
reg = <0 0x14010000 0 0x1000>;
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_LOW>;
};
disp_gamma0@14011000 {
compatible = "mediatek,disp_gamma0";
reg = <0 0x14011000 0 0x1000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_LOW>;
};
disp_dither0@14012000 {
compatible = "mediatek,disp_dither0";
reg = <0 0x14012000 0 0x1000>;
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_LOW>;
};
dsi_split@14013000 {
compatible = "mediatek,dsi_split";
reg = <0 0x14013000 0 0x1000>;
};
dsi0@14014000 {
compatible = "mediatek,dsi0";
reg = <0 0x14014000 0 0x1000>;
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_LOW>;
};
dpi0@14015000 {
compatible = "mediatek,dpi0";
reg = <0 0x14015000 0 0x1000>;
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_LOW>;
};
mm_mutex: mm_mutex@14016000 {
compatible = "mediatek,mm_mutex";
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_LOW>;
};
md_pcm@80220000 {
compatible = "mediatek,md_pcm";
reg = <0 0x80220000 0 0x1000>;
};
psmcu_mbist_config@80240000 {
compatible = "mediatek,psmcu_mbist_config";
reg = <0 0x80240000 0 0x1000>;
};
md_elm@80250000 {
compatible = "mediatek,md_elm";
reg = <0 0x80250000 0 0x1000>;
};
md_abm@80260000 {
compatible = "mediatek,md_abm";
reg = <0 0x80260000 0 0x1000>;
};
md_soe@80310000 {
compatible = "mediatek,md_soe";
reg = <0 0x80310000 0 0x1000>;
};
md_infra_busmon@80320000 {
compatible = "mediatek,md_infra_busmon";
reg = <0 0x80320000 0 0x1000>;
};
md_uart1@80330000 {
compatible = "mediatek,md_uart1";
reg = <0 0x80330000 0 0x1000>;
};
md_uart2@80340000 {
compatible = "mediatek,md_uart2";
reg = <0 0x80340000 0 0x1000>;
};
mdinfra_mbist_config@80350000 {
compatible = "mediatek,mdinfra_mbist_config";
reg = <0 0x80350000 0 0x1000>;
};
mdsys_mbist_config@80360000 {
compatible = "mediatek,mdsys_mbist_config";
reg = <0 0x80360000 0 0x1000>;
};
mdsmicfg@803a0000 {
compatible = "mediatek,mdsmicfg";
reg = <0 0x803a0000 0 0x1000>;
};
mdinfra_misc@803b0000 {
compatible = "mediatek,mdinfra_misc";
reg = <0 0x803b0000 0 0x1000>;
};
md_bus_recoder@803c0000 {
compatible = "mediatek,md_bus_recoder";
reg = <0 0x803c0000 0 0x1000>;
};
md_ppc_top@803d0000 {
compatible = "mediatek,md_ppc_top";
reg = <0 0x803d0000 0 0x1000>;
};
a7_wdt@f0400000 {
compatible = "mediatek,a7_wdt";
reg = <0 0xf0400000 0 0x1000>;
};
a7_mbist_config@f0410000 {
compatible = "mediatek,a7_mbist_config";
reg = <0 0xf0410000 0 0x1000>;
};
a7_cirq@f0420000 {
compatible = "mediatek,a7_cirq";
reg = <0 0xf0420000 0 0x1000>;
};
pf_bsi_apb1@80200000 {
compatible = "mediatek,pf_bsi_apb1";
reg = <0 0x80200000 0 0x1000>;
};
pf_bsi_apb2@80201000 {
compatible = "mediatek,pf_bsi_apb2";
reg = <0 0x80201000 0 0x1000>;
};
rfic1_bsispi@80202000 {
compatible = "mediatek,rfic1_bsispi";
reg = <0 0x80202000 0 0x1000>;
};
rfic2_bsispi@80203000 {
compatible = "mediatek,rfic2_bsispi";
reg = <0 0x80203000 0 0x1000>;
};
mipi0_bsispi@80205000 {
compatible = "mediatek,mipi0_bsispi";
reg = <0 0x80205000 0 0x1000>;
};
mipi1_bsispi@80206000 {
compatible = "mediatek,mipi1_bsispi";
reg = <0 0x80206000 0 0x1000>;
};
idc_suart@80207000 {
compatible = "mediatek,idc_suart";
reg = <0 0x80207000 0 0x1000>;
};
mdm_psys_misc@8020d000 {
compatible = "mediatek,mdm_psys_misc";
reg = <0 0x8020d000 0 0x1000>;
};
mdm_psys_mbistcon@8020e000 {
compatible = "mediatek,mdm_psys_mbistcon";
reg = <0 0x8020e000 0 0x1000>;
};
md1_abb_mixedsys@8020c000 {
compatible = "mediatek,md1_abb_mixedsys";
reg = <0 0x8020c000 0 0x1000>;
};
md2_abb_mixedsys@8020c000 {
compatible = "mediatek,md2_abb_mixedsys";
reg = <0 0x8020c000 0 0x1000>;
};
idma@82000000 {
compatible = "mediatek,idma";
reg = <0 0x82000000 0 0x1000>;
};
ahb2dspio@82800000 {
compatible = "mediatek,ahb2dspio";
reg = <0 0x82800000 0 0x1000>;
};
md2g_confg@82c00000 {
compatible = "mediatek,md2g_confg";
reg = <0 0x82c00000 0 0x1000>;
};
apc@82c30000 {
compatible = "mediatek,apc";
reg = <0 0x82c30000 0 0x1000>;
};
csd_acc@82c70000 {
compatible = "mediatek,csd_acc";
reg = <0 0x82c70000 0 0x1000>;
};
share_d1@82ca0000 {
compatible = "mediatek,share_d1";
reg = <0 0x82ca0000 0 0x1000>;
};
irdma@82cb0000 {
compatible = "mediatek,irdma";
reg = <0 0x82cb0000 0 0x1000>;
};
patch@82cc0000 {
compatible = "mediatek,patch";
reg = <0 0x82cc0000 0 0x1000>;
};
mdafe@82cd0000 {
compatible = "mediatek,mdafe";
reg = <0 0x82cd0000 0 0x1000>;
};
bfe@82ce0000 {
compatible = "mediatek,bfe";
reg = <0 0x82ce0000 0 0x1000>;
};
modem_lite_confg@83000000 {
compatible = "mediatek,modem_lite_confg";
reg = <0 0x83000000 0 0x1000>;
};
modem_lite_topsm@83010000 {
compatible = "mediatek,modem_lite_topsm";
reg = <0 0x83010000 0 0x1000>;
};
tdma@83020000 {
compatible = "mediatek,tdma";
reg = <0 0x83020000 0 0x1000>;
};
shreg2@83030000 {
compatible = "mediatek,shreg2";
reg = <0 0x83030000 0 0x1000>;
};
divider@83040000 {
compatible = "mediatek,divider";
reg = <0 0x83040000 0 0x1000>;
};
fcs@83050000 {
compatible = "mediatek,fcs";
reg = <0 0x83050000 0 0x1000>;
};
gcu@83060000 {
compatible = "mediatek,gcu";
reg = <0 0x83060000 0 0x1000>;
};
bsi_2g@83070000 {
compatible = "mediatek,bsi_2g";
reg = <0 0x83070000 0 0x1000>;
};
bpi_2g@83080000 {
compatible = "mediatek,bpi_2g";
reg = <0 0x83080000 0 0x1000>;
};
afc_2g@83090000 {
compatible = "mediatek,afc_2g";
reg = <0 0x83090000 0 0x1000>;
};
tdd@84000000 {
compatible = "mediatek,tdd";
reg = <0 0x84000000 0 0x1000>;
};
l2ulsbdma@85000000 {
compatible = "mediatek,l2ulsbdma";
reg = <0 0x85000000 0 0x1000>;
};
l2ulhbdma@85010000 {
compatible = "mediatek,l2ulhbdma";
reg = <0 0x85010000 0 0x1000>;
};
l2dlsbdma@85020000 {
compatible = "mediatek,l2dlsbdma";
reg = <0 0x85020000 0 0x1000>;
};
l2dlhbdma@85030000 {
compatible = "mediatek,l2dlhbdma";
reg = <0 0x85030000 0 0x1000>;
};
l2mbist@85040000 {
compatible = "mediatek,l2mbist";
reg = <0 0x85040000 0 0x1000>;
};
l2pseuphy@85050000 {
compatible = "mediatek,l2pseuphy";
reg = <0 0x85050000 0 0x1000>;
};
l2hwlog@85058000 {
compatible = "mediatek,l2hwlog";
reg = <0 0x85058000 0 0x1000>;
};
l2soindma@85060000 {
compatible = "mediatek,l2soindma";
reg = <0 0x85060000 0 0x1000>;
};
l2sooutdma@85070000 {
compatible = "mediatek,l2sooutdma";
reg = <0 0x85070000 0 0x1000>;
};
l2ullmac@85080000 {
compatible = "mediatek,l2ullmac";
reg = <0 0x85080000 0 0x1000>;
};
l2dllmac@85090000 {
compatible = "mediatek,l2dllmac";
reg = <0 0x85090000 0 0x1000>;
};
l2calmac@85098000 {
compatible = "mediatek,l2calmac";
reg = <0 0x85098000 0 0x1000>;
};
l2ulfifomng@850a0000 {
compatible = "mediatek,l2ulfifomng";
reg = <0 0x850a0000 0 0x1000>;
};
l2dlfifomng@850a4000 {
compatible = "mediatek,l2dlfifomng";
reg = <0 0x850a4000 0 0x1000>;
};
l2sofifomng@850a8000 {
compatible = "mediatek,l2sofifomng";
reg = <0 0x850a8000 0 0x1000>;
};
l2sec@850b0000 {
compatible = "mediatek,l2sec";
reg = <0 0x850b0000 0 0x1000>;
};
l2ulsecctl@850b4000 {
compatible = "mediatek,l2ulsecctl";
reg = <0 0x850b4000 0 0x1000>;
};
l2dlsecctl@850b8000 {
compatible = "mediatek,l2dlsecctl";
reg = <0 0x850b8000 0 0x1000>;
};
l2sosecctl@850bc000 {
compatible = "mediatek,l2sosecctl";
reg = <0 0x850bc000 0 0x1000>;
};
l2misc@850c0000 {
compatible = "mediatek,l2misc";
reg = <0 0x850c0000 0 0x1000>;
};
l2ulbuf@850e0000 {
compatible = "mediatek,l2ulbuf";
reg = <0 0x850e0000 0 0x1000>;
};
l2dlbuf@850f0000 {
compatible = "mediatek,l2dlbuf";
reg = <0 0x850f0000 0 0x1000>;
};
mdl1ao@f60f0000 {
compatible = "mediatek,mdl1ao";
reg = <0 0xf60f0000 0 0x1000>;
};
modem_confg@87000000 {
compatible = "mediatek,modem_confg";
reg = <0 0x87000000 0 0x1000>;
};
modem_topsm@87010000 {
compatible = "mediatek,modem_topsm";
reg = <0 0x87010000 0 0x1000>;
};
bsi_3g@87070000 {
compatible = "mediatek,bsi_3g";
reg = <0 0x87070000 0 0x1000>;
};
bpi_3g@87080000 {
compatible = "mediatek,bpi_3g";
reg = <0 0x87080000 0 0x1000>;
};
afc_3g@87090000 {
compatible = "mediatek,afc_3g";
reg = <0 0x87090000 0 0x1000>;
};
wcdma_timer@870a0000 {
compatible = "mediatek,wcdma_timer";
reg = <0 0x870a0000 0 0x1000>;
};
dpa_bc@870b0000 {
compatible = "mediatek,dpa_bc";
reg = <0 0x870b0000 0 0x1000>;
};
pfc_encode@870c0000 {
compatible = "mediatek,pfc_encode";
reg = <0 0x870c0000 0 0x1000>;
};
pfc_decode@870d0000 {
compatible = "mediatek,pfc_decode";
reg = <0 0x870d0000 0 0x1000>;
};
hspasys_1_confg@87200000 {
compatible = "mediatek,hspasys_1_confg";
reg = <0 0x87200000 0 0x1000>;
};
hseq@87210000 {
compatible = "mediatek,hseq";
reg = <0 0x87210000 0 0x1000>;
};
hsce@87220000 {
compatible = "mediatek,hsce";
reg = <0 0x87220000 0 0x1000>;
};
hspasys_1_mbist@87230000 {
compatible = "mediatek,hspasys_1_mbist";
reg = <0 0x87230000 0 0x1000>;
};
hspasys_2_confg@87400000 {
compatible = "mediatek,hspasys_2_confg";
reg = <0 0x87400000 0 0x1000>;
};
hseq_dc@87410000 {
compatible = "mediatek,hseq_dc";
reg = <0 0x87410000 0 0x1000>;
};
hsce_dc@87420000 {
compatible = "mediatek,hsce_dc";
reg = <0 0x87420000 0 0x1000>;
};
rake_dc@87430000 {
compatible = "mediatek,rake_dc";
reg = <0 0x87430000 0 0x1000>;
};
hspasys_2_mbist@87440000 {
compatible = "mediatek,hspasys_2_mbist";
reg = <0 0x87440000 0 0x1000>;
};
uea_uia_u0@87600000 {
compatible = "mediatek,uea_uia_u0";
reg = <0 0x87600000 0 0x1000>;
};
uea_uia_u1@87610000 {
compatible = "mediatek,uea_uia_u1";
reg = <0 0x87610000 0 0x1000>;
};
dpa_rlc@87620000 {
compatible = "mediatek,dpa_rlc";
reg = <0 0x87620000 0 0x1000>;
};
dpa_mac@87630000 {
compatible = "mediatek,dpa_mac";
reg = <0 0x87630000 0 0x1000>;
};
upa@f0920000 {
compatible = "mediatek,upa";
reg = <0 0xf0920000 0 0x1000>;
};
h_rxbrp@87650000 {
compatible = "mediatek,h_rxbrp";
reg = <0 0x87650000 0 0x1000>;
};
rxbrp@87660000 {
compatible = "mediatek,rxbrp";
reg = <0 0x87660000 0 0x1000>;
};
hspasys_3_confg@f0910000 {
compatible = "mediatek,hspasys_3_confg";
reg = <0 0xf0910000 0 0x1000>;
};
txbrp@87680000 {
compatible = "mediatek,txbrp";
reg = <0 0x87680000 0 0x1000>;
};
txcrp@87690000 {
compatible = "mediatek,txcrp";
reg = <0 0x87690000 0 0x1000>;
};
h_txbrp@876a0000 {
compatible = "mediatek,h_txbrp";
reg = <0 0x876a0000 0 0x1000>;
};
txupc@876b0000 {
compatible = "mediatek,txupc";
reg = <0 0x876b0000 0 0x1000>;
};
bc@876c0000 {
compatible = "mediatek,bc";
reg = <0 0x876c0000 0 0x1000>;
};
dbg_tx@876d0000 {
compatible = "mediatek,dbg_tx";
reg = <0 0x876d0000 0 0x1000>;
};
hspasys_3_mbist@876e0000 {
compatible = "mediatek,hspasys_3_mbist";
reg = <0 0x876e0000 0 0x1000>;
};
rxsrp@87800000 {
compatible = "mediatek,rxsrp";
reg = <0 0x87800000 0 0x1000>;
};
indec@87810000 {
compatible = "mediatek,indec";
reg = <0 0x87810000 0 0x1000>;
};
rake_0@87820000 {
compatible = "mediatek,rake_0";
reg = <0 0x87820000 0 0x1000>;
};
rake_1@87830000 {
compatible = "mediatek,rake_1";
reg = <0 0x87830000 0 0x1000>;
};
rake_2@87840000 {
compatible = "mediatek,rake_2";
reg = <0 0x87840000 0 0x1000>;
};
searcher@87850000 {
compatible = "mediatek,searcher";
reg = <0 0x87850000 0 0x1000>;
};
rxdfe@87860000 {
compatible = "mediatek,rxdfe";
reg = <0 0x87860000 0 0x1000>;
};
hspasys_4_confg@87870000 {
compatible = "mediatek,hspasys_4_confg";
reg = <0 0x87870000 0 0x1000>;
};
dbg@87880000 {
compatible = "mediatek,dbg";
reg = <0 0x87880000 0 0x1000>;
};
dwrap0@87890000 {
compatible = "mediatek,dwrap0";
reg = <0 0x87890000 0 0x1000>;
};
log3g@878a0000 {
compatible = "mediatek,log3g";
reg = <0 0x878a0000 0 0x1000>;
};
hspasys_4_mbist@878b0000 {
compatible = "mediatek,hspasys_4_mbist";
reg = <0 0x878b0000 0 0x1000>;
};
dwrap1@878c0000 {
compatible = "mediatek,dwrap1";
reg = <0 0x878c0000 0 0x1000>;
};
c2ksys@38000000 {
compatible = "mediatek,c2ksys";
reg = <0 0x38000000 0 0x1000>;
};
mt_charger: mt_charger {
compatible = "mediatek,mt-charger";
bootmode = <&chosen>;
};
lk_charger: lk_charger {
compatible = "mediatek,lk_charger";
enable_anime;
/* enable_pe_plus; */
enable_pd20_reset;
power_path_support;
max_charger_voltage = <6500000>;
fast_charge_voltage = <3000000>;
/* charging current */
usb_charger_current = <500000>;
ac_charger_current = <2050000>;
ac_charger_input_current = <3200000>;
non_std_ac_charger_current = <500000>;
charging_host_charger_current = <1500000>;
ta_ac_charger_current = <3000000>;
pd_charger_current = <500000>;
/* battery temperature protection */
temp_t4_threshold = <50>;
temp_t3_threshold = <45>;
temp_t1_threshold = <0>;
};
charger: charger {
compatible = "mediatek,charger";
algorithm_name = "SwitchCharging";
/* enable_sw_jeita; */
/* enable_pe_plus; */
/* enable_pe_2; */
/* enable_pe_3; */
/* enable_pe_4; */
enable_type_c;
power_path_support;
enable_dynamic_mivr;
bootmode = <&chosen>;
/* common */
battery_cv = <4350000>;
max_charger_voltage = <6500000>;
min_charger_voltage = <4600000>;
/* dynamic mivr */
min_charger_voltage_1 = <4400000>;
min_charger_voltage_2 = <4200000>;
max_dmivr_charger_current = <1400000>;
/* charging current */
usb_charger_current_suspend = <0>;
usb_charger_current_unconfigured = <70000>;
usb_charger_current_configured = <500000>;
usb_charger_current = <500000>;
ac_charger_current = <2050000>;
ac_charger_input_current = <3200000>;
non_std_ac_charger_current = <500000>;
charging_host_charger_current = <1500000>;
apple_1_0a_charger_current = <650000>;
apple_2_1a_charger_current = <800000>;
ta_ac_charger_current = <3000000>;
/* sw jeita */
jeita_temp_above_t4_cv = <4240000>;
jeita_temp_t3_to_t4_cv = <4240000>;
jeita_temp_t2_to_t3_cv = <4340000>;
jeita_temp_t1_to_t2_cv = <4240000>;
jeita_temp_t0_to_t1_cv = <4040000>;
jeita_temp_below_t0_cv = <4040000>;
temp_t4_thres = <50>;
temp_t4_thres_minus_x_degree = <47>;
temp_t3_thres = <45>;
temp_t3_thres_minus_x_degree = <39>;
temp_t2_thres = <10>;
temp_t2_thres_plus_x_degree = <16>;
temp_t1_thres = <0>;
temp_t1_thres_plus_x_degree = <6>;
temp_t0_thres = <0>;
temp_t0_thres_plus_x_degree = <0>;
temp_neg_10_thres = <0>;
/* battery temperature protection */
enable_min_charge_temp;
min_charge_temp = <0>;
min_charge_temp_plus_x_degree = <6>;
max_charge_temp = <50>;
max_charge_temp_minus_x_degree = <47>;
/* PE */
ta_12v_support;
ta_9v_support;
pe_ichg_level_threshold = <1000000>; /* uA */
ta_ac_12v_input_current = <3200000>;
ta_ac_9v_input_current = <3200000>;
ta_ac_7v_input_current = <3200000>;
/* PE 2.0 */
pe20_ichg_level_threshold = <1000000>; /* uA */
ta_start_battery_soc = <0>;
ta_stop_battery_soc = <85>;
/* PE 4.0 */
high_temp_to_leave_pe40 = <46>;
high_temp_to_enter_pe40 = <39>;
low_temp_to_leave_pe40 = <10>;
low_temp_to_enter_pe40 = <16>;
/* PE 4.0 single charger*/
pe40_single_charger_input_current = <3000000>;
pe40_single_charger_current = <3000000>;
/* PE 4.0 dual charger*/
pe40_dual_charger_input_current = <3000000>;
pe40_dual_charger_chg1_current = <2000000>;
pe40_dual_charger_chg2_current = <2000000>;
pe40_stop_battery_soc = <80>;
/* PE 4.0 cable impedance (mohm) */
pe40_r_cable_1a_lower = <540>;
pe40_r_cable_2a_lower = <403>;
pe40_r_cable_3a_lower = <264>;
/* dual charger */
chg1_ta_ac_charger_current = <1500000>;
chg2_ta_ac_charger_current = <1500000>;
slave_mivr_diff = <100000>;
dual_polling_ieoc = <750000>;
/* cable measurement impedance */
cable_imp_threshold = <699>;
vbat_cable_imp_threshold = <3900000>; /* uV */
/* bif */
bif_threshold1 = <4250000>;
bif_threshold2 = <4300000>;
bif_cv_under_threshold2 = <4450000>;
/* PD */
pd_vbus_low_bound = <5000000>;
pd_vbus_upper_bound = <5000000>;
pd_ichg_level_threshold = <1000000>; /* uA */
pd_stop_battery_soc = <80>;
ibus_err = <14>;
vsys_watt = <5000000>;
};
pd_adapter: pd_adapter {
compatible = "mediatek,pd_adapter";
adapter_name = "pd_adapter";
};
rt9465_slave_chr: rt9465_slave_chr {
compatible = "richtek,rt9465";
};
subpmic_pmu_eint: mt6360_pmu_eint {
};
irtx_pwm:irtx_pwm {
compatible = "mediatek,irtx-pwm";
pwm_ch = <0>;
pwm_data_invert = <0>;
};
pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
compatible = "mediatek,pmic_clock_buffer";
mediatek,clkbuf-quantity = <7>;
mediatek,clkbuf-config = <2 1 1 2 0 0 1>;
mediatek,clkbuf-output-impedance = <6 4 6 4 0 0 6>;
mediatek,clkbuf-controls-for-desense = <0 4 0 4 0 0 0>;
};
gpio_usage_mapping: gpio_usage_mapping {
compatible = "mediatek,gpio_usage_mapping";
};
mrdump_ext_rst: mrdump_ext_rst {
compatible = "mediatek, mrdump_ext_rst-eint";
mode = "IRQ";
status = "okay";
};
touch: touch {
compatible = "goodix,touch", "mediatek,touch";
};
tcpc_pd: tcpc_pd {
};
msdc1_ins: msdc1_ins {
};
smart_pa: smart_pa {
};
vproc_buck: vproc_buck {
};
rt-pd-manager {
compatible = "mediatek,rt-pd-manager";
};
md1_sim1_hot_plug_eint:md1_sim1_hot_plug_eint{
};
md1_sim2_hot_plug_eint:md1_sim2_hot_plug_eint{
};
};
&i2c6 {
speaker_amp: speaker_amp@34 {
compatible = "mediatek,speaker_amp";
#sound-dai-cells = <0>;
reg = <0x34>;
status = "okay";
};
};
&pio {
aud_clk_mosi_off: aud_clk_mosi_off {
pins_cmd0_dat {
pinmux = <PINMUX_GPIO189__FUNC_GPIO189>;
input-enable;
bias-pull-down;
};
pins_cmd1_dat {
pinmux = <PINMUX_GPIO190__FUNC_GPIO190>;
input-enable;
bias-pull-down;
};
};
aud_clk_mosi_on: aud_clk_mosi_on {
pins_cmd0_dat {
pinmux = <PINMUX_GPIO189__FUNC_AUD_CLK_MOSI>;
input-schmitt-enable;
bias-disable;
};
pins_cmd1_dat {
pinmux = <PINMUX_GPIO190__FUNC_AUD_SYNC_MOSI>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_mosi_off: aud_dat_mosi_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO191__FUNC_GPIO191>;
input-enable;
bias-pull-down;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO192__FUNC_GPIO192>;
input-enable;
bias-pull-down;
};
};
aud_dat_mosi_on: aud_dat_mosi_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO191__FUNC_AUD_DAT_MOSI0>;
input-schmitt-enable;
bias-disable;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO192__FUNC_AUD_DAT_MOSI1>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_mosi_ch34_off: aud_dat_mosi_ch34_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
input-enable;
bias-pull-down;
};
};
aud_dat_mosi_ch34_on: aud_dat_mosi_ch34_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO143__FUNC_AUD_DAT_MOSI2>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_miso_off: aud_dat_miso_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO193__FUNC_GPIO193>;
input-enable;
bias-pull-down;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO194__FUNC_GPIO194>;
input-enable;
bias-pull-down;
};
};
aud_dat_miso_on: aud_dat_miso_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO193__FUNC_AUD_DAT_MISO0>;
input-schmitt-enable;
bias-disable;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO194__FUNC_AUD_DAT_MISO1>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_miso_ch34_off: aud_dat_miso_ch34_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO146__FUNC_GPIO146>;
input-enable;
bias-pull-down;
};
};
aud_dat_miso_ch34_on: aud_dat_miso_ch34_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO146__FUNC_AUD_DAT_MISO2>;
input-schmitt-enable;
bias-disable;
};
};
vow_dat_miso_off: vow_dat_miso_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO193__FUNC_GPIO193>;
input-enable;
bias-pull-down;
};
};
vow_dat_miso_on: vow_dat_miso_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO193__FUNC_VOW_DAT_MISO>;
input-schmitt-enable;
bias-disable;
};
};
vow_clk_miso_off: vow_clk_miso_off {
pins_cmd3_dat {
pinmux = <PINMUX_GPIO194__FUNC_GPIO194>;
input-enable;
bias-pull-down;
};
};
vow_clk_miso_on: vow_clk_miso_on {
pins_cmd3_dat {
pinmux = <PINMUX_GPIO194__FUNC_VOW_CLK_MISO>;
input-schmitt-enable;
bias-disable;
};
};
aud_nle_mosi_off: aud_nle_mosi_off {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO144__FUNC_GPIO144>;
input-enable;
bias-pull-down;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO145__FUNC_GPIO145>;
input-enable;
bias-pull-down;
};
};
aud_nle_mosi_on: aud_nle_mosi_on {
pins_cmd1_dat {
pinmux = <PINMUX_GPIO144__FUNC_AUD_NLE_MOSI1>;
input-schmitt-enable;
bias-disable;
};
pins_cmd2_dat {
pinmux = <PINMUX_GPIO145__FUNC_AUD_NLE_MOSI0>;
input-schmitt-enable;
bias-disable;
};
};
aud_dat_miso2_off: aud_dat_miso2_off {
pins_cmd3_dat {
pinmux = <PINMUX_GPIO146__FUNC_GPIO146>;
input-enable;
bias-pull-down;
};
};
aud_dat_miso2_on: aud_dat_miso2_on {
pins_cmd3_dat {
pinmux = <PINMUX_GPIO146__FUNC_AUD_DAT_MISO2>;
input-schmitt-enable;
bias-disable;
};
};
aud_gpio_i2s0_off: aud_gpio_i2s0_off {
pins_cmd_dat {
pinmux = <PINMUX_GPIO70__FUNC_GPIO70>;
};
};
aud_gpio_i2s0_on: aud_gpio_i2s0_on {
pins_cmd_dat {
pinmux = <PINMUX_GPIO70__FUNC_I2S0_DI>;
};
};
aud_gpio_i2s1_off: aud_gpio_i2s1_off {
};
aud_gpio_i2s1_on: aud_gpio_i2s1_on {
};
aud_gpio_i2s2_off: aud_gpio_i2s2_off {
};
aud_gpio_i2s2_on: aud_gpio_i2s2_on {
};
aud_gpio_i2s3_off: aud_gpio_i2s3_off {
pins_cmd_dat {
pinmux = <PINMUX_GPIO67__FUNC_GPIO67>,
<PINMUX_GPIO68__FUNC_GPIO68>,
<PINMUX_GPIO71__FUNC_GPIO71>;
};
};
aud_gpio_i2s3_on: aud_gpio_i2s3_on {
pins_cmd_dat {
pinmux = <PINMUX_GPIO67__FUNC_I2S3_LRCK>,
<PINMUX_GPIO68__FUNC_I2S3_DO>,
<PINMUX_GPIO71__FUNC_I2S3_BCK>;
};
};
aud_gpio_i2s5_off: aud_gpio_i2s5_off {
};
aud_gpio_i2s5_on: aud_gpio_i2s5_on {
};
};
#include "mediatek/v1/mt6359.dtsi"
#include "mediatek/cust_mt6785_msdc.dtsi"
#include "mediatek/v1/mt6360.dtsi"
#include "mediatek/v1/mt6360_pd.dtsi"
#ifdef CONFIG_MTK_ENABLE_GENIEZONE
#include "mediatek/trusty.dtsi"
#endif
Reference in New Issue Copy Permalink