# Xtensa default parameter values # Customer ID=7578; Build=0x88165; Copyright (c) 2004-2018 Tensilica Inc. ALL RIGHTS RESERVED. # These coded instructions, statements, and computer programs are the # copyrighted works and confidential proprietary information of Tensilica Inc. # They may not be modified, copied, reproduced, distributed, or disclosed to # third parties in any manner, medium, or form, in whole or in part, without # the prior written consent of Tensilica Inc. # WARNING: This file has been automatically generated with values that are # specific to a particular Xtensa processor configuration. Changing values # here will likely result in an inconsistent system. Do not edit! # Version information for software tools and target hardware SWToolsRelease = RI-2019.1 SWToolsVername = 14.01 SWToolsVersion = 1401000 HWMicroArchLatest = 270012 HWMicroArchEarliest = 270012 TargetHWVersion = LX7.0.12 ConfigName = Xm_hifi3_prod_v3 IsPreconfiguredCore = 0 uarchName = Barcelona HasVectorPipe = 0 HasXNNE = 0 # Preconfigured ISA parameters IsaIsBigEndian = 0 IsaMaxInstructionSize = 8 IsaUseWindowedRegisters = 1 IsaUseDensityInstruction = 1 IsaNumContexts = 1 IsaUseL32R = 1 IsaUseConst16 = 0 IsaUseAbs = 1 IsaUseAddx = 1 IsaUsePredictedBranches = 0 IsaUseNormShiftAmount = 1 IsaUseMinMax = 1 IsaUseSignExtend = 1 IsaUseDepBits = 0 IsaUseClamps = 1 IsaUseMAC16 = 0 IsaUseMul16 = 1 MUL32ImplementsMul16 = 1 MAC16ImplementsMul16 = 0 IsaUseS32C1I = 0 IsaUseTAPMaster = 0 IsaUseVectorFPU2005 = 0 IsaAssumesSPFPU = 1 IsaAssumesDPFPU = 0 IsaUseDoubleFP_accel = 0 IsaUseFloatingPoint = 1 IsaUseFloatingPointDiv = 1 IsaUseFloatingPointRecip = 1 IsaUseFloatingPointSqrt = 1 IsaUseFloatingPointRSqrt = 1 IsaUseDoubleFP = 0 IsaUseDoubleFPDiv = 0 IsaUseDoubleFPRecip = 0 IsaUseDoubleFPSqrt = 0 IsaUseDoubleFPRSqrt = 0 IsaUseVectra1 = 0 IsaUseVectra2 = 0 IsaUseVTMMU = 0 IsaUseLinuxMMU = 0 IsaUseLinuxMMUIIndexCount = 0 IsaUseLinuxMMUDIndexCount = 0 IsaUseRegionProt = 1 IsaUseRegionProtXlation = 0 IsaUseThreadPtr = 0 IsaUseBBE16 = 0 IsaUseBBENEP = 0 IsaUsePDX = 0 IsaUseFusionG = 0 IsaUseFusionJ = 0 IsaUseVision = 0 IsaUseBall = 0 IsaUseFusion = 0 IsaUseHiFi2 = 0 IsaUseHiFi3 = 1 IsaUseHiFi3Z = 0 IsaUseHiFi4 = 0 IsaUseHiFi5 = 0 IsaUseHiFiPro = 0 IsaUseHiFi2_32x24 = 0 IsaUseHiFi2_40b = 0 IsaUseConnXD2 = 0 IsaUse32bitMul = 1 IsaUse32bitMulh = 0 IsaUseIterative32bitMul = 0 IsaUse32bitDiv = 1 IsaUseBooleans = 1 IsaUseCoprocessor = 1 IsaCoprocessorCount = 2 IsaUseLeadingZeros = 1 IsaUseLoops = 1 IsaUseExtL32R = 0 IsaUseLitBase = 0 IsaUseInstPif = 1 IsaUseDataPif = 1 IsaUseExceptions = 1 IsaUseImpreciseExceptions = 0 IsaUseHalt = 0 IsaUsePrid = 1 ProcessorID = 0 HWConfigID0 = 0xC0B3DBFE HWConfigID1 = 0x2308250D IsaMisAlignedLoadExc = 1 IsaMisAlignedStoreExc = 1 IsaUseSynchronization = 1 IsaUsePerfCounters = 0 perfCounterCount = 8 IsaSysHandlesMisAlignedLoad = 0 IsaSysHandlesMisAlignedStore = 0 IsaHardwareHandlesMisAlignedLoad = 0 IsaHardwareHandlesMisAlignedStore = 0 IsaUseOCD = 1 DebugLoadStoreDDR = 1 DebugDataVAddrTrapCount = 2 DebugInstVAddrTrapCount = 2 DebugExternalInterrupt = 1 ExternalRegistersInterface = 1 ArithmeticException = 0 NumMiscRegs = 0 PIFReadDataBits = 64 PIFWriteDataBits = 64 PIFWriteResponse = 1 PIFCriticalWordFirst = 1 PIFArbitraryByteEnables = 1 PIFInbound = 1 PIFInboundBufferEntries = 2 PIFReqAttribute = 0 #PIFReqDomain: Implies if POReqDomain[1:0] signal is present. #Also implies data cache tag have 3 extra bits (Allocate/Shared/Inner). PIFReqDomain = 0 EarlyRestart = 1 LoopBufferSize = 32 MemoryErrorsEnabled = 0 DataErrorWordWidth = 0 TIEUseWideStore = 1 WideInstHoldingBuffer = 1 IPrefetchBuffers = 0 PrefetchBuffers = 16 PrefetchToL1 = 0 PrefetchCastoutLines = 1 PrefetchBlock = 0 PrefetchBlockEntries = 2 CMEDowngrades = 0 WriteBufferEntries = 16 WriteBufferBypassAddrBits = 0 HasL2CC = 0 DataCacheBytes = 65536 DataCacheWayCount = 4 DataCacheLineBytes = 128 DataCacheAccessWidth = 64 DataCacheWriteback = 1 DataCacheLock = 1 DataCacheTest = 1 DataCacheDataParity = 0 DataCacheDataECC = 0 DataCacheTagParity = 0 DataCacheTagECC = 0 DataCacheCoherence = 0 DataCacheBanks = 1 DataCacheWayDisable = 1 InstCacheBytes = 32768 InstCacheWayCount = 2 InstCacheLineBytes = 128 InstCacheAccessWidth = 64 InstCacheLock = 1 InstCacheTest = 1 InstCacheDataParity = 0 InstCacheDataECC = 0 InstCacheTagParity = 0 InstCacheTagECC = 0 InstCacheBanks = 1 InstCacheWayDisable = 1 PhysicalAddressWidth = 32 ByteEnableWidth = 8 MasterExclAccess = 1 SlaveExclAccess = 1 ExtExclMasters = 1 UnifiedRAMCount = 0 InstRAMCount = 1 InstRAM0Latency = 2 InstROMCount = 0 DataRAMCount = 2 DataRAM0Latency = 2 DataRAM1Latency = 2 DataROMCount = 0 DataPortCount = 0 MissBufferEntries = 0 StoreBufferEntries = 3 # Local memory info for ISS: # Get the count for each local memory type, and if # the count is non-zero, return a list of parameters # [ size, base_address, access_width, busy, dma, cbox, rcw, parity, ecc, enable_mask, enable_code, udma, dyn_base ] # for each instance of that memory type. # ISSEntriesPerRam = 13 ISSUnifiedRAMCount = 0 ISSDataRAMCount = 2 ISSDataRAMBanks=1 ISSDataRAMSubBanks=1 DataRAMSplitRW=0 DataRAMAttributeWidth=0 ISSDataRAMInfo = [ 0x10000 0x4ffb0000 64 1 1 0 0 0 0 0 0 0 0 0x20000 0x4ffc0000 64 1 1 0 0 0 0 0 0 0 0 ] ISSDataROMCount = 0 ISSInstRAMCount = 1 ISSInstRAMBanks=1 ISSInstRAMSubBanks=1 InstRAMSplitRW=0 InstRAMAttributeWidth=0 ISSInstRAMInfo = [ 0x10000 0x4ffe0000 64 0 1 0 0 0 0 0 0 0 0 ] ISSInstROMCount = 0 ISSDataPortCount = 0 # C-Box CBox = 0 # LX ROM Patching NumROMPatchRegs = 0 # PC PC_Width = 32 PC_UpperFixedBits = 0x00000000 # Local memory latency InstCIFCycles = 2 InstFetchWidth = 64 DataCIFCycles = 2 LoadStoreWidth = 64 LoadStoreUnitsCount = 1 AllowImemLoadStore = 1 FastL32RFromIRam = 1 ImplRegFileBuildingBlock = FlipFlop ImplResetFlops = 1 ImplAsyncReset = 1 ImplTargetSpeed = 938 ImplTargetSize = 510128 ImplTargetTechnology = 28hm ImplOperatingCondition = Worst ImplVoltageCondition = Nominal ClkGateFuncUnit = 1 ClkGateGlobal = 1 LatchesTransparent = 0 FullScan = 1 TracePort = 1 TracePortData = 0 TracePortMemBytes = 2048 TRAX = 1 PIFBridgeType = AXI PIFAsyncBusBridge = 1 BootLoader = 0 DCQueues = 0 DCPorts = 1 TIE_DC545CK = 0 TIE_DC570T = 0 TIE_MUL32 = 1 TIE_MUL32_H = 0 ConnXBBE16 = 0 ConnXBBE16_VecDiv = 0 ConnXBBE16_Rsqrt = 0 ConnXBBE16_Despread = 0 # Base vector addresses RelocatableVectors = 1 VectorBase1FromPins = 1 StaticVectorSelect = 0 StaticVectorBase0 = 0x4ffe0000 StaticVectorBase1 = 0x4ffe0700 DynVecBaseReset = 0x4ffe0400 DynVecBaseAlignBits = 10 InterruptStackBase = 0x00000000 RelocatableISB = 1 InterruptTableBase = 0x00000000 RelocatableITB = 0 # Vector offsets ResetVectorOffset = 0x00000000 MemoryExceptionVectorOffset = 0x00000000 WindowVectorsOffset = 0x00000000 KernelExceptionVectorOffset = 0x0000029c UserExceptionVectorOffset = 0x000002bc DoubleExceptionVectorOffset = 0x000002dc Level2InterruptVectorOffset = 0x0000017c Level3InterruptVectorOffset = 0x000001a0 Level4InterruptVectorOffset = 0x000001e0 Level5InterruptVectorOffset = 0x00000220 Level6InterruptVectorOffset = 0x00000260 Level7InterruptVectorOffset = 0x00000000 DebugExceptionVectorOffset = 0x00000220 NMIExceptionVectorOffset = 0x00000260 # Vectors configured Vectors = [ ResetVector KernelExceptionVector UserExceptionVector DoubleExceptionVector WindowVectors Level2InterruptVector Level3InterruptVector Level4InterruptVector DebugExceptionVector NMIExceptionVector ] VectorSizes = [ 736 28 28 28 376 28 56 56 56 56 ] StaticVectors = [ ResetVector ] # Interrupts InterruptCount = 32 InterruptLevelMax = 5 InterruptExtCount = 27 IsaUseHighLevelInterrupt = 1 ISSInterruptLevelMasks = [ 0x0 0x040c00ff 0x5830ff00 0x20c30000 0x03000000 0x00000000 ] InterruptVectorOffsets = [ 0x0 0x0 0x0000017c 0x000001a0 0x000001e0 0x00000220 ] IsNMIConfigured = 1 ISSInterruptSoftwareMask = 0x40000000 ISSInterruptExtLevelMask = 0x0003ffff ISSInterruptWriteErrMask = 0x20000000 ISSInterruptExtEdgeMask = 0x03fc0000 ISSInterruptNMIMask = 0x80000000 ISSInterruptUDmaDoneMask = 0x00000000 ISSInterruptUDmaErrMask = 0x00000000 ISSInterruptGSErrMask = 0x00000000 ISSAllInterruptMask = 0xffffffff EXCMLevel = 3 TimerCount = 2 ISSTimerInterrupts = [ 26 27 ] # Debug info for ISS IsaUseDebug = 1 DebugInterruptLevel = 5 NewExceptionArch = 1 ExternalExceptionArch = 0 ExceptionArch2 = 1 ExceptionArch3 = 0 # NX Branch Prediction Using BTB (Branch Target Buffer) BTB = [ # Configured 0 ] AXI = 1 AxiECC = 0 AceLite = 0 FullAce = 0 MPU = [ # configured 1 # num of MPU background map entries 2 # num of MPU foreground map entries which software can write using WPTLB 16 # num of MTU entries 0 # Virtual address start LSB 12 # Is micro DMA configured 0 # Is block prefetch configured 0 # MPU Background Map Entries: Each line consists of an entry of the form: #VirtStartAddr SizeInBytes AccessRights MemoryType 0x00000000 0x80000000 0x00000007 0x00000006 0x80000000 0x80000000 0x00000007 0x00000006 ] MMU = [ # configured 0 ] # iDMA information iDMA = 0 iDMANumChannels = 0 iDMATranspose = 0 iDMAPifBufDepth = 0 iDMAMaxOutstandingRows = 0 iDMAMaxOutstandingReq = 0 iDMAPifDataBits = 0 iDMAAddrWidth = 32 #GatherScatter Information: 0 for regs implies that this isn't present GatherScatter = 0 GS_ScatterRegs = 0 GS_GatherRegs = 0 GS_Unalign = 0 GS_ElementsPerCycle = 0 # Special locations used by ISS SysUartPAddr = 0xffffffff DVMagicLocVAddr = 0xdeede000 DVMagicLocPAddr = 0xdeede000 DVPrintfPAddr = 0xdeede004 DVPrintfVAddr = 0xdeede004 # Bus errors BusAddressErrors = [ 0x3ffff000 0x3ffff100 0x3ffff200 0x3ffff300 0xfffff000 0xfffff108 0xfffff210 0xfffff318 ] BusAddressErrorCount = 8 BusDataErrors = [ 0x3ffff420 0x3ffff528 0x3ffff630 0x3ffff738 0xfffff420 0xfffff528 0xfffff630 0xfffff738 ] BusDataErrorCount = 8 BusErrorPattern = 0 # System information SW_ABI = windowed SW_FloatingPointABI = 1 SW_CLibrary = xclib SW_FuSa = 0 SW_memmap_cacheattr_reset = default default-lsp = sim alwaysPIC = 0 maxPageSize = 1 enableShared = 0 sysroot = # for Linux: # default-lsp = linux # alwaysPIC = 1 # maxPageSize = 1 # enableShared = 1 # sysroot = BuildUniqueID = 557413 BuildMode = Evaluation ConfigKey0 = 0xFE46D32D ConfigKey1 = 0x1DFD2DDE # File locations # Note: Relative paths are relative to the location of the parameter file. install-prefix = ../../../../../../../prebuilts/xcc/linux-x86/xtensa/RI-2019.1-linux/XtensaTools config-prefix = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/ xtensa-tools = ../../../../../../../prebuilts/xcc/linux-x86/xtensa/RI-2019.1-linux/XtensaTools/Tools tc-tools = ../../../../../../../prebuilts/xcc/linux-x86/xtensa/RI-2019.1-linux/XtensaTools/TIE isa-base-dlls = [ ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/config/libisa-core-hw.so ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/config/libisa-core.so ] ctype-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/config/libctype.so iss-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/config/libcas-core.so iss-ref-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/config/libcas-ref-core.so fiss-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/config/libfiss-base.so fiss-ref-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/config/libfiss-ref-base.so xml-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/config/libtie-core.so xml-msem-dll= ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/config/libtie-Xtensa-msem.so xtensa-base-header = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2019.1-linux/xtensa-elf/arch/include/xtensa/config/defs.h tie-internal-module-headers = [] # TIE parameters isa-tie-dll = iss-tie-dll = iss-ref-tie-dll = xml-tie-dll = xtensa-tie-header = IsaUseWideBranches = 1 tie-checksum-0 = 0 tie-checksum-1 = 0 tie-checksum-2 = 0 tie-checksum-3 = 0 tie-includedir = tie-ident = 0 # Register information num_aregs = 64 # Pipeline stages ISSPipeBStage = 1 ISSPipeEStage = 1 ISSPipeMStage = 3 ISSPipeWStage = 4 ISSArchLicense = 0 # Initial values for ISS rams iss_irom_init_value = 0x00000000 iss_iram_init_value = 0x6c6cb6b6 iss_dram_init_value = 0x01234567 iss_drom_init_value = 0x00000000 iss_dport_init_value = 0x00000000 iss_uram_init_value = 0x00000000 # Initial values for ISS caches iss_idata_init_value = 0xa5a5a5a5 iss_itag_init_value = 0xabcdef00 iss_ddata_init_value = 0x1a2b3c4d iss_dtag_init_value = 0xbecada00 # System Ram and Rom parameters ISSSysRamBytes = 0x80000000 ISSSysRamPAddr = 0x50000000 # DV parameters DV_DynVecBaseReset = 0x4ffe0400 DV_StaticVectorBase0 = 0x4ffe0000 DV_StaticVectorBase1 = 0x4ffe0700