127 lines
7.4 KiB
C++
127 lines
7.4 KiB
C++
//===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
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//
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// The Subzero Code Generator
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines properties of ARM32 instructions in the form of x-macros.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SUBZERO_SRC_ICEINSTARM32_DEF
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#define SUBZERO_SRC_ICEINSTARM32_DEF
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#include "IceRegList.h"
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// NOTE: PC and SP are not considered isInt, to avoid register allocating.
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//
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// For the NaCl sandbox we also need to r9 (and the r8-r9 pair) for TLS, so
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// just reserve always.
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// TODO(jpp): Allow r9 to be isInt when sandboxing is turned off (native mode).
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//
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// IP is not considered isInt to reserve it as a scratch register. A scratch
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// register is useful for expanding instructions post-register allocation.
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//
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// LR is not considered isInt to avoid being allocated as a register. It is
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// technically preserved, but save/restore is handled separately, based on
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// whether or not the function MaybeLeafFunc.
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//
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// The register tables can be generated using the gen_arm32_reg_tables.py
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// script.
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#include "IceRegistersARM32.def"
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// The register tables defined in IceRegistersARM32 use the following x-macro:
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//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
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// isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
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// We also provide a combined table, so that there is a namespace where all of
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// the registers are considered and have distinct numberings. This is in
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// contrast to the above, where the "encode" is based on how the register
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// numbers will be encoded in binaries and values can overlap.
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#define REGARM32_TABLE \
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/* val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
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isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
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REGARM32_GPR_TABLE \
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REGARM32_I64PAIR_TABLE \
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REGARM32_FP32_TABLE \
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REGARM32_FP64_TABLE \
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REGARM32_VEC128_TABLE
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//#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,
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// isGPR, isInt, isFP32, isFP64, isVec128, alias_init)
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#define REGARM32_TABLE_BOUNDS \
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/* val, init */ \
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X(Reg_GPR_First, = Reg_r0) \
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X(Reg_GPR_Last, = Reg_pc) \
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X(Reg_I64PAIR_First, = Reg_r0r1) \
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X(Reg_I64PAIR_Last, = Reg_r10fp) \
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X(Reg_SREG_First, = Reg_s0) \
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X(Reg_SREG_Last, = Reg_s31) \
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X(Reg_DREG_First, = Reg_d0) \
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X(Reg_DREG_Last, = Reg_d31) \
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X(Reg_QREG_First, = Reg_q0) \
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X(Reg_QREG_Last, = Reg_q15)
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// define X(val, init)
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// Load/Store instruction width suffixes and FP/Vector element size suffixes
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// the # of offset bits allowed as part of an addressing mode (for sign or zero
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// extending load/stores).
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#define ICETYPEARM32_TABLE \
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/* tag, element type, int_width, fp_width, uvec_width, svec_width, \
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addr bits sext, zext, reg-reg addr allowed, shift allowed, */ \
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X(IceType_void, IceType_void, "" , "" , "" , "" , 0 , 0 , 0, 0) \
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X(IceType_i1, IceType_void, "b", "" , "" , "" , 8 , 12, 1, 1) \
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X(IceType_i8, IceType_void, "b", "" , "" , "" , 8 , 12, 1, 1) \
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X(IceType_i16, IceType_void, "h", "" , "" , "" , 8 , 8 , 1, 0) \
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X(IceType_i32, IceType_void, "" , "" , "" , "" , 12, 12, 1, 1) \
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X(IceType_i64, IceType_void, "d", "" , "" , "" , 12, 12, 1, 1) \
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X(IceType_f32, IceType_void, "" , ".f32", "" , "" , 8, 8 , 0, 0) \
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X(IceType_f64, IceType_void, "" , ".f64", "" , "" , 8, 8 , 0, 0) \
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X(IceType_v4i1, IceType_i32 , "" , ".i32", ".u32", ".s32", 0 , 0 , 1, 0) \
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X(IceType_v8i1, IceType_i16 , "" , ".i16", ".u16", ".s16", 0 , 0 , 1, 0) \
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X(IceType_v16i1, IceType_i8 , "" , ".i8" , ".u8" , ".s8" , 0 , 0 , 1, 0) \
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X(IceType_v16i8, IceType_i8 , "" , ".i8" , ".u8" , ".s8" , 0 , 0 , 1, 0) \
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X(IceType_v8i16, IceType_i16 , "" , ".i16", ".u16", ".s16", 0 , 0 , 1, 0) \
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X(IceType_v4i32, IceType_i32 , "" , ".i32", ".u32", ".s32", 0 , 0 , 1, 0) \
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X(IceType_v4f32, IceType_f32 , "" , ".f32", ".f32", ".f32", 0 , 0 , 1, 0)
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//#define X(tag, elementty, int_width, fp_width, uvec_width, svec_width, sbits,
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// ubits, rraddr, shaddr)
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// Shifter types for Data-processing operands as defined in section A5.1.2.
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#define ICEINSTARM32SHIFT_TABLE \
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/* enum value, emit */ \
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X(LSL, "lsl") \
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X(LSR, "lsr") \
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X(ASR, "asr") \
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X(ROR, "ror") \
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X(RRX, "rrx")
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//#define X(tag, emit)
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// Attributes for the condition code 4-bit encoding (that is independent of the
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// APSR's NZCV fields). For example, EQ is 0, but corresponds to Z = 1, and NE
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// is 1, but corresponds to Z = 0.
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#define ICEINSTARM32COND_TABLE \
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/* enum value, encoding, opposite, emit */ \
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X(EQ, 0, NE, "eq") /* equal */ \
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X(NE, 1, EQ, "ne") /* not equal */ \
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X(CS, 2, CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */ \
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X(CC, 3, CS, "cc") /* carry clear/unsigned (AKA lo: lower) */ \
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X(MI, 4, PL, "mi") /* minus/negative */ \
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X(PL, 5, MI, "pl") /* plus/positive or zero */ \
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X(VS, 6, VC, "vs") /* overflow (float unordered) */ \
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X(VC, 7, VS, "vc") /* no overflow (float not unordered) */ \
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X(HI, 8, LS, "hi") /* unsigned higher */ \
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X(LS, 9, HI, "ls") /* unsigned lower or same */ \
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X(GE, 10, LT, "ge") /* signed greater than or equal */ \
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X(LT, 11, GE, "lt") /* signed less than */ \
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X(GT, 12, LE, "gt") /* signed greater than */ \
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X(LE, 13, GT, "le") /* signed less than or equal */ \
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X(AL, 14, kNone, "") /* always (unconditional) */ \
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X(kNone, 15, kNone, "??") /* special condition / none */
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//#define X(tag, encode, opp, emit)
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#endif // SUBZERO_SRC_ICEINSTARM32_DEF
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