504 lines
13 KiB
Plaintext
504 lines
13 KiB
Plaintext
# Xtensa default parameter values
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# Customer ID=7578; Build=0x7aa7f; Copyright (c) 2004-2018 Tensilica Inc. ALL RIGHTS RESERVED.
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# These coded instructions, statements, and computer programs are the
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# copyrighted works and confidential proprietary information of Tensilica Inc.
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# They may not be modified, copied, reproduced, distributed, or disclosed to
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# third parties in any manner, medium, or form, in whole or in part, without
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# the prior written consent of Tensilica Inc.
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# WARNING: This file has been automatically generated with values that are
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# specific to a particular Xtensa processor configuration. Changing values
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# here will likely result in an inconsistent system. Do not edit!
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# Version information for software tools and target hardware
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SWToolsRelease = RI-2018.0
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SWToolsVername = 14.00
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SWToolsVersion = 1400000
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HWMicroArchLatest = 270006
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HWMicroArchEarliest = 270006
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TargetHWVersion = LX7.0.6
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ConfigName = Xm_hifi3_prod_v2
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IsPreconfiguredCore = 0
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uarchName = Barcelona
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HasVectorPipe = 0
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HasXNNE = 0
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# Preconfigured ISA parameters
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IsaIsBigEndian = 0
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IsaMaxInstructionSize = 8
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IsaUseWindowedRegisters = 1
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IsaUseDensityInstruction = 1
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IsaNumContexts = 1
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IsaUseL32R = 1
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IsaUseConst16 = 0
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IsaUseAbs = 1
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IsaUseAddx = 1
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IsaUsePredictedBranches = 0
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IsaUseNormShiftAmount = 1
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IsaUseMinMax = 1
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IsaUseSignExtend = 1
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IsaUseDepBits = 0
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IsaUseClamps = 1
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IsaUseMAC16 = 0
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IsaUseMul16 = 1
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MUL32ImplementsMul16 = 1
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MAC16ImplementsMul16 = 0
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IsaUseS32C1I = 0
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IsaUseTAPMaster = 0
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IsaUseVectorFPU2005 = 0
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IsaAssumesSPFPU = 1
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IsaAssumesDPFPU = 0
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IsaUseDoubleFP_accel = 0
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IsaUseFloatingPoint = 1
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IsaUseFloatingPointDiv = 1
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IsaUseFloatingPointRecip = 1
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IsaUseFloatingPointSqrt = 1
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IsaUseFloatingPointRSqrt = 1
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IsaUseDoubleFP = 0
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IsaUseDoubleFPDiv = 0
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IsaUseDoubleFPRecip = 0
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IsaUseDoubleFPSqrt = 0
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IsaUseDoubleFPRSqrt = 0
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IsaUseVectra1 = 0
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IsaUseVectra2 = 0
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IsaUseVTMMU = 0
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IsaUseLinuxMMU = 0
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IsaUseLinuxMMUIIndexCount = 0
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IsaUseLinuxMMUDIndexCount = 0
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IsaUseRegionProt = 1
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IsaUseRegionProtXlation = 0
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IsaUseThreadPtr = 0
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IsaUseBBE16 = 0
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IsaUseBBENEP = 0
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IsaUsePDX = 0
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IsaUseFusionG = 0
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IsaUseFusionJ = 0
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IsaUseVision = 0
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IsaUseBall = 0
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IsaUseFusion = 0
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IsaUseHiFi2 = 0
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IsaUseHiFi3 = 1
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IsaUseHiFi3Z = 0
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IsaUseHiFi4 = 0
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IsaUseHiFi5 = 0
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IsaUseHiFiPro = 0
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IsaUseHiFi2_32x24 = 0
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IsaUseHiFi2_40b = 0
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IsaUseConnXD2 = 0
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IsaUse32bitMul = 1
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IsaUse32bitMulh = 0
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IsaUseIterative32bitMul = 0
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IsaUse32bitDiv = 1
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IsaUseBooleans = 1
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IsaUseCoprocessor = 1
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IsaCoprocessorCount = 2
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IsaUseLeadingZeros = 1
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IsaUseLoops = 1
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IsaUseExtL32R = 0
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IsaUseLitBase = 0
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IsaUseInstPif = 1
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IsaUseDataPif = 1
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IsaUseExceptions = 1
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IsaUseImpreciseExceptions = 0
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IsaUseHalt = 0
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IsaUsePrid = 1
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ProcessorID = 0
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HWConfigID0 = 0xC0B3DBFE
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HWConfigID1 = 0x218719DA
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IsaMisAlignedLoadExc = 1
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IsaMisAlignedStoreExc = 1
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IsaUseSynchronization = 1
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IsaUsePerfCounters = 0
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perfCounterCount = 8
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IsaSysHandlesMisAlignedLoad = 0
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IsaSysHandlesMisAlignedStore = 0
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IsaHardwareHandlesMisAlignedLoad = 0
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IsaHardwareHandlesMisAlignedStore = 0
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IsaUseOCD = 1
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DebugLoadStoreDDR = 1
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DebugDataVAddrTrapCount = 2
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DebugInstVAddrTrapCount = 2
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DebugExternalInterrupt = 1
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ExternalRegistersInterface = 1
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ArithmeticException = 0
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NumMiscRegs = 0
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PIFReadDataBits = 64
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PIFWriteDataBits = 64
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PIFWriteResponse = 1
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PIFCriticalWordFirst = 1
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PIFArbitraryByteEnables = 1
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PIFInbound = 1
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PIFInboundBufferEntries = 2
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PIFReqAttribute = 0
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#PIFReqDomain: Implies if POReqDomain[1:0] signal is present.
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#Also implies data cache tag have 3 extra bits (Allocate/Shared/Inner).
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PIFReqDomain = 0
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EarlyRestart = 1
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LoopBufferSize = 32
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MemoryErrorsEnabled = 0
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DataErrorWordWidth = 0
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TIEUseWideStore = 1
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WideInstHoldingBuffer = 1
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IPrefetchBuffers = 0
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PrefetchBuffers = 16
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PrefetchToL1 = 0
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PrefetchCastoutLines = 1
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PrefetchBlock = 0
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PrefetchBlockEntries = 2
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CMEDowngrades = 0
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WriteBufferEntries = 16
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WriteBufferBypassAddrBits = 0
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HasL2CC = 0
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DataCacheBytes = 65536
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DataCacheWayCount = 4
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DataCacheLineBytes = 128
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DataCacheAccessWidth = 64
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DataCacheWriteback = 1
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DataCacheLock = 1
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DataCacheTest = 1
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DataCacheDataParity = 0
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DataCacheDataECC = 0
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DataCacheTagParity = 0
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DataCacheTagECC = 0
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DataCacheCoherence = 0
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DataCacheBanks = 1
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DataCacheWayDisable = 1
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InstCacheBytes = 32768
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InstCacheWayCount = 2
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InstCacheLineBytes = 128
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InstCacheAccessWidth = 64
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InstCacheLock = 1
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InstCacheTest = 1
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InstCacheDataParity = 0
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InstCacheDataECC = 0
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InstCacheTagParity = 0
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InstCacheTagECC = 0
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InstCacheBanks = 1
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InstCacheWayDisable = 1
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PhysicalAddressWidth = 32
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ByteEnableWidth = 8
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MasterExclAccess = 1
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SlaveExclAccess = 1
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ExtExclMasters = 1
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UnifiedRAMCount = 0
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InstRAMCount = 1
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InstRAM0Latency = 2
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InstROMCount = 0
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DataRAMCount = 2
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DataRAM0Latency = 2
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DataRAM1Latency = 2
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DataROMCount = 0
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DataPortCount = 0
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StoreBufferEntries = 3
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# Local memory info for ISS:
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# Get the count for each local memory type, and if
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# the count is non-zero, return a list of parameters
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# [ size, base_address, access_width, busy, dma, cbox, rcw, parity, ecc, enable_mask, enable_code, udma, dyn_base ]
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# for each instance of that memory type.
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#
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ISSEntriesPerRam = 13
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ISSUnifiedRAMCount = 0
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ISSDataRAMCount = 2
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ISSDataRAMBanks=1
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ISSDataRAMSubBanks=1
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DataRAMSplitRW=0
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DataRAMAttributeWidth=0
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ISSDataRAMInfo = [ 0x10000 0x4ffb0000 64 1 1 0 0 0 0 0 0 0 0 0x20000 0x4ffc0000 64 1 1 0 0 0 0 0 0 0 0 ]
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ISSDataROMCount = 0
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ISSInstRAMCount = 1
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ISSInstRAMBanks=1
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ISSInstRAMSubBanks=1
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InstRAMSplitRW=0
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InstRAMAttributeWidth=0
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ISSInstRAMInfo = [ 0x10000 0x4ffe0000 64 0 1 0 0 0 0 0 0 0 0 ]
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ISSInstROMCount = 0
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ISSDataPortCount = 0
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# C-Box
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CBox = 0
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# PC
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PC_Width = 32
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PC_UpperFixedBits = 0x00000000
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# Local memory latency
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InstCIFCycles = 2
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InstFetchWidth = 64
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DataCIFCycles = 2
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LoadStoreWidth = 64
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LoadStoreUnitsCount = 1
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AllowImemLoadStore = 1
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FastL32RFromIRam = 1
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ImplRegFileBuildingBlock = FlipFlop
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ImplResetFlops = 1
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ImplAsyncReset = 1
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ImplTargetSpeed = 938
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ImplTargetSize = 510128
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ImplTargetTechnology = 28hm
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ImplOperatingCondition = Worst
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ImplVoltageCondition = Nominal
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ClkGateFuncUnit = 1
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ClkGateGlobal = 1
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LatchesTransparent = 0
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FullScan = 1
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TracePort = 1
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TracePortData = 0
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TracePortMemBytes = 2048
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TRAX = 1
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PIFBridgeType = AXI
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PIFAsyncBusBridge = 1
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BootLoader = 0
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DCQueues = 0
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DCPorts = 1
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TIE_DC545CK = 0
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TIE_DC570T = 0
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TIE_MUL32 = 1
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TIE_MUL32_H = 0
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ConnXBBE16 = 0
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ConnXBBE16_VecDiv = 0
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ConnXBBE16_Rsqrt = 0
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ConnXBBE16_Despread = 0
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# Base vector addresses
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RelocatableVectors = 1
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VectorBase1FromPins = 1
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StaticVectorSelect = 0
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StaticVectorBase0 = 0x4ffe0000
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StaticVectorBase1 = 0x4ffe0700
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DynVecBaseReset = 0x4ffe0400
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DynVecBaseAlignBits = 10
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InterruptStackBase = 0x00000000
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RelocatableISB = 1
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InterruptTableBase = 0x00000000
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RelocatableITB = 0
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# Vector offsets
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ResetVectorOffset = 0x00000000
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MemoryExceptionVectorOffset = 0x00000000
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WindowVectorsOffset = 0x00000000
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KernelExceptionVectorOffset = 0x0000029c
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UserExceptionVectorOffset = 0x000002bc
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DoubleExceptionVectorOffset = 0x000002dc
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Level2InterruptVectorOffset = 0x0000017c
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Level3InterruptVectorOffset = 0x000001a0
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Level4InterruptVectorOffset = 0x000001e0
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Level5InterruptVectorOffset = 0x00000220
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Level6InterruptVectorOffset = 0x00000260
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Level7InterruptVectorOffset = 0x00000000
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DebugExceptionVectorOffset = 0x00000220
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NMIExceptionVectorOffset = 0x00000260
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# Vectors configured
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Vectors = [ ResetVector KernelExceptionVector UserExceptionVector DoubleExceptionVector WindowVectors Level2InterruptVector Level3InterruptVector Level4InterruptVector DebugExceptionVector NMIExceptionVector ]
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VectorSizes = [ 736 28 28 28 376 28 56 56 56 56 ]
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StaticVectors = [ ResetVector ]
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# Interrupts
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InterruptCount = 32
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InterruptLevelMax = 5
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InterruptExtCount = 27
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IsaUseHighLevelInterrupt = 1
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ISSInterruptLevelMasks = [ 0x0 0x040c00ff 0x5830ff00 0x20c30000 0x03000000 0x00000000 ]
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InterruptVectorOffsets = [ 0x0 0x0 0x0000017c 0x000001a0 0x000001e0 0x00000220 ]
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IsNMIConfigured = 1
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ISSInterruptSoftwareMask = 0x40000000
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ISSInterruptExtLevelMask = 0x0003ffff
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ISSInterruptWriteErrMask = 0x20000000
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ISSInterruptExtEdgeMask = 0x03fc0000
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ISSInterruptNMIMask = 0x80000000
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ISSInterruptUDmaDoneMask = 0x00000000
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ISSInterruptUDmaErrMask = 0x00000000
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ISSInterruptGSErrMask = 0x00000000
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ISSAllInterruptMask = 0xffffffff
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EXCMLevel = 3
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TimerCount = 2
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ISSTimerInterrupts = [ 26 27 ]
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# Debug info for ISS
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IsaUseDebug = 1
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DebugInterruptLevel = 5
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NewExceptionArch = 1
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ExternalExceptionArch = 0
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ExceptionArch2 = 1
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ExceptionArch3 = 0
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# NX Branch Prediction Using BTB (Branch Target Buffer)
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BTB = [
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# Configured
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0
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]
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AXI = 1
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AxiECC = 0
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AceLite = 0
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FullAce = 0
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MPU = [
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# configured
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1
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# num of MPU background map entries
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2
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# num of MPU foreground map entries which software can write using WPTLB
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16
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# num of MTU entries
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0
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# Virtual address start LSB
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12
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# Is micro DMA configured
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0
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# Is block prefetch configured
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0
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# MPU Background Map Entries: Each line consists of an entry of the form:
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#VirtStartAddr SizeInBytes AccessRights MemoryType
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0x00000000 0x80000000 0x00000007 0x00000006
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0x80000000 0x80000000 0x00000007 0x00000006
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]
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MMU = [
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# configured
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0
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]
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# iDMA information
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iDMA = 0
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iDMANumChannels = 0
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iDMATranspose = 0
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iDMAPifBufDepth = 0
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iDMAMaxOutstandingRows = 0
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iDMAPifDataBits = 0
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iDMAAddrWidth = 32
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#GatherScatter Information: 0 for regs implies that this isn't present
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GatherScatter = 0
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#FIXME: Need to add in gather()/scatter() in future?
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GS_ScatterRegs = 0
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GS_GatherRegs = 0
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GS_Unalign = 0
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GS_ElementsPerCycle = 0
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# Special locations used by ISS
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SysUartPAddr = 0xffffffff
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DVMagicLocVAddr = 0xdeede000
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DVMagicLocPAddr = 0xdeede000
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DVPrintfPAddr = 0xdeede004
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DVPrintfVAddr = 0xdeede004
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# Bus errors
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BusAddressErrors = [ 0x3ffff000 0x3ffff100 0x3ffff200 0x3ffff300 0xfffff000 0xfffff108 0xfffff210 0xfffff318 ]
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BusAddressErrorCount = 8
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BusDataErrors = [ 0x3ffff420 0x3ffff528 0x3ffff630 0x3ffff738 0xfffff420 0xfffff528 0xfffff630 0xfffff738 ]
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BusDataErrorCount = 8
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BusErrorPattern = 0
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# System information
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SW_ABI = windowed
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SW_FloatingPointABI = 1
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SW_CLibrary = xclib
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SW_FuSa = 0
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SW_memmap_cacheattr_reset = default
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default-lsp = sim
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alwaysPIC = 0
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maxPageSize = 1
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enableShared = 0
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sysroot =
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# for Linux:
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# default-lsp = linux
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# alwaysPIC = 1
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# maxPageSize = 1
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# enableShared = 1
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# sysroot = <sysroot directory>
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BuildUniqueID = 502399
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BuildMode = Evaluation
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ConfigKey0 = 0x972567AA
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ConfigKey1 = 0x7611A58E
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# File locations
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# Note: Relative paths are relative to the location of the parameter file.
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install-prefix = ../../../../../../../prebuilts/xcc/linux-x86/xtensa/RI-2018.0-linux/XtensaTools
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config-prefix = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux
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xtensa-tools = ../../../../../../../prebuilts/xcc/linux-x86/xtensa/RI-2018.0-linux/XtensaTools/Tools
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tc-tools = ../../../../../../../prebuilts/xcc/linux-x86/xtensa/RI-2018.0-linux/XtensaTools/TIE
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isa-base-dlls = [
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../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/config/libisa-core-hw.so
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../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/config/libisa-core.so
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]
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ctype-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/config/libctype.so
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iss-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/config/libcas-core.so
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iss-ref-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/config/libcas-ref-core.so
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fiss-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/config/libfiss-base.so
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fiss-ref-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/config/libfiss-ref-base.so
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xml-base-dll = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/config/libtie-core.so
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xml-msem-dll= ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/config/libtie-Xtensa-msem.so
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xtensa-base-header = ../../../../../../../vendor/mediatek/proprietary/tinysys/adsp/license/prebuilt/HIFI3/3rd_party/hwcfg/RI-2018.0-linux/xtensa-elf/arch/include/xtensa/config/defs.h
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tie-internal-module-headers = []
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# TIE parameters
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isa-tie-dll =
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iss-tie-dll =
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iss-ref-tie-dll =
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xml-tie-dll =
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xtensa-tie-header =
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IsaUseWideBranches = 1
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tie-checksum-0 = 0
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tie-checksum-1 = 0
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tie-checksum-2 = 0
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tie-checksum-3 = 0
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tie-includedir =
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tie-ident = 0
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# Register information
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num_aregs = 64
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# Pipeline stages
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ISSPipeBStage = 1
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ISSPipeEStage = 1
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ISSPipeMStage = 3
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ISSPipeWStage = 4
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ISSArchLicense = 0
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# Initial values for ISS rams
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iss_irom_init_value = 0x00000000
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iss_iram_init_value = 0x6c6cb6b6
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iss_dram_init_value = 0x01234567
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iss_drom_init_value = 0x00000000
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iss_dport_init_value = 0x00000000
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iss_uram_init_value = 0x00000000
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# Initial values for ISS caches
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iss_idata_init_value = 0xa5a5a5a5
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iss_itag_init_value = 0xabcdef00
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iss_ddata_init_value = 0x1a2b3c4d
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iss_dtag_init_value = 0xbecada00
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# System Ram and Rom parameters
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ISSSysRamBytes = 0x80000000
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ISSSysRamPAddr = 0x50000000
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# DV parameters
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DV_DynVecBaseReset = 0x4ffe0400
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DV_StaticVectorBase0 = 0x4ffe0000
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DV_StaticVectorBase1 = 0x4ffe0700
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