480 lines
22 KiB
Plaintext
480 lines
22 KiB
Plaintext
MSGID: FUSION_AR_OPERAND_LIMIT
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AR operand count limit (%d) exceeded.
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MSGID: FUSION_CHECKSUM
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The data-flow graph for the region has changed.
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MSGID: FUSION_CLOSURE
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Additional nodes need to be included.
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MSGID: FUSION_DEAD_COPY
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An unused copy node can't be included in the fusion.
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MSGID: FUSION_IMPOSSIBLE
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Cannot create a valid fusion starting from the selected node(s).
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MSGID: FUSION_IN_OPERAND_LIMIT
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Input operand count limit (%d) exceeded.
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MSGID: FUSION_INTERFACE_LATENCY
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Interface %s must be defined in stage %d but the logic latency is %d cycles.
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MSGID: FUSION_INVALID
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The manual fusion is invalid.
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MSGID: FUSION_LATENCY
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Estimated fusion latency (%d cycles) exceeds the limit (%d cycles).
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MSGID: FUSION_MATCH
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The compiler is unable to apply the generated fusion.
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MSGID: FUSION_MULTI_INLINE
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Multiple fused operations need to be inlined.
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MSGID: FUSION_MULTI_INTERFACE_DEF
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Multiple definitions of interface %s required.
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MSGID: FUSION_MULTI_INTERFACE_USE
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Multiple uses of interface %s required.
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MSGID: FUSION_MULTI_MEMORY
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Unable to combine multiple memory operations.
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MSGID: FUSION_MULTI_STATE_DEF
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Multiple definitions of state %s required.
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MSGID: FUSION_MULTI_STATE_USE
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Multiple uses of state %s required.
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MSGID: FUSION_NODE_BAD
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Unsupported node.
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MSGID: FUSION_NODE_BRANCH
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Branches can't be fused.
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MSGID: FUSION_NODE_CORE_STATE
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Operation uses a core state.
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MSGID: FUSION_NODE_EXCEPTION
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Operation raises an exception.
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MSGID: FUSION_NODE_FUSIBLE
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The node can be included in fusions.
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MSGID: FUSION_NODE_IMMEDIATE
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Operation contains an unsupported immediate operand.
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MSGID: FUSION_NODE_NO_GENERATE
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Operation is not extended or replaced.
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MSGID: FUSION_NODE_NO_REFERENCE
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Operation has no reference.
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MSGID: FUSION_NODE_MEMORY
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Memory operations can't be fused (the 'memory_fusions' option is turned off).
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MSGID: FUSION_NODE_OPERAND
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Operand nodes exist for visualization purposes only.
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MSGID: FUSION_NODE_PROTO
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Non-instruction protos can't be fused.
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MSGID: FUSION_NODE_SHARED_FUNC
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Unable to fuse operations that call shared functions.
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MSGID: FUSION_NODE_TIECOMP_DISALLOWED
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Operation is not allowed in a TIEcomp construct.
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MSGID: FUSION_NODE_VECTOR_MEMORY
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Vector memory operations can't be fused.
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MSGID: FUSION_NOT_FOUND
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Unable to find the fusion region.
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MSGID: FUSION_OP_COUNT_THRESHOLD
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Fused operations count below threshold (%d).
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MSGID: FUSION_OPERAND_LIMIT
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Operand count limit (%d) exceeded.
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MSGID: FUSION_OUT_OPERAND_LIMIT
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Output operand count limit (%d) exceeded.
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MSGID: FUSION_READ_REGPORT_LIMIT
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The regfile %s read port count limit (%d) exceeded.
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MSGID: FUSION_REGFILE_LIMIT
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The regfile for type %s exceeds the allowed or supported resource limits.
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MSGID: FUSION_VALID
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The manual fusion is valid.
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MSGID: FUSION_WRITE_REGPORT_LIMIT
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The regfile %s write port count limit (%d) exceeded.
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MSGID: REGION_INDEXED_OP_MEMORY_WIDTH
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Vectorization by %d requires a PIF width >= %d bits to support indexed memory operations.
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LONGDESC
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The region requires an indexed memory operation with width that exceeds the current PIF width. You can increase the PIF width by editing the processor configuration.
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MSGID: REGION_OP_MEMORY_WIDTH
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Vectorization by %d requires that the PIF width be >= %d bits.
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LONGDESC
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The region requires a memory operation with width that exceeds the current PIF width. You can increase the PIF width by editing the processor configuration.
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MSGID: REGION_OP_STORE_DISABLE
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Vectorization by %d requires arbitrary byte enables to support unaligned stores.
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LONGDESC
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The region requires unaligned store operations. These operations require arbitrary byte enables. You can add arbitrary byte enables by editing the processor configuration.
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MSGID: REGION_UNALIGNED_LOAD
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Vectorization by %d requires unaligned loads.
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LONGDESC
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Vectorization of this region will generate unaligned load operations. The extra hardware and opcode space required by these operations may be avoided by using '#pragma aligned', or by accessing global or local arrays directly.
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MSGID: REGION_UNALIGNED_STORE
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Vectorization by %d requires unaligned stores.
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LONGDESC
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Vectorization of this region will generate unaligned store operations. The extra hardware and opcode space required by these operations may be avoided by using '#pragma aligned', or by accessing global or local arrays directly.
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MSGID: SIMD_ACCESS_GAPS
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Gaps in memory access sequence (base '%s').
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LONGDESC
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The compiler is unable to vectorize array accesses with gaps. A loop can only be vectorized if it can be transformed so that it accesses sequential array elements on each loop iteration. The example loop below can't be vectorized because it accesses only the even elements of the arrays.
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for (i = 0; i < N; i += 2)
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a[i] = b[i] + c[i];
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MSGID: SIMD_ANALYSIS_OP
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Unable to analyze %s.
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LONGDESC
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The current version of the compiler does not support vectorization of this type of operation.
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MSGID: SIMD_ANALYSIS_REDUCTION
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Unable to analyze reduction of %s.
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LONGDESC
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The current version of the compiler does not support this type of vector reduction.
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MSGID: SIMD_ARRAY_ALIAS
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Array base '%s' is aliased with array base '%s' at line %d.
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LONGDESC
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The compiler conservatively assumes that the two array bases may point to the same memory location. In certain cases, e.g. direct references to global arrays, the concurrent or simd pragma, the __restrict qualifier, or the -OPT:alias=restrict option can be used to prevent aliasing and allow vectorization.
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MSGID: SIMD_ARRAY_DEPENDENCE
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Dependence between array access '%s' and array access '%s' at line %d.
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LONGDESC
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Vectorization requires that loop iterations can be executed in parallel. This message indicates that data dependences make parallel execution illegal. The example loop below can't be vectorized because the data computed in each iteration (i) depends on the data computed in the previous iteration (i-1).
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for (i = 1; i < N; i++)
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b[i] = b[i - 1] + a[i];
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MSGID: SIMD_BAD_ACCESS
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%s is not a simple array access.
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LONGDESC
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The compiler is unable to vectorize loops that contain complex indirect memory accesses. The example loops below can't be vectorized because XPRES is unable to determine that sequential elements of array 'b' are accessed on each iteration of the loop.
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for (i = 1; i < N; i++)
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a[i] = b[c[i]];
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for (i = 1; i < N; i++)
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a[i] = b[i % 4];
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MSGID: SIMD_BAD_ACCESS_STRIDE
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Bad array access stride (base '%s').
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LONGDESC
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The compiler is unable to vectorize array accesses with non-unit strides. A loop can only be vectorized if it can be transformed so that it accesses sequential array elements on each loop iteration. Loop 'i' below can't be vectorized because it doesn't access sequential elements from array 'b'. Loop 'j' can't be vectorized because it doesn't access sequential elements from array 'a'.
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for (i = 0; i < N; i++)
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for (j = 0; j < N; j++)
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a[j][i] = b[i][j];
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MSGID: SIMD_BAD_CALL
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Loop contains call to function '%s'.
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LONGDESC
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The compiler is unable to vectorize loops that contain function calls.
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MSGID: SIMD_BAD_DGRAPH
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Dependence analysis overflow -- too many array accesses.
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LONGDESC
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The compiler is unable to vectorize loops because the function is too large and/or the function contains too many array accesses. This error can be avoided by splitting the function into several smaller functions.
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MSGID: SIMD_BAD_LOOP
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Non-array indirect memory accesses, calls or unhandled control-flow.
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LONGDESC
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Loops with non-array indirect memory accesses, function calls, use of non-vectorizable TIE intrinsics or unsupported control-flow such as GOTO statements and loops with non-computable trip counts can't be vectorized.
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MSGID: SIMD_BAD_LOOP_UPPER_BOUND
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Unsupported loop upper bound expression.
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LONGDESC
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The compiler tries to standardize all for-loop upper bounds to 'index <= bound' expressions. Vectorization is not possible if the compiler is unable to perform this transformation.
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MSGID: SIMD_BAD_TIE_OP
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Non-vectorizable input TIE instruction '%s'.
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LONGDESC
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The compiler is unable to vectorize loops containing TIE instructions that access states, memory or queues.
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MSGID: SIMD_BOOLEAN
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Boolean coprocessor required.
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LONGDESC
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Vector if-conversion requires the boolean coprocessor option. You can enable the boolean coprocessor option by editing the processor configuration.
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MSGID: SIMD_DATA_DEPENDENCE
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Data dependences prevent vectorization.
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LONGDESC
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Vectorization requires that loop iterations can be executed in parallel. This message indicates that data dependences make parallel execution illegal. The example loop below can't be vectorized because the data computed in each iteration (i) depends on the data computed in the previous iteration (i-1).
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for (i = 1; i < N; i++)
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b[i] = b[i - 1] + a[i];
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MSGID: SIMD_DISABLED
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To enable vectorization use -O3 -LNO:simd.
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LONGDESC
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The verbosity option was set (-LNO:simd_v) without setting the appropriate optimization options (-O3 -LNO:simd).
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MSGID: SIMD_IF_DIFF_VL
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Mismatched if-statement vector lengths.
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LONGDESC
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Vectorization of if-statements is performed through a code transformation called 'if-conversion'. If-coversion is implemented by executing the expressions in the then and the else branches together and merging the results based on the if-condition. For example:
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Original code:
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if (a > b)
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c = a - b;
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else
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c = a + b;
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If-converted code:
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t1 = a - b;
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t2 = a + b;
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c = (a > b) ? t1 : t2;
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MSGID: SIMD_IF_HAS_LOOP
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Loop in if-statement.
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LONGDESC
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The current version of the compiler is unable to apply if-conversion in the presence of loops in the then or else branch of an if-statement.
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Vectorization of if-statements is performed through a code transformation called 'if-conversion'. If-coversion is implemented by executing the expressions in the then and the else branches together and merging the results based on the if-condition. For example:
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Original code:
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if (a > b)
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c = a - b;
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else
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c = a + b;
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If-converted code:
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t1 = a - b;
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t2 = a + b;
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c = (a > b) ? t1 : t2;
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The following is an example of a loop contained within the then branch of an if-statement. In this example, the 'j' loop can not be vectorized because it contains an if-statement with a loop in the then branch. The compiler can vectorize a loop that is within the then or else branch, so it may be possible to vectorize the 'i' loop (assuming other vectorization requirements are satisfied).
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for (j = 0; j < 16; j++) {
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if (a < b)
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for (i = 0; i < 16; i++) x[i] = y[i];
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...
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}
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MSGID: SIMD_IF_UNSAFE_ACCESS
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Unsafe accesses in if-statement.
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LONGDESC
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Vectorization of if-statements is performed through a code transformation called 'if-conversion'. If-coversion is implemented by executing the expressions in the then and the else branches together and merging the results based on the if-condition. For example:
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Original code:
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if (a > b)
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c = a - b;
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else
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c = a + b;
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If-converted code:
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t1 = a - b;
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t2 = a + b;
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c = (a > b) ? t1 : t2;
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Since if-conversion executes the then- and the else- branches of the if-statement before testing the if-condition, safe transformation requires that each operation or memory access is present on both branches of the if-statement. If the operation or access is not on both sides of the if-statement but it can be speculated safely, the -TENV:X=? or the -LNO:simd_agg_if_conv compiler option, or the simd_if_convert pragma can be used to force transformation.
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For example, the following code cannot be vectorized because 'a' is only written when the condition is true.
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for (i = 0; i < n; i++)
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if (b[i] < c[i]) a[i] = b[i]
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By adding the simd_if_convert pragma to the loop as shown below, we inform the compiler that it is safe to write to 'a' on every iteration (that is, it is safe for the compiler to treat the code as if it were written a[i] = (b[i] < c[i]) ? b[i] : a[i]).
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#pragma simd_if_convert
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for (i = 0; i < n; i++)
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if (b[i] < c[i]) a[i] = b[i]
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MSGID: SIMD_LOOP_BEGIN
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Vectorization analysis begins with a new loop.
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LONGDESC
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Before vectorizing a loop, the compiler performs complete operator and data dependence analysis on the loop to check the legality of the transformation.
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MSGID: SIMD_LOOP_COST_MODEL
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Vectorization of this loop is not beneficial.
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LONGDESC
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The compiler may choose not to vectorize a loop because the estimated performance of the vectorized loop is worse than the original, non-vector loop performance or than the performance achieved by vectorizing another loop in the same loop nest.
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MSGID: SIMD_LOOP_NON_VECTORIZABLE
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Loop is not vectorizable.
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LONGDESC
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The compiler is unable to vectorize this loop.
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MSGID: SIMD_LOOP_PRAGMA_NOSIMD
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Loop has 'pragma no_simd' directive.
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LONGDESC
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This loop has a 'pragma no_simd' that disables vectorization.
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MSGID: SIMD_LOOP_VECTORIZATION_SKIP
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Loop vectorization is skipped for loop %d from -LNO:simd_skip
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LONGDESC
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The compiler skips to vectorize this loop from option -LNO:simd_skip.
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MSGID: SIMD_LOOP_VECTORIZATION_TRY
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Trying loop vectorization by %d
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LONGDESC
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The compiler is trying vectorization.
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MSGID: SIMD_LOOP_VECTORIZATION_RETRY
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Retrying loop vectorization by %d (%s)
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LONGDESC
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The compiler is retrying vectorization with a different strategy.
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MSGID: SIMD_LOOP_STEP
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Non-unit loop step %d.
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LONGDESC
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Vectorization is supported only if the for-loop step is equal to one.
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MSGID: SIMD_LOOP_TOO_DEEP
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Loop nest is too deep.
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LONGDESC
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Vectorization analysis is not performed on outer loops that contain too deeply nested inner loops.
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MSGID: SIMD_LOOP_VECTORIZABLE
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Loop is vectorizable.
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LONGDESC
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Although the operator and data dependence analysis determined that the loop can be vectorized, the required SIMD TIE may not necessarily be generated. The loop may not be important enough or the current version of the XPRES compiler may be unable to generate the necessary vector semantics.
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MSGID: SIMD_LOOP_VECTORIZED
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Loop %d is vectorized by %d.
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MSGID: SIMD_NEGATIVE_ACCESS_STRIDE
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Negative memory access stride (base '%s').
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LONGDESC
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The compiler is unable to vectorize array accesses with negative stride. For example, the loop below can't be vectorized because of array 'b' is accessed with a negative stride.
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for (i = 0; i < N; i ++)
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a[i] = b[N - i - 1];
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MSGID: SIMD_NO_COMMON_VL
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No common vectorization length is available.
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MSGID: SIMD_NO_COND_MOVE
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No conditional move instruction for vector type %s.
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LONGDESC
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Vectorization of if-statements is performed through a code transformation called 'if-conversion'. If-coversion is implemented by executing the expressions in the then and the else branches together and merging the results based on the if-condition. For example:
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Original code:
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if (a > b)
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c = a - b;
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else
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c = a + b;
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If-converted code:
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t1 = a - b;
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t2 = a + b;
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c = (a > b) ? t1 : t2;
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Vector if-conversion requires a conditional move instruction for merging a result of the specified vector type but no such instruction is available in the current processor configuration.
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MSGID: SIMD_NO_COPROC
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Vectorization turned off by -mno-use-coproc
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LONGDESC
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Vectorization may generate co-processor instructions which is disabled with -mno-use-coproc. If it should be allowed, remove -mno-use-coproc from the command line.
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MSGID: SIMD_NO_GUARDS
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Insufficient guard bits.
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MSGID: SIMD_NO_LOAD_CONV
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The processor configuration does not support load conversion from %s to %s.
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MSGID: SIMD_NO_LOOP
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No well-formed for-loops in function.
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LONGDESC
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The compiler can only vectorize for-loops with clear data dependences.
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MSGID: SIMD_NO_REDUCTION
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The processor configuration does not support vector reduction of %s.
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MSGID: SIMD_NO_SCALAR_CONV
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The processor configuration does not support scalar to vector conversion of %s.
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MSGID: SIMD_NO_SELECT
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No %d-way vector select instruction available to transform %s accesses.
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LONGDESC
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In certain cases, the data needs to be rearranged in order to vectorize a loop successfully. However, the required vector select instructions are not available in the current processor configuration.
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MSGID: SIMD_NO_SNL
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Function contains no well-formed simply-nested for-loops.
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LONGDESC
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The compiler can vectorize inner or outer simply-nested for-loops. In a simply-nested loop, there is only one loop at each nesting depth. For example:
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for (i = 0; i < N; i++) {
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...
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for (j = 0; j < M; j++) { ... }
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...
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for (k = 0; k < M; k++) { ... }
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...
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}
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Loop j and k are at the same nesting depth, so loop i is not simply-nested. The compiler may transform the loop nest into two simply nested loops -- one for i and j, and another one for i and k. If an outer loop can't be transformed to simply-nested loops, it won't be vectorized.
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MSGID: SIMD_NO_STORE_CONV
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The processor configuration does not support store conversion from %s to %s.
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MSGID: SIMD_NO_TYPE_CONV
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The processor configuration does not support type conversion from %s to %s.
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MSGID: SIMD_NO_VECTOR_OP
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The processor configuration does not support vector %s.
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MSGID: SIMD_NO_VECTOR_TYPE
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The processor configuration does not support vector %s.
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MSGID: SIMD_NO_VECTOR_TYPE_SIZE
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The processor configuration does not support %d-way vector %s.
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MSGID: SIMD_NON_COUNTABLE_LOOP
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The loop is not a countable for-loop.
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LONGDESC
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The compiler can vectorize only single induction variable countable for-loops, or loops that can be transformed automatically into this form. Use of non-int induction variables or pointer accesses may prevent the compiler from recognizing countable for-loops.
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MSGID: SIMD_OUTER_LOOP
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This is an outer loop. Refer to the enclosed inner loops for analysis messages.
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MSGID: SIMD_PRAGMA_IGNORED
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Unable to apply the #pragma at line %d to a for-loop.
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LONGDESC
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#pragma 'concurrent', 'simd' or 'simd_if_convert' must be placed immediately before the countable for-loop it applies to. For example,
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#pragma simd
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for (i = 0; i < N; i++)
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a[i] = b[i];
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MSGID: SIMD_PROC_BEGIN
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Vectorization analysis for function '%s'.
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MSGID: SIMD_SCALAR_ARRAY_STORE
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Scalar array store '%s' prevents vectorization.
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LONGDESC
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A non-vector store to an array element prevents vectorization. For example, the loop below can't be vectorized because of the use of array 'temp'. In order to vectorize such loops, one should use temporary scalar variables instead.
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int temp[2];
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for (i = 0; i < 100; i += 2) {
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temp[0] = a[i];
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temp[1] = a[i + 1];
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b[i] = temp[0] + temp[1];
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b[i + 1] = temp[0] - temp[1];
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}
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MSGID: SIMD_SCALAR_DEPENDENCE
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Bad scalar dependences (variable '%s').
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LONGDESC
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Data dependences on a scalar variable prevent vectorization. For example, the loop below can't be vectorized because of the data dependence on 'partial_sum'.
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int partial_sum = 0;
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for (i = 0; i < 100; i++) {
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partial_sum += a[i];
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b[i] = partial_sum;
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}
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MSGID: SIMD_SIGNED_POW_TWO_DIV
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Unsupported division of a signed value by a power-of-two amount.
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LONGDESC
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In order to vectorize a loop by converting a power-of-two division operation into an equivalent right-shift operation, the type of the shifted value must be unsigned. The sample expressions below demonstrate the difference between signed and unsigned division:
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1 / 2 = 0
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1 >> 1 = 0
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(-1) / 2 = 0
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(-1) >> 1 = -1
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One possible conversion from division to right-shift operations is illustrated by the following example:
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unsigned int ui;
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signed int si;
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ui = ui / 4;
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si = si / 4;
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The equivalent shift expressions for the two variables are:
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ui = ui >> 2;
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si = ((si >= 0) ? si : (si + 3)) >> 2;
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MSGID: SIMD_SMALL_TRIP_COUNT
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Loop trip count is too small.
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LONGDESC
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Vectorization is not supported if the smallest available vectorization factor is greater than the loop iteration count.
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MSGID: SIMD_TRAPEZOIDAL_INNER_LOOP
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Inner loop bounds depend on outer loop index.
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LONGDESC
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Loop nests where the loop bound of an inner loop depends on an outer loop index are called trapezoidal. The compiler may vectorize trapezoidal loops of depth 2. In this example, loops j and k can be vectorized but loop i cannot because it contains trapezoidal inner loops.
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for (i = 0; i < 100; i++)
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for (j = 0; j < i; j++)
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for (k = 0; k < i; k++)
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s += a[i + j + k];
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MSGID: SIMD_UNALIGNED_LOAD
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The processor configuration does not support unaligned %s loads.
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MSGID: SIMD_UNALIGNED_STORE
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The processor configuration does not support unaligned %s stores.
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MSGID: SIMD_UNSIGNED_LOOP_UPPER_BOUND
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Unsigned '<' upper bound expression may prevent loop vectorization.
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LONGDESC
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The compiler tries to standardize all for-loop upper bounds to 'index <= bound' expressions. When an unsigned '<' loop bound expression is transformed to '<=', the extra code required to guarantee correctness can't be vectorized. Therefore, unsigned '<' upper bounds may prevent vectorization of enclosing loops.
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MSGID: SIMD_VARIANT_SHIFT
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Shift by loop-variant shift amount not supported (%s).
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LONGDESC
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The compiler is unable to vectorize expressions with shift-amounts that vary for different loop iterations. For example, if 'i' is the loop index, the left-shift 'a[i] << b[i]' has a shift-amount 'b[i]' that potentially varies on every iteration, and so a loop containing this expression cannot be vectorized.
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MSGID: SIMD_VAR_STRIDE
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The processor configuration does not support variable stride accesses.
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LONGDESC
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In certain cases, variable stride accesses can be vectorized using indexed updating, scalar-to-vector loads (LS.XU), and vector select instructions. However, these instructions are not available in the current processor configuration.
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MSGID: TIE_COPROCESSOR
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Unable to replace TIE with coprocessor '%s'. Remove the coprocessor statement or use the 'generate' option to extend the TIE.
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MSGID: TIE_BIG_CTYPE
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Unable to replace input TIE -- ctype '%s' has size %d, which is greater than the containing regfile size.
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MSGID: SIMD_NOANALYSIS_LOOP
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Already vectorized or non-analyzable loop.
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LONGDESC
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The loop cannot be analyzed to determine if it is vectorizable or not. The loop may contain non-array indirect memory accesses, function calls, use of non-vectorizable TIE intrinsics or unsupported control-flow such as GOTO statements. Or the loop may already be vectorized using SIMD operations specified in the input TIE.
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MSGID: SIMD_FUSED_LOOP
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Loop at line %d fused into loop at line %d
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LONGDESC
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This loop has been combined with an adjacent loop.
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MSGID: SIMD_DELETED_LOOP
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Loop at line %d deleted as dead code
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LONGDESC
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This loop has been deleted as redundant or unreachable code.
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