Initial commit: Linux kernel 4.19 for Unplugged OS

drivers/misc/mediatek/lpm/modules/include/gs/mtk_lpm_pwr_gs.h

@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_LPM_PWR_GS_H__
+#define __MTK_LPM_PWR_GS_H__
+
+enum MTK_LPM_GS_COMPARER {
+	MTK_LPM_GS_CMP_PMIC,
+	MTK_LPM_GS_CMP_CLK,
+	MTK_LPM_GS_CMP_PLL,
+	MTK_LPM_GS_CMP_MAX
+};
+
+struct mtk_lpm_gs_cmp {
+	int (*init)(void);
+	void (*deinit)(void);
+	int (*cmp_init)(void *data);
+	int (*cmp)(int user);
+	int (*cmp_by_type)(int user, unsigned int type);
+};
+
+int mtk_lpm_pwr_gs_compare_register(int comparer, struct mtk_lpm_gs_cmp *cmp);
+
+void mtk_lpm_pwr_gs_compare_unregister(int comparer);
+
+int mtk_lpm_pwr_gs_compare_init(int comparer, void *info);
+
+int mtk_lpm_pwr_gs_compare(int comparer, int user);
+
+int mtk_lpm_pwr_gs_compare_by_type(int comparer, int user, unsigned int type);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/gs/v1/mtk_power_gs.h

@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_POWER_GS_V1_H__
+#define __MTK_POWER_GS_V1_H__
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/debugfs.h>
+#include <linux/proc_fs.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+#define REMAP_SIZE_MASK     0xFFF
+
+enum MTK_LPM_PWR_GS_TYPE {
+	MTK_LPM_PWR_GS_TYPE_SUSPEND,
+	MTK_LPM_PWR_GS_TYPE_VCORELP_26M,
+	MTK_LPM_PWR_GS_TYPE_VCORELP,
+	MTK_LPM_PWR_GS_TYPE_MAX
+};
+
+enum GS_FLAGS {
+	GS_PMIC = (0x1 << 0),
+	GS_PMIC_6315 = (0x1 << 1),
+	GS_CG   = (0x1 << 2),
+	GS_DCM  = (0x1 << 3),
+	/* GS_ALL will need to be modified, if the gs_dump_flag is changed */
+	GS_ALL  = (GS_PMIC | GS_PMIC_6315 | GS_CG | GS_DCM),
+};
+
+/* pmic */
+struct mtk_lpm_gs_pmic_user {
+	char *name;
+	unsigned int array_sz;
+	const unsigned int *array;
+};
+
+struct mtk_lpm_gs_pmic {
+	unsigned int type;
+	const char *regulator;
+	const char *pwr_domain;
+	struct mtk_lpm_gs_pmic_user user[MTK_LPM_PWR_GS_TYPE_MAX];
+};
+
+struct mtk_lpm_gs_pmic_info {
+	int (*attach)(struct mtk_lpm_gs_pmic *p);
+	struct mtk_lpm_gs_pmic **pmic;
+};
+
+/* DCM, CG */
+struct mtk_lpm_gs_clk_user {
+	char *name;
+	unsigned int array_sz;
+	const unsigned int *array;
+};
+
+struct mtk_lpm_gs_clk {
+	unsigned int type;
+	char *name;
+	struct mtk_lpm_gs_clk_user user[MTK_LPM_PWR_GS_TYPE_MAX];
+};
+
+struct mtk_lpm_gs_clk_info {
+	int (*attach)(struct mtk_lpm_gs_clk *p);
+	struct mtk_lpm_gs_clk **dcm;
+};
+
+struct phys_to_virt_table {
+	void __iomem *va;
+	unsigned int pa;
+};
+
+struct base_remap {
+	unsigned int table_pos;
+	unsigned int table_size;
+	struct phys_to_virt_table *table;
+};
+
+int mtk_lpm_pwr_gs_common_init(void);
+
+void mtk_lpm_pwr_gs_common_deinit(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6779/mt6779_cond.h

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MT6779_COND_H__
+#define __MT6779_COND_H__
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]    : idle condition check fail
+ */
+
+#define SPM_COND_BLOCKED_CG_IDX		(0)
+#define SPM_COND_BLOCKED_PLL_IDX	(16)
+#define SPM_COND_BLOCKED_PLL		(1<<30L)
+#define SPM_COND_CHECK_FAIL		(1<<31L)
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS_0 = 0,
+	PLAT_SPM_COND_MTCMOS_1,
+	PLAT_SPM_COND_CG_INFRA_0,
+	PLAT_SPM_COND_CG_INFRA_1,
+	PLAT_SPM_COND_CG_INFRA_2,
+	PLAT_SPM_COND_CG_INFRA_3,
+	PLAT_SPM_COND_CG_MMSYS_0,
+	PLAT_SPM_COND_CG_MMSYS_1,
+	PLAT_SPM_COND_MAX,
+};
+
+enum PLAT_SPM_PLL_COND {
+	PLAT_SPM_COND_UNIVPLL = 0,
+	PLAT_SPM_COND_MFGPLL,
+	PLAT_SPM_COND_MSDCPLL,
+	PLAT_SPM_COND_TVPLL,
+	PLAT_SPM_COND_MMPLL,
+	PLAT_SPM_COND_PLL_MAX,
+};
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6779/mt6779_pcm_def.h

@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __pcm_def_h__
+#define __pcm_def_h__
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF                      (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN               (1U << 1)
+#define R0_SC_MEM_CK_OFF                      (1U << 2)
+#define R0_SC_AXI_CK_OFF                      (1U << 3)
+#define R0_SC_DR_SRAM_LOAD                    (1U << 4)
+#define R0_SC_MD26M_CK_OFF                    (1U << 5)
+#define R0_SC_DPY_MODE_SW                     (1U << 6)
+#define R0_SC_DMSUS_OFF                       (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN                  (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE                 (1U << 9)
+#define R0_SC_MPLLOUT_OFF                     (1U << 10)
+#define R0_SC_TX_TRACKING_DIS                 (1U << 11)
+#define R0_SC_DPY_DLL_EN                      (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN                   (1U << 13)
+#define R0_SC_DPY_VREF_EN                     (1U << 14)
+#define R0_SC_PHYPLL_EN                       (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN                 (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE                 (1U << 17)
+#define R0_SC_MPLL_OFF                        (1U << 18)
+#define R0_SC_SHU_RESTORE                     (1U << 19)
+#define R0_SC_CKSQ0_OFF                       (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH         (1U << 21)
+#define R0_SC_DR_SHU_EN                       (1U << 22)
+#define R0_SC_DHPY_PRECAL_UP                  (1U << 23)
+#define R0_SC_MPLL_S_OFF                      (1U << 24)
+#define R0_SC_DHPY_RXDLY_TRACK_EN             (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN                   (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN                  (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW                  (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW                 (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0                   (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1                   (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ                    (1U << 0)
+#define R7_EMI_CLK_OFF_REQ                    (1U << 1)
+#define R7_TOP_MAS_PAU_REQ                    (1U << 2)
+#define R7_SPM2CKSYS_MEM_CK_MUX_UPDATE        (1U << 3)
+#define R7_PCM_CK_SEL0                        (1U << 4)
+#define R7_PCM_CK_SEL1                        (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ             (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL                  (1U << 7)
+#define R7_SC_26M_CK_SEL                      (1U << 8)
+#define R7_PCM_TIMER_SET                      (1U << 9)
+#define R7_PCM_TIMER_CLR                      (1U << 10)
+#define R7_SRCVOLTEN                          (1U << 11)
+#define R7_CSYSPWRUPACK                       (1U << 12)
+#define R7_IM_SLEEP_ENABLE                    (1U << 13)
+#define R7_SRCCLKENO_0                        (1U << 14)
+#define R7_SPM_SYSRST_B                       (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK             (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL              (1U << 17)
+#define R7_SC_AXI_DCM_DIS                     (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM                   (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN                  (1U << 20)
+#define R7_SRCCLKENO_1                        (1U << 21)
+#define R7_WDT_KICK_P                         (1U << 22)
+#define R7_SC_TIMER_RST                       (1U << 23)
+#define R7_WAKEUP_EXT_W_SEL                   (1U << 24)
+#define R7_WAKEUP_EXT_R_SEL                   (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN                    (1U << 26)
+#define R7_FORCE_26M_WAKE                     (1U << 27)
+#define R7_FORCE_APSRC_WAKE                   (1U << 28)
+#define R7_FORCE_INFRA_WAKE                   (1U << 29)
+#define R7_FORCE_VRF18_WAKE                   (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK            (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER_EVENT                   (1U << 0)
+#define R12_SPM_TWAM_IRQ_B                    (1U << 1)
+#define R12_KP_IRQ_B                          (1U << 2)
+#define R12_APWDT_EVENT_B                     (1U << 3)
+#define R12_APXGPT1_EVENT_B                   (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B              (1U << 5)
+#define R12_EINT_EVENT_B                      (1U << 6)
+#define R12_CONN_WDT_IRQ_B                    (1U << 7)
+#define R12_CCIF0_EVENT_B                     (1U << 8)
+#define R12_LOWBATTERY_IRQ_B                  (1U << 9)
+#define R12_SC_SSPM2SPM_WAKEUP                (1U << 10)
+#define R12_SC_SCP2SPM_WAKEUP                 (1U << 11)
+#define R12_SC_ADSP2SPM_WAKEUP                (1U << 12)
+#define R12_PCM_WDT_EVENT_B                   (1U << 13)
+#define R12_USBX_CDSC_B                       (1U << 14)
+#define R12_USBX_POWERDWN_B                   (1U << 15)
+#define R12_SYS_TIMER_EVENT_B                 (1U << 16)
+#define R12_EINT_EVENT_SECURE_B               (1U << 17)
+#define R12_CCIF1_EVENT_B                     (1U << 18)
+#define R12_UART0_IRQ_B                       (1U << 19)
+#define R12_AFE_IRQ_MCU_B                     (1U << 20)
+#define R12_THERMAL_CTRL_EVENT_B              (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B                    (1U << 22)
+#define R12_MD2AP_PEER_WAKEUP_EVENT           (1U << 23)
+#define R12_CSYSPWREQ_B                       (1U << 24)
+#define R12_MD1_WDT_B                         (1U << 25)
+#define R12_AP2AP_PEER_WAKEUP_EVENT           (1U << 26)
+#define R12_SEJ_EVENT_B                       (1U << 27)
+#define R12_SPM_CPU_WAKEUP_EVENT              (1U << 28)
+#define R12_CPU_IRQOUT                        (1U << 29)
+#define R12_CPU_WFI                           (1U << 30)
+#define R12_MCUSYS_IDLE_TO_EMI_ALL            (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE                       (1U << 0)
+#define R12EXT_26M_SLEEP                      (1U << 1)
+#define R12EXT_INFRA_WAKE                     (1U << 2)
+#define R12EXT_INFRA_SLEEP                    (1U << 3)
+#define R12EXT_APSRC_WAKE                     (1U << 4)
+#define R12EXT_APSRC_SLEEP                    (1U << 5)
+#define R12EXT_VRF18_WAKE                     (1U << 6)
+#define R12EXT_VRF18_SLEEP                    (1U << 7)
+#define R12EXT_DVFS_WAKE                      (1U << 8)
+#define R12EXT_DDREN_WAKE                     (1U << 9)
+#define R12EXT_DDREN_SLEEP                    (1U << 10)
+#define R12EXT_DDREN2_WAKE                    (1U << 11)
+#define R12EXT_DDREN2_SLEEP                   (1U << 12)
+#define R12EXT_CONN_SRCCLKENB                 (1U << 13)
+#define R12EXT_CONN_SRCCLKENB__B              (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE                (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE              (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE              (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE               (1U << 18)
+#define R12EXT_VS2_VOTER_INT0                 (1U << 19)
+#define R12EXT_VS2_VOTER_INT1                 (1U << 20)
+#define R12EXT_VS2_VOTER_INT2                 (1U << 21)
+#define R12EXT_VS1_VOTER_INT0                 (1U << 22)
+#define R12EXT_VS1_VOTER_INT1                 (1U << 23)
+#define R12EXT_BIT24                          (1U << 24)
+#define R12EXT_BIT25                          (1U << 25)
+#define R12EXT_BIT26                          (1U << 26)
+#define R12EXT_BIT27                          (1U << 27)
+#define R12EXT_BIT28                          (1U << 28)
+#define R12EXT_BIT29                          (1U << 29)
+#define R12EXT_BIT30                          (1U << 30)
+#define R12EXT_BIT31                          (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0                        (1U << 0)
+#define R13_SRCCLKENI1                        (1U << 1)
+#define R13_MD_SRCCLKENA_0                    (1U << 2)
+#define R13_MD_APSRC_REQ_0                    (1U << 3)
+#define R13_CONN_DDR_EN                       (1U << 4)
+#define R13_MD_SRCCLKENA_1                    (1U << 5)
+#define R13_SSPM_SRCCLKENA                    (1U << 6)
+#define R13_SSPM_APSRC_REQ                    (1U << 7)
+#define R13_MD1_STATE                         (1U << 8)
+#define R13_EMI_CLK_OFF_2_ACK                 (1U << 9)
+#define R13_MM_STATE                          (1U << 10)
+#define R13_SSPM_STATE                        (1U << 11)
+#define R13_MD_DDR_EN_0                       (1U << 12)
+#define R13_CONN_STATE                        (1U << 13)
+#define R13_CONN_SRCCLKENA                    (1U << 14)
+#define R13_CONN_APSRC_REQ                    (1U << 15)
+#define R13_BIT16                             (1U << 16)
+#define R13_BIT17                             (1U << 17)
+#define R13_SCP_STATE                         (1U << 18)
+#define R13_CSYSPWRUPREQ                      (1U << 19)
+#define R13_PWRAP_SLEEP_ACK                   (1U << 20)
+#define R13_EMI_CLK_OFF_ACK_ALL               (1U << 21)
+#define R13_AUDIO_DSP_STATE                   (1U << 22)
+#define R13_SW_DMDRAMCSHU_ACK_ALL             (1U << 23)
+#define R13_CONN_SRCCLKENB                    (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL           (1U << 25)
+#define R13_INFRA_AUX_IDLE                    (1U << 26)
+#define R13_DVFS_STATE                        (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL       (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL        (1U << 29)
+#define R13_MD_VRF18_REQ_0                    (1U << 30)
+#define R13_DDR_EN_STATE                      (1U << 31)
+
+enum SPM_WAKE_SRC_LIST {
+	WAKE_SRC_R12_PCM_TIMER = (1U << 0),
+	WAKE_SRC_R12_SPM_TWAM_IRQ_B = (1U << 1),
+	WAKE_SRC_R12_KP_IRQ_B = (1U << 2),
+	WAKE_SRC_R12_APWDT_EVENT_B = (1U << 3),
+	WAKE_SRC_R12_APXGPT1_EVENT_B = (1U << 4),
+	WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B = (1U << 5),
+	WAKE_SRC_R12_EINT_EVENT_B = (1U << 6),
+	WAKE_SRC_R12_CONN_WDT_IRQ_B = (1U << 7),
+	WAKE_SRC_R12_CCIF0_EVENT_B = (1U << 8),
+	WAKE_SRC_R12_LOWBATTERY_IRQ_B = (1U << 9),
+	WAKE_SRC_R12_SSPM_SPM_IRQ_B = (1U << 10),
+	WAKE_SRC_R12_SCP_SPM_IRQ_B = (1U << 11),
+	WAKE_SRC_R12_SC_ADSP2SPM_WAKEUP = (1U << 12),
+	WAKE_SRC_R12_PCM_WDT_WAKEUP_B = (1U << 13),
+	WAKE_SRC_R12_USB_CDSC_B = (1U << 14),
+	WAKE_SRC_R12_USB_POWERDWN_B = (1U << 15),
+	WAKE_SRC_R12_SYS_TIMER_EVENT_B = (1U << 16),
+	WAKE_SRC_R12_EINT_EVENT_SECURE_B = (1U << 17),
+	WAKE_SRC_R12_CCIF1_EVENT_B = (1U << 18),
+	WAKE_SRC_R12_UART0_IRQ_B = (1U << 19),
+	WAKE_SRC_R12_AFE_IRQ_MCU_B = (1U << 20),
+	WAKE_SRC_R12_THERMAL_CTRL_EVENT_B = (1U << 21),
+	WAKE_SRC_R12_SYS_CIRQ_IRQ_B = (1U << 22),
+	WAKE_SRC_R12_MD2AP_PEER_WAKEUP_EVENT = (1U << 23),
+	WAKE_SRC_R12_CSYSPWREQ_B = (1U << 24),
+	WAKE_SRC_R12_MD1_WDT_B = (1U << 25),
+	WAKE_SRC_R12_AP2AP_PEER_WAKEUP_EVENT = (1U << 26),
+	WAKE_SRC_R12_SEJ_EVENT_B = (1U << 27),
+	WAKE_SRC_R12_SPM_CPU_WAKEUP_EVENT = (1U << 28),
+	WAKE_SRC_R12_CPU_IRQOUT = (1U << 29),
+	WAKE_SRC_R12_CPU_WFI = (1U << 30),
+};
+
+extern const char *wakesrc_str[32];
+
+/* define WAKE_SRC_CONN2AP for conn use */
+#define WAKE_SRC_CONN2AP WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B
+
+#endif /* __pcm_def_h__ */

drivers/misc/mediatek/lpm/modules/include/mt6779/mt6779_pwr_ctrl.h

@@ -0,0 +1,454 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __PWR_CTRL_H__
+#define __PWR_CTRL_H__
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP              0x3FF  /* bit0 ~ bit9 */
+#define WAKE_MISC_DVFSRC_IRQ	         (1U << 16)
+#define WAKE_MISC_REG_CPU_WAKEUP         (1U << 17)
+#define WAKE_MISC_PCM_TIMER_EVENT        (1U << 18)
+#define WAKE_MISC_PMIC_OUT_B		     ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B             (1U << 21)
+#define WAKE_MISC_PMSR_IRQ_B_SET0        (1U << 22)
+#define WAKE_MISC_PMSR_IRQ_B_SET1        (1U << 23)
+#define WAKE_MISC_PMSR_IRQ_B_SET2        (1U << 24)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0   (1U << 25)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1	 (1U << 26)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2	 (1U << 27)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3	 (1U << 28)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL (1U << 29)
+#define WAKE_MISC_PMIC_IRQ_ACK			 (1U << 30)
+#define WAKE_MISC_PMIC_SCP_IRQ			 (1U << 31)
+
+struct pwr_ctrl {
+
+	/* for SPM */
+	u32 pcm_flags;
+	u32 pcm_flags_cust;
+	u32 pcm_flags_cust_set;
+	u32 pcm_flags_cust_clr;
+	u32 pcm_flags1;
+	u32 pcm_flags1_cust;
+	u32 pcm_flags1_cust_set;
+	u32 pcm_flags1_cust_clr;
+	u32 timer_val;
+	u32 timer_val_cust;
+	u32 timer_val_ramp_en;
+	u32 timer_val_ramp_en_sec;
+	u32 wake_src;
+	u32 wake_src_cust;
+	u32 wakelock_timer_val;
+	u8 wdt_disable;
+	/* Auto-gen Start */
+
+	/* SPM_CLK_CON */
+	u8 reg_srcclken0_ctl;
+	u8 reg_srcclken1_ctl;
+	u8 reg_spm_lock_infra_dcm;
+	u8 reg_srcclken_mask;
+	u8 reg_md1_c32rm_en;
+	u8 reg_md2_c32rm_en;
+	u8 reg_clksq0_sel_ctrl;
+	u8 reg_clksq1_sel_ctrl;
+	u8 reg_srcclken0_en;
+	u8 reg_srcclken1_en;
+	u32 reg_sysclk0_src_mask_b;
+	u32 reg_sysclk1_src_mask_b;
+
+	/* SPM_AP_STANDBY_CON */
+	u8 reg_wfi_op;
+	u8 reg_wfi_type;
+	u8 reg_mp0_cputop_idle_mask;
+	u8 reg_mp1_cputop_idle_mask;
+	u8 reg_mcusys_idle_mask;
+	u8 reg_md_apsrc_1_sel;
+	u8 reg_md_apsrc_0_sel;
+	u8 reg_conn_apsrc_sel;
+
+	/* SPM_SRC_REQ */
+	u8 reg_spm_apsrc_req;
+	u8 reg_spm_f26m_req;
+	u8 reg_spm_infra_req;
+	u8 reg_spm_vrf18_req;
+	u8 reg_spm_ddr_en_req;
+	u8 reg_spm_ddr_en2_req;
+	u8 reg_spm_dvfs_req;
+	u8 reg_spm_sw_mailbox_req;
+	u8 reg_spm_sspm_mailbox_req;
+	u8 reg_spm_adsp_mailbox_req;
+	u8 reg_spm_scp_mailbox_req;
+	u8 reg_spm_mcusys_pwr_event_req;
+	u8 cpu_md_dvfs_sop_force_on;
+
+	/* SPM_SRC_MASK */
+	u8 reg_md_srcclkena_0_mask_b;
+	u8 reg_md_srcclkena2infra_req_0_mask_b;
+	u8 reg_md_apsrc2infra_req_0_mask_b;
+	u8 reg_md_apsrc_req_0_mask_b;
+	u8 reg_md_vrf18_req_0_mask_b;
+	u8 reg_md_ddr_en_0_mask_b;
+	u8 reg_md_ddr_en2_0_mask_b;
+	u8 reg_md_srcclkena_1_mask_b;
+	u8 reg_md_srcclkena2infra_req_1_mask_b;
+	u8 reg_md_apsrc2infra_req_1_mask_b;
+	u8 reg_md_apsrc_req_1_mask_b;
+	u8 reg_md_vrf18_req_1_mask_b;
+	u8 reg_md_ddr_en_1_mask_b;
+	u8 reg_md_ddr_en2_1_mask_b;
+	u8 reg_conn_srcclkena_mask_b;
+	u8 reg_conn_srcclkenb_mask_b;
+	u8 reg_conn_infra_req_mask_b;
+	u8 reg_conn_apsrc_req_mask_b;
+	u8 reg_conn_vrf18_req_mask_b;
+	u8 reg_conn_ddr_en_mask_b;
+	u8 reg_conn_ddr_en2_mask_b;
+	u8 reg_srcclkeni0_srcclkena_mask_b;
+	u8 reg_srcclkeni0_infra_req_mask_b;
+	u8 reg_srcclkeni1_srcclkena_mask_b;
+	u8 reg_srcclkeni1_infra_req_mask_b;
+	u8 reg_srcclkeni2_srcclkena_mask_b;
+	u8 reg_srcclkeni2_infra_req_mask_b;
+	u8 reg_infrasys_apsrc_req_mask_b;
+	u8 reg_infrasys_ddr_en_mask_b;
+	u8 reg_infrasys_ddr_en2_mask_b;
+	u8 reg_md32_srcclkena_mask_b;
+	u8 reg_conn_vfe28_req_mask_b;
+
+	/* SPM_SRC2_MASK */
+	u8 reg_md32_infra_req_mask_b;
+	u8 reg_md32_apsrc_req_mask_b;
+	u8 reg_md32_vrf18_req_mask_b;
+	u8 reg_md32_ddr_en_mask_b;
+	u8 reg_md32_ddr_en2_mask_b;
+	u8 reg_scp_srcclkena_mask_b;
+	u8 reg_scp_infra_req_mask_b;
+	u8 reg_scp_apsrc_req_mask_b;
+	u8 reg_scp_vrf18_req_mask_b;
+	u8 reg_scp_ddr_en_mask_b;
+	u8 reg_scp_ddr_en2_mask_b;
+	u8 reg_ufs_srcclkena_mask_b;
+	u8 reg_ufs_infra_req_mask_b;
+	u8 reg_ufs_apsrc_req_mask_b;
+	u8 reg_ufs_vrf18_req_mask_b;
+	u8 reg_ufs_ddr_en_mask_b;
+	u8 reg_ufs_ddr_en2_mask_b;
+	u8 reg_disp0_apsrc_req_mask_b;
+	u8 reg_disp0_ddr_en_mask_b;
+	u8 reg_disp0_ddr_en2_mask_b;
+	u8 reg_disp1_apsrc_req_mask_b;
+	u8 reg_disp1_ddr_en_mask_b;
+	u8 reg_disp1_ddr_en2_mask_b;
+	u8 reg_gce_infra_req_mask_b;
+	u8 reg_gce_apsrc_req_mask_b;
+	u8 reg_gce_vrf18_req_mask_b;
+	u8 reg_gce_ddr_en_mask_b;
+	u8 reg_gce_ddr_en2_mask_b;
+	u8 reg_emi_ch0_ddr_en_mask_b;
+	u8 reg_emi_ch1_ddr_en_mask_b;
+	u8 reg_emi_ch0_ddr_en2_mask_b;
+	u8 reg_emi_ch1_ddr_en2_mask_b;
+
+	/* SPM_SRC3_MASK */
+	u8 reg_dvfsrc_event_trigger_mask_b;
+	u8 reg_sw2spm_int0_mask_b;
+	u8 reg_sw2spm_int1_mask_b;
+	u8 reg_sw2spm_int2_mask_b;
+	u8 reg_sw2spm_int3_mask_b;
+	u8 reg_sc_adsp2spm_wakeup_mask_b;
+	u8 reg_sc_sspm2spm_wakeup_mask_b;
+	u8 reg_sc_scp2spm_wakeup_mask_b;
+	u8 reg_csyspwrreq_mask;
+	u8 reg_spm_srcclkena_reserved_mask_b;
+	u8 reg_spm_infra_req_reserved_mask_b;
+	u8 reg_spm_apsrc_req_reserved_mask_b;
+	u8 reg_spm_vrf18_req_reserved_mask_b;
+	u8 reg_spm_ddr_en_reserved_mask_b;
+	u8 reg_spm_ddr_en2_reserved_mask_b;
+	u8 reg_audio_dsp_srcclkena_mask_b;
+	u8 reg_audio_dsp_infra_req_mask_b;
+	u8 reg_audio_dsp_apsrc_req_mask_b;
+	u8 reg_audio_dsp_vrf18_req_mask_b;
+	u8 reg_audio_dsp_ddr_en_mask_b;
+	u8 reg_audio_dsp_ddr_en2_mask_b;
+	u8 reg_mcusys_pwr_event_mask_b;
+	u8 reg_msdc0_srcclkena_mask_b;
+	u8 reg_msdc0_infra_req_mask_b;
+	u8 reg_msdc0_apsrc_req_mask_b;
+	u8 reg_msdc0_vrf18_req_mask_b;
+	u8 reg_msdc0_ddr_en_mask_b;
+	u8 reg_msdc0_ddr_en2_mask_b;
+	u8 reg_conn_srcclkenb2pwrap_mask_b;
+
+	/* SPM_SRC4_MASK */
+	u32 ccif_event_mask_b;
+	u8 reg_apu_core0_srcclkena_mask_b;
+	u8 reg_apu_core0_infra_req_mask_b;
+	u8 reg_apu_core0_apsrc_req_mask_b;
+	u8 reg_apu_core0_vrf18_req_mask_b;
+	u8 reg_apu_core0_ddr_en_mask_b;
+	u8 reg_apu_core1_srcclkena_mask_b;
+	u8 reg_apu_core1_infra_req_mask_b;
+	u8 reg_apu_core1_apsrc_req_mask_b;
+	u8 reg_apu_core1_vrf18_req_mask_b;
+	u8 reg_apu_core1_ddr_en_mask_b;
+	u8 reg_apu_core2_srcclkena_mask_b;
+	u8 reg_apu_core2_infra_req_mask_b;
+	u8 reg_apu_core2_apsrc_req_mask_b;
+	u8 reg_apu_core2_vrf18_req_mask_b;
+	u8 reg_apu_core2_ddr_en_mask_b;
+	u8 reg_apu_core2_ddr_en2_mask_b;
+
+	/* SPM_SRC5_MASK */
+	u32 reg_mcusys_merge_apsrc_req_mask_b;
+	u32 reg_mcusys_merge_ddr_en_mask_b;
+	u32 reg_mcusys_merge_ddr_en2_mask_b;
+	u8 reg_apu_core0_ddr_en2_mask_b;
+	u8 reg_apu_core1_ddr_en2_mask_b;
+	u8 reg_cg_check_ddr_en_mask_b;
+	u8 reg_cg_check_ddr_en2_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	u32 reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	u32 reg_ext_wakeup_event_mask;
+
+	/* SPM_SRC6_MASK */
+	u8 reg_msdc1_srcclkena_mask_b;
+	u8 reg_msdc1_infra_req_mask_b;
+	u8 reg_msdc1_apsrc_req_mask_b;
+	u8 reg_msdc1_vrf18_req_mask_b;
+	u8 reg_msdc1_ddr_en_mask_b;
+	u8 reg_msdc1_ddr_en2_mask_b;
+	u8 reg_msdc1_srcclkena_ack_mask;
+	u8 reg_msdc1_infra_ack_mask;
+	u8 reg_msdc1_apsrc_ack_mask;
+	u8 reg_msdc1_vrf18_ack_mask;
+	u8 reg_msdc1_ddr_en_ack_mask;
+	u8 reg_msdc1_ddr_en2_ack_mask;
+
+	/* MP0_CPU0_WFI_EN */
+	u8 mp0_cpu0_wfi_en;
+
+	/* MP0_CPU1_WFI_EN */
+	u8 mp0_cpu1_wfi_en;
+
+	/* MP0_CPU2_WFI_EN */
+	u8 mp0_cpu2_wfi_en;
+
+	/* MP0_CPU3_WFI_EN */
+	u8 mp0_cpu3_wfi_en;
+
+	/* MP0_CPU4_WFI_EN */
+	u8 mp0_cpu4_wfi_en;
+
+	/* MP0_CPU5_WFI_EN */
+	u8 mp0_cpu5_wfi_en;
+
+	/* MP0_CPU6_WFI_EN */
+	u8 mp0_cpu6_wfi_en;
+
+	/* MP0_CPU7_WFI_EN */
+	u8 mp0_cpu7_wfi_en;
+
+	/* Auto-gen End */
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+	PW_REG_SRCCLKEN0_CTL,
+	PW_REG_SRCCLKEN1_CTL,
+	PW_REG_SPM_LOCK_INFRA_DCM,
+	PW_REG_SRCCLKEN_MASK,
+	PW_REG_MD1_C32RM_EN,
+	PW_REG_MD2_C32RM_EN,
+	PW_REG_CLKSQ0_SEL_CTRL,
+	PW_REG_CLKSQ1_SEL_CTRL,
+	PW_REG_SRCCLKEN0_EN,
+	PW_REG_SRCCLKEN1_EN,
+	PW_REG_SYSCLK0_SRC_MASK_B,
+	PW_REG_SYSCLK1_SRC_MASK_B,
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDR_EN_REQ,
+	PW_REG_SPM_DDR_EN2_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+	PW_REG_SPM_MCUSYS_PWR_EVENT_REQ,
+	PW_CPU_MD_DVFS_SOP_FORCE_ON,
+	PW_REG_MD_SRCCLKENA_0_MASK_B,
+	PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
+	PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
+	PW_REG_MD_APSRC_REQ_0_MASK_B,
+	PW_REG_MD_VRF18_REQ_0_MASK_B,
+	PW_REG_MD_DDR_EN_0_MASK_B,
+	PW_REG_MD_DDR_EN2_0_MASK_B,
+	PW_REG_MD_SRCCLKENA_1_MASK_B,
+	PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
+	PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
+	PW_REG_MD_APSRC_REQ_1_MASK_B,
+	PW_REG_MD_VRF18_REQ_1_MASK_B,
+	PW_REG_MD_DDR_EN_1_MASK_B,
+	PW_REG_MD_DDR_EN2_1_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_CONN_DDR_EN_MASK_B,
+	PW_REG_CONN_DDR_EN2_MASK_B,
+	PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
+	PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
+	PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDR_EN_MASK_B,
+	PW_REG_INFRASYS_DDR_EN2_MASK_B,
+	PW_REG_MD32_SRCCLKENA_MASK_B,
+	PW_REG_CONN_VFE28_REQ_MASK_B,
+	PW_REG_MD32_INFRA_REQ_MASK_B,
+	PW_REG_MD32_APSRC_REQ_MASK_B,
+	PW_REG_MD32_VRF18_REQ_MASK_B,
+	PW_REG_MD32_DDR_EN_MASK_B,
+	PW_REG_MD32_DDR_EN2_MASK_B,
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDR_EN_MASK_B,
+	PW_REG_SCP_DDR_EN2_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDR_EN_MASK_B,
+	PW_REG_UFS_DDR_EN2_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDR_EN_MASK_B,
+	PW_REG_DISP0_DDR_EN2_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDR_EN_MASK_B,
+	PW_REG_DISP1_DDR_EN2_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GCE_DDR_EN_MASK_B,
+	PW_REG_GCE_DDR_EN2_MASK_B,
+	PW_REG_EMI_CH0_DDR_EN_MASK_B,
+	PW_REG_EMI_CH1_DDR_EN_MASK_B,
+	PW_REG_EMI_CH0_DDR_EN2_MASK_B,
+	PW_REG_EMI_CH1_DDR_EN2_MASK_B,
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_SW2SPM_INT0_MASK_B,
+	PW_REG_SW2SPM_INT1_MASK_B,
+	PW_REG_SW2SPM_INT2_MASK_B,
+	PW_REG_SW2SPM_INT3_MASK_B,
+	PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRREQ_MASK,
+	PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
+	PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
+	PW_REG_SPM_DDR_EN2_RESERVED_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
+	PW_REG_AUDIO_DSP_DDR_EN2_MASK_B,
+	PW_REG_MCUSYS_PWR_EVENT_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDR_EN_MASK_B,
+	PW_REG_MSDC0_DDR_EN2_MASK_B,
+	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+	PW_CCIF_EVENT_MASK_B,
+	PW_REG_APU_CORE0_SRCCLKENA_MASK_B,
+	PW_REG_APU_CORE0_INFRA_REQ_MASK_B,
+	PW_REG_APU_CORE0_APSRC_REQ_MASK_B,
+	PW_REG_APU_CORE0_VRF18_REQ_MASK_B,
+	PW_REG_APU_CORE0_DDR_EN_MASK_B,
+	PW_REG_APU_CORE1_SRCCLKENA_MASK_B,
+	PW_REG_APU_CORE1_INFRA_REQ_MASK_B,
+	PW_REG_APU_CORE1_APSRC_REQ_MASK_B,
+	PW_REG_APU_CORE1_VRF18_REQ_MASK_B,
+	PW_REG_APU_CORE1_DDR_EN_MASK_B,
+	PW_REG_APU_CORE2_SRCCLKENA_MASK_B,
+	PW_REG_APU_CORE2_INFRA_REQ_MASK_B,
+	PW_REG_APU_CORE2_APSRC_REQ_MASK_B,
+	PW_REG_APU_CORE2_VRF18_REQ_MASK_B,
+	PW_REG_APU_CORE2_DDR_EN_MASK_B,
+	PW_REG_APU_CORE2_DDR_EN2_MASK_B,
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDR_EN2_MASK_B,
+	PW_REG_APU_CORE0_DDR_EN2_MASK_B,
+	PW_REG_APU_CORE1_DDR_EN2_MASK_B,
+	PW_REG_CG_CHECK_DDR_EN_MASK_B,
+	PW_REG_CG_CHECK_DDR_EN2_MASK_B,
+	PW_REG_WAKEUP_EVENT_MASK,
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDR_EN_MASK_B,
+	PW_REG_MSDC1_DDR_EN2_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_ACK_MASK,
+	PW_REG_MSDC1_INFRA_ACK_MASK,
+	PW_REG_MSDC1_APSRC_ACK_MASK,
+	PW_REG_MSDC1_VRF18_ACK_MASK,
+	PW_REG_MSDC1_DDR_EN_ACK_MASK,
+	PW_REG_MSDC1_DDR_EN2_ACK_MASK,
+	PW_MP0_CPU0_WFI_EN,
+	PW_MP0_CPU1_WFI_EN,
+	PW_MP0_CPU2_WFI_EN,
+	PW_MP0_CPU3_WFI_EN,
+	PW_MP0_CPU4_WFI_EN,
+	PW_MP0_CPU5_WFI_EN,
+	PW_MP0_CPU6_WFI_EN,
+	PW_MP0_CPU7_WFI_EN,
+	PW_MAX_COUNT,
+};
+
+#endif /* __PWR_CTRL_H__ */

drivers/misc/mediatek/lpm/modules/include/mt6779/mt6779_spm_comm.h

@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MT6779_SPM_COMM_H__
+#define __MT6779_SPM_COMM_H__
+
+struct mt6779_spm_wake_status {
+	u32 r12;			/* SPM_SW_RSV_0 */
+	u32 r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	u32 raw_sta;		/* SPM_WAKEUP_STA */
+	u32 raw_ext_sta;	/* SPM_WAKEUP_EXT_STA */
+	u32 md32pcm_wakeup_sta;/* MD32CPM_WAKEUP_STA */
+	u32 md32pcm_event_sta;/* MD32PCM_EVENT_STA */
+	u32 wake_misc;		/* SPM_SW_RSV_5 */
+	u32 timer_out;		/* SPM_SW_RSV_6 */
+	u32 r13;			/* PCM_REG13_DATA */
+	u32 idle_sta;		/* SUBSYS_IDLE_STA */
+	u32 req_sta0;		/* SRC_REQ_STA_0 */
+	u32 req_sta1;		/* SRC_REQ_STA_1 */
+	u32 req_sta2;		/* SRC_REQ_STA_2 */
+	u32 req_sta3;		/* SRC_REQ_STA_3 */
+	u32 req_sta4;		/* SRC_REQ_STA_4 */
+	u32 debug_flag;		/* PCM_WDT_LATCH_SPARE_0 */
+	u32 debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	u32 b_sw_flag0;		/* SPM_SW_RSV_7 */
+	u32 b_sw_flag1;		/* SPM_SW_RSV_8 */
+	u32 isr;			/* SPM_IRQ_STA */
+	u32 sw_flag0;		/* SPM_SW_FLAG_0 */
+	u32 sw_flag1;		/* SPM_SW_FLAG_1 */
+	u32 clk_settle;		/* SPM_CLK_SETTLE */
+	u32 src_req;	/* SPM_SRC_REQ */
+	u32 log_index;
+	u32 is_abort;
+};
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ * From Legacy sleep_def.h
+ */
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN               (0x1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN             (0x1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN            (0x1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS             (0x1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS             (0x1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO       (0x1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF           (0x1U << 6)
+#define SPM_FLAG_DISABBLE_ARMPLL_OFF           (0x1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRUPACK_HIGH        (0x1U << 8)
+#define SPM_FLAG_DISABLE_CPU_VPROC_VSRAM_PDN   (0x1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO           (0x1U << 10)
+#define SPM_FLAG_ENABLE_MET_DEBUG_USAGE        (0x1U << 11)
+#define SPM_FLAG_RESERVED_BIT12                (0x1U << 12)
+#define SPM_FLAG_SODI_NO_EVENT                 (0x1U << 13)
+#define SPM_FLAG_ENABLE_SODI3                  (0x1U << 14)
+#define SPM_FLAG_RESERVED_BIT15                (0x1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP          (0x1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP       (0x1U << 17)
+#define SPM_FLAG_RESERVED_BIT18                (0x1U << 18)
+#define SPM_FLAG_SUSPEND_OPTION                (0x1U << 19)
+#define SPM_FLAG_DEEPIDLE_OPTION               (0x1U << 20)
+#define SPM_FLAG_SODI_OPTION                   (0x1U << 21)
+#define SPM_FLAG_RESERVED_BIT22                (0x1U << 22)
+#define SPM_FLAG_RESERVED_BIT23                (0x1U << 23)
+#define SPM_FLAG_RESERVED_BIT24                (0x1U << 24)
+#define SPM_FLAG_RESERVED_BIT25                (0x1U << 25)
+#define SPM_FLAG_RESERVED_BIT26                (0x1U << 26)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT27     (0x1U << 27)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT28     (0x1U << 28)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT29     (0x1U << 29)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT30     (0x1U << 30)
+#define SPM_FLAG_SPM_FLAG_DONT_TOUCH_BIT31     (0x1U << 31)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M       (0x1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF           (0x1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH     (0x1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF           (0x1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON             (0x1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5                (0x1U << 5)
+#define SPM_FLAG1_DISABLE_NO_RESUME            (0x1U << 6)
+#define SPM_FLAG1_ENABLE_BIG_BUCK_OFF          (0x1U << 7)
+#define SPM_FLAG1_ENABLE_BIG_BUCK_ON           (0x1U << 8)
+#define SPM_FLAG1_FORCE_CPU_BUCK_OFF           (0x1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW          (0x1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH       (0x1U << 11)
+#define SPM_FLAG1_DISABLE_TOP_26M_CK_OFF       (0x1U << 12)
+#define SPM_FLAG1_DISABPE_PCM_26M_SWITCH       (0x1U << 13)
+#define SPM_FLAG1_DISABLE_CKSQ_OFF             (0x1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15               (0x1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16               (0x1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17               (0x1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18               (0x1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19               (0x1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP    (0x1U << 20)
+#define SPM_FLAG1_DISABLE_AXI_MEM_CLK_OFF      (0x1U << 21)
+#define SPM_FLAG1_DISABLE_VS1_VOTER            (0x1U << 22)
+#define SPM_FLAG1_DISABLE_VS2_VOTER            (0x1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CON    (0x1U << 24)
+#define SPM_FLAG1_DISABLE_MD_BUCK_0P55         (0x1U << 25)
+#define SPM_FLAG1_DISABLE_MD_LDO_0P60          (0x1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27               (0x1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28               (0x1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29               (0x1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30               (0x1U << 30)
+#define SPM_FLAG1_RESERVED_BIT31               (0x1U << 31)
+/* --- SPM DEBUG Define --- */
+#define DEBUG_IDX_26M_WAKE                     (0x1U << 0)
+#define DEBUG_IDX_26M_SLEEP                    (0x1U << 1)
+#define DEBUG_IDX_INFRA_WAKE                   (0x1U << 2)
+#define DEBUG_IDX_INFRA_SLEEP                  (0x1U << 3)
+#define DEBUG_IDX_APSRC_WAKE                   (0x1U << 4)
+#define DEBUG_IDX_APSRC_SLEEP                  (0x1U << 5)
+#define DEBUG_IDX_VRF18_WAKE                   (0x1U << 6)
+#define DEBUG_IDX_VRF18_SLEEP                  (0x1U << 7)
+#define DEBUG_IDX_DDREN_WAKE                   (0x1U << 8)
+#define DEBUG_IDX_DDREN_SLEEP                  (0x1U << 9)
+#define DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC     (0x1U << 10)
+#define DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN     (0x1U << 11)
+#define DEBUG_IDX_CPU_PDN                      (0x1U << 12)
+#define DEBUG_IDX_VPROC1_OFF                   (0x1U << 13)
+#define DEBUG_IDX_VPROC2_OFF                   (0x1U << 14)
+#define DEBUG_IDX_ARMPLL_OFF                   (0x1U << 15)
+#define DEBUG_IDX_SYSRAM_SLP                   (0x1U << 16)
+#define DEBUG_IDX_SSPM_WFI                     (0x1U << 17)
+#define DEBUG_IDX_SSPM_SRAM_SLP                (0x1U << 18)
+#define DEBUG_IDX_SSPM_ON                      (0x1U << 19)
+#define DEBUG_IDX_SYSRAM_ON                    (0x1U << 20)
+#define DEBUG_IDX_ARMPLL_ON                    (0x1U << 21)
+#define DEBUG_IDX_VPROC1_ON                    (0x1U << 22)
+#define DEBUG_IDX_VPROC2_ON                    (0x1U << 23)
+#define DEBUG_IDX_SCP_VCORE_0P625V             (0x1U << 24)
+#define DEBUG_IDX_SCP_VCORE_0P700V             (0x1U << 25)
+#define DEBUG_IDX_SCP_VCORE_0P750V             (0x1U << 26)
+#define DEBUG_IDX_SCP_VCORE_0P800V             (0x1U << 27)
+#define DEBUG_IDX_VCORE_DVFS_START             (0x1U << 28)
+#define DEBUG_IDX_APSRC_SLEEP_ABORT            (0x1U << 29)
+#define DEBUG_IDX_AXI_MEM_CLK_OFF              (0x1U << 30)
+#define DEBUG_IDX_AXI_MEM_CLK_ON               (0x1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define DEBUG_IDX_SPM_GO_WAKEUP_NOW            (0x1U << 0)
+#define DEBUG_IDX_RESERVED_BIT1                (0x1U << 1)
+#define DEBUG_IDX_SYSPLL_OFF                   (0x1U << 2)
+#define DEBUG_IDX_SYSPLL_ON                    (0x1U << 3)
+#define DEBUG_IDX_CURRENT_IS_VCORE_DFS         (0x1U << 4)
+#define DEBUG_IDX_INFRA_MTCMOS_OFF             (0x1U << 5)
+#define DEBUG_IDX_INFRA_MTCMOS_ON              (0x1U << 6)
+#define DEBUG_IDX_VTCXO_SLEEP_ABORT_0          (0x1U << 7)
+#define DEBUG_IDX_VTCXO_SLEEP_ABORT_1          (0x1U << 8)
+#define DEBUG_IDX_RESERVED_BIT9                (0x1U << 9)
+#define DEBUG_IDX_RESERVED_BIT10               (0x1U << 10)
+#define DEBUG_IDX_PWRAP_CLK_TO_ULPOSC          (0x1U << 11)
+#define DEBUG_IDX_PWRAP_CLK_TO_26M             (0x1U << 12)
+#define DEBUG_IDX_SCP_CLK_TO_32K               (0x1U << 13)
+#define DEBUG_IDX_SCP_CLK_TO_26M               (0x1U << 14)
+#define DEBUG_IDX_BUS_CLK_OFF                  (0x1U << 15)
+#define DEBUG_IDX_BUS_CLK_ON                   (0x1U << 16)
+#define DEBUG_IDX_SRCLKEN2_LOW                 (0x1U << 17)
+#define DEBUG_IDX_SRCLKEN2_HIGH                (0x1U << 18)
+#define DEBUG_IDX_DORMANT_WAKEUP               (0x1U << 19)
+#define DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON  (0x1U << 20)
+#define DEBUG_IDX_PMIC_IRQ_ACK_LOW_ABORT       (0x1U << 21)
+#define DEBUG_IDX_PMIC_IRQ_ACK_HIGH_ABORT      (0x1U << 22)
+#define DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT    (0x1U << 23)
+#define DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT   (0x1U << 24)
+#define DEBUG_IDX_EMI_SLP_IDLE_ABORT           (0x1U << 25)
+#define DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT        (0x1U << 26)
+#define DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT       (0x1U << 27)
+#define DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT       (0x1U << 28)
+#define DEBUG_IDX_MCUSYS_PWR_ACK_LOW_ABORT     (0x1U << 29)
+#define DEBUG_IDX_CORE_PWR_ACK_HIGH_ABORT      (0x1U << 30)
+#define DEBUG_IDX_CURRENT_IS_LP                (0x1U << 31)
+/* --- SPM DEBUG2 Define --- */
+#define DEBUG_IDX_VS2_BIT0                     (0x1U << 0)
+#define DEBUG_IDX_VS2_BTT1                     (0x1U << 1)
+#define DEBUG_IDX_VS2_BIT2                     (0x1U << 2)
+#define DEBUG_IDX_VS1_BIT0                     (0x1U << 3)
+#define DEBUG_IDX_VS1_BIT1                     (0x1U << 4)
+
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC \
+	| DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 (DEBUG_IDX_VTCXO_SLEEP_ABORT_0 \
+	| DEBUG_IDX_VTCXO_SLEEP_ABORT_1 \
+	| DEBUG_IDX_PMIC_IRQ_ACK_LOW_ABORT \
+	| DEBUG_IDX_PMIC_IRQ_ACK_HIGH_ABORT \
+	| DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT \
+	| DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT \
+	| DEBUG_IDX_EMI_SLP_IDLE_ABORT \
+	| DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT \
+	| DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT \
+	| DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT \
+	| DEBUG_IDX_MCUSYS_PWR_ACK_LOW_ABORT \
+	| DEBUG_IDX_CORE_PWR_ACK_HIGH_ABORT)
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6779/mtk_lp_plat_apmcu.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef __MTK_LP_PLAT_APMCU_H__
+#define __MTK_LP_PLAT_APMCU_H__
+
+#include <linux/types.h>
+
+#define nr_cluster_ids                  (1)
+#define get_physical_cluster_id(cpu)    (0)
+
+#define LP_PM_SYSRAM_INFO_OFS  0x8
+#define LP_PM_SYSRAM_SIZE      0x800
+
+extern void __iomem *cpu_pm_syssram_base;
+/* 0x11B000 */
+#define MT_CPU_PM_KERNEL_SRAMBASE	(cpu_pm_syssram_base + 0x100)
+#define MT_CPU_PM_KERNEL_SRAM(slot)	(MT_CPU_PM_KERNEL_SRAMBASE + (slot<<2))
+
+
+#define cpu_pm_sync_writel(v, a)				\
+do {								\
+	__raw_writel((v), (void __force __iomem *)((a)));	\
+	mb(); /*make sure register access in order */		\
+} while (0)
+
+#define MT_CPU_PM_KERNEL_SRAM_WR(slot, val) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			cpu_pm_sync_writel(val,\
+				MT_CPU_PM_KERNEL_SRAM(slot)); uval; })
+
+
+#define MT_CPU_PM_KERNEL_SRAM_RD(slot) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			uval = __raw_readl(MT_CPU_PM_KERNEL_SRAM(slot));\
+		uval; })
+
+void mtk_lp_plat_set_mcusys_off(int cpu);
+void mtk_lp_plat_clr_mcusys_off(int cpu);
+
+void mtk_lp_plat_set_cluster_off(int cpu);
+void mtk_lp_plat_clr_cluster_off(int cpu);
+
+bool mtk_lp_plat_is_mcusys_off(void);
+bool mtk_lp_plat_is_cluster_off(int cpu);
+
+int mtk_lp_plat_apmcu_init(void);
+int mtk_lp_plat_apmcu_early_init(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6779/mtk_lp_plat_apmcu_mbox.h

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_LP_PLAT_APMCU_MBOX_H__
+#define __MTK_LP_PLAT_APMCU_MBOX_H__
+
+enum {
+	MBOX_SSPM,
+	MBOX_MCUPM,
+
+	NF_MBOX,
+};
+
+/* SSPM Mbox */
+#define APMCU_SSPM_MBOX_ID           3
+#define APMCU_SSPM_MBOX_SPM_CMD_SIZE 8
+
+#define APMCU_SSPM_MBOX_SPM_CMD      0
+#define APMCU_SSPM_MBOX_SPM_ARGS1    1
+#define APMCU_SSPM_MBOX_SPM_ARGS2    2
+#define APMCU_SSPM_MBOX_SPM_ARGS3    3
+#define APMCU_SSPM_MBOX_SPM_ARGS4    4
+#define APMCU_SSPM_MBOX_SPM_ARGS5    5
+#define APMCU_SSPM_MBOX_SPM_ARGS6    6
+#define APMCU_SSPM_MBOX_SPM_ARGS7    7
+#define APMCU_SSPM_MBOX_AP_READY     17
+
+void mtk_set_sspm_lp_cmd(void *buf);
+void mtk_clr_sspm_lp_cmd(void);
+
+
+/* MCUPM Mbox */
+
+#define APMCU_MCUPM_MBOX_ID             3
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY       0
+#define APMCU_MCUPM_MBOX_RESERVED_1     1
+#define APMCU_MCUPM_MBOX_RESERVED_2     2
+#define APMCU_MCUPM_MBOX_RESERVED_3     3
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN    4
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE  5
+#define APMCU_MCUPM_MBOX_BUCK_MODE      6
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE    7
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA       8
+#define APMCU_MCUPM_MBOX_RESERVED_9     9
+#define APMCU_MCUPM_MBOX_RESERVED_10    10
+#define APMCU_MCUPM_MBOX_RESERVED_11    11
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU     12
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN (4) */
+#define MCUPM_MCUSYS_CTRL               (1 << 0)
+#define MCUPM_BUCK_CTRL                 (1 << 1)
+#define MCUPM_ARMPLL_CTRL               (1 << 2)
+#define MCUPM_PWR_CTRL_MASK             ((1 << 3) - 1)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_L3_CACHE_MODE (5) */
+#define MCUPM_L3_OFF_MODE               0 /* default */
+#define MCUPM_L3_DORMANT_MODE           1
+#define NF_MCUPM_L3_MODE                2U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE (6) */
+#define MCUPM_BUCK_NORMAL_MODE          0 /* default */
+#define MCUPM_BUCK_LP_MODE              1
+#define MCUPM_BUCK_OFF_MODE             2
+#define NF_MCUPM_BUCK_MODE              3U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE (7) */
+#define MCUPM_ARMPLL_ON                 0 /* default */
+#define MCUPM_ARMPLL_GATING             1
+#define MCUPM_ARMPLL_OFF                2
+#define NF_MCUPM_ARMPLL_MODE            3U
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA (9) */
+#define MCUPM_TASK_UNINIT               0
+#define MCUPM_TASK_INIT                 1
+#define MCUPM_TASK_INIT_FINISH          2
+#define MCUPM_TASK_WAIT                 3
+#define MCUPM_TASK_RUN                  4
+#define MCUPM_TASK_PAUSE                5
+
+void mtk_mcupm_pwr_ctrl_en(int dev);
+void mtk_mcupm_pwr_ctrl_dis(int dev);
+
+void mtk_set_mcupm_pll_mode(unsigned int mode);
+int mtk_get_mcupm_pll_mode(void);
+
+void mtk_set_mcupm_buck_mode(unsigned int mode);
+int mtk_get_mcupm_buck_mode(void);
+
+void mtk_set_preferred_cpu_wakeup(int cpu);
+int mtk_get_preferred_cpu_wakeup(void);
+
+bool mtk_mcupm_is_ready(void);
+
+void mtk_wait_mbox_init_done(void);
+void mtk_notify_subsys_ap_ready(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6779/mtk_lp_plat_reg.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_PLAT_CPC_REG_H__
+#define __MTK_PLAT_CPC_REG_H__
+
+/**************************************
+ * CPC related register
+ * base address = 0x0C53A000
+ **************************************/
+#define CPC_FLOW_CTRL_CFG              (0x814)
+#define CPC_MCUSYS_LAST_CORE_REQ       (0x818)
+#define CPC_CPUSYS_LAST_CORE_RESP      (0x81C)
+#define CPC_MCUSYS_LAST_CORE_RESP      (0x824)
+#define CPC_PWR_ON_MASK                (0x828)
+#define CPC_SPMC_PWR_STATUS            (0x840)
+#define CPC_CPUSYS_CPU_ON_SW_HINT_CLR  (0x8AC)
+
+#define SPMC_DBG_SETTING               (0xB00)
+
+#define CPC_TRACE_DATA_SEL             (0xB14)
+
+#define CPC_CPU0_LATENCY               (0xB40)
+#define CPC_CPU1_LATENCY               (0xB44)
+#define CPC_CPU2_LATENCY               (0xB48)
+#define CPC_CPU3_LATENCY               (0xB4C)
+#define CPC_CPU4_LATENCY               (0xB50)
+#define CPC_CPU5_LATENCY               (0xB54)
+#define CPC_CPU6_LATENCY               (0xB58)
+#define CPC_CPU7_LATENCY               (0xB5C)
+#define CPC_CLUSTER_OFF_LATENCY        (0xB60)
+#define CPC_CLUSTER_ON_LATENCY         (0xB64)
+#define CPC_MCUSYS_LATENCY             (0xB68)
+#define CPC_DORMANT_COUNTER            (0xB70)
+#define CPC_DORMANT_COUNTER_CLR        (0xB74)
+#define CPC_CPU_LATENCY(cpu)           ((CPC_CPU0_LATENCY) + 4 * (cpu))
+
+/**************************************
+ * system sram for apmcu debug
+ * base address = 0x0011B000
+ **************************************/
+#define SYSRAM_CPUSYS_CNT              (0x1E8)
+#define SYSRAM_MCUSYS_CNT              (0x1EC)
+#define SYSRAM_CPC_CPUSYS_CNT_BACKUP   (0x1F0)
+#define SYSRAM_CPC_MCUSYS_CNT_BACKUP   (0x1F4)
+#define SYSRAM_CPU_ONLINE              (0x1F8)
+
+/* Run time information. The registers may be cleared in db dump flow */
+#define SYSRAM_RECENT_CPU_CNT(i)       (4 * (i) + 0x1B0)
+#define SYSRAM_RECENT_CPUSYS_CNT       (0x1D0)
+#define SYSRAM_RECENT_MCUSYS_CNT       (0x1D4)
+#define SYSRAM_RECENT_CNT_TS_L         (0x1D8)
+#define SYSRAM_RECENT_CNT_TS_H         (0x1DC)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6781/mt6781_cond.h

@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MT6781_COND_H__
+#define __MT6781_COND_H__
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]    : idle condition check fail
+ */
+
+#define SPM_COND_BLOCKED_CG_IDX		(0)
+#define SPM_COND_BLOCKED_PLL_IDX	(16)
+#define SPM_COND_BLOCKED_PLL		(1<<30L)
+#define SPM_COND_CHECK_FAIL		(1<<31L)
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS_0 = 0,
+	PLAT_SPM_COND_CG_INFRA_0,
+	PLAT_SPM_COND_CG_INFRA_1,
+	PLAT_SPM_COND_CG_INFRA_2,
+	PLAT_SPM_COND_CG_INFRA_3,
+	PLAT_SPM_COND_CG_INFRA_4,
+	PLAT_SPM_COND_CG_INFRA_5,
+	PLAT_SPM_COND_CG_MMSYS_0,
+	PLAT_SPM_COND_CG_MMSYS_1,
+	PLAT_SPM_COND_CG_MMSYS_2,
+	PLAT_SPM_COND_CG_MMSYS_3,
+	PLAT_SPM_COND_MAX,
+};
+
+enum PLAT_SPM_PLL_COND {
+	PLAT_SPM_COND_UNIVPLL = 0,
+	PLAT_SPM_COND_MFGPLL,
+	PLAT_SPM_COND_MSDCPLL,
+	PLAT_SPM_COND_TVPLL,
+	PLAT_SPM_COND_MMPLL,
+	PLAT_SPM_COND_PLL_MAX,
+};
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6781/mt6781_pcm_def.h

@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+#ifndef __pcm_def_h__
+#define __pcm_def_h__
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF                      (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN               (1U << 1)
+#define R0_SC_MEM_CK_OFF                      (1U << 2)
+#define R0_SC_AXI_CK_OFF                      (1U << 3)
+#define R0_SC_DR_SRAM_LOAD                    (1U << 4)
+#define R0_SC_MD26M_CK_OFF                    (1U << 5)
+#define R0_SC_DPY_MODE_SW                     (1U << 6)
+#define R0_SC_DMSUS_OFF                       (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN                  (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE                 (1U << 9)
+#define R0_SC_MPLLOUT_OFF                     (1U << 10)
+#define R0_SC_TX_TRACKING_DIS                 (1U << 11)
+#define R0_SC_DPY_DLL_EN                      (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN                   (1U << 13)
+#define R0_SC_DPY_VREF_EN                     (1U << 14)
+#define R0_SC_PHYPLL_EN                       (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN                 (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE                 (1U << 17)
+#define R0_SC_MPLL_OFF                        (1U << 18)
+#define R0_SC_SHU_RESTORE                     (1U << 19)
+#define R0_SC_CKSQ0_OFF                       (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH         (1U << 21)
+#define R0_SC_DR_SHU_EN                       (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP                  (1U << 23)
+#define R0_SC_MPLL_S_OFF                      (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN          (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN                   (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN                  (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW                  (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW                 (1U << 29)
+#define R0_SC_DR0_SHU_LEVEL			(1U << 30)
+#define R0_SC_DR1_SHU_LEVEL			(1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ                    (1U << 0)
+#define R7_EMI_CLK_OFF_REQ_PCM                (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ                (1U << 2)
+#define R7_SPM_CK_UPDATE                      (1U << 3)
+#define R7_SPM_CK_SEL0                        (1U << 4)
+#define R7_SPM_CK_SEL1                        (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ             (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL                  (1U << 7)
+#define R7_SC_26M_CK_SEL                      (1U << 8)
+#define R7_PCM_TIMER_SET                      (1U << 9)
+#define R7_PCM_TIMER_CLR                      (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ              (1U << 11)
+#define R7_CSYSPWRUPACK                       (1U << 12)
+#define R7_PCM_IM_SLP_EN                      (1U << 13)
+#define R7_SRCCLKENO0                         (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE                  (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK             (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL              (1U << 17)
+#define R7_SC_AXI_DCM_DIS                     (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM                   (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN                  (1U << 20)
+#define R7_SRCCLKENO1                         (1U << 21)
+#define R7_PCM_WDT_KICK_P                     (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC              (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM                 (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM           (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN                    (1U << 26)
+#define R7_FORCE_F26M_WAKE                    (1U << 27)
+#define R7_FORCE_APSRC_WAKE                   (1U << 28)
+#define R7_FORCE_INFRA_WAKE                   (1U << 29)
+#define R7_FORCE_VRF18_WAKE                   (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK            (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER                         (1U << 0)
+#define R12_TWAM_IRQ_B                        (1U << 1)
+#define R12_KP_IRQ_B                          (1U << 2)
+#define R12_APWDT_EVENT_B                     (1U << 3)
+#define R12_APXGPT1_EVENT_B                   (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B              (1U << 5)
+#define R12_EINT_EVENT_B                      (1U << 6)
+#define R12_CONN_WDT_IRQ_B                    (1U << 7)
+#define R12_CCIF0_EVENT_B                     (1U << 8)
+#define R12_LOWBATTERY_IRQ_B                  (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B                 (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B                  (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B                 (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B                  (1U << 13)
+#define R12_USBX_CDSC_B                       (1U << 14)
+#define R12_USBX_POWERDWN_B                   (1U << 15)
+#define R12_SYS_TIMER_EVENT_B                 (1U << 16)
+#define R12_EINT_EVENT_SECURE_B               (1U << 17)
+#define R12_CCIF1_EVENT_B                     (1U << 18)
+#define R12_UART0_IRQ_B                       (1U << 19)
+#define R12_AFE_IRQ_MCU_B                     (1U << 20)
+#define R12_THERM_CTRL_EVENT_B                (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B                    (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B                (1U << 23)
+#define R12_CSYSPWREQ_B                       (1U << 24)
+#define R12_MD1_WDT_B                         (1U << 25)
+#define R12_CLDMA_EVENT_B                     (1U << 26)
+#define R12_SEJ_EVENT_B                       (1U << 27)
+#define R12_REG_CPU_WAKEUP                    (1U << 28)
+#define R12_CPU_IRQOUT						  (1U << 29)
+#define R12_CPU_WFI							  (1U << 30)
+#define R12_MCUSYS_IDLE						  (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE                       (1U << 0)
+#define R12EXT_26M_SLEEP                      (1U << 1)
+#define R12EXT_INFRA_WAKE                     (1U << 2)
+#define R12EXT_INFRA_SLEEP                    (1U << 3)
+#define R12EXT_APSRC_WAKE                     (1U << 4)
+#define R12EXT_APSRC_SLEEP                    (1U << 5)
+#define R12EXT_VRF18_WAKE                     (1U << 6)
+#define R12EXT_VRF18_SLEEP                    (1U << 7)
+#define R12EXT_DVFS_WAKE                      (1U << 8)
+#define R12EXT_DDREN_WAKE                     (1U << 9)
+#define R12EXT_DDREN_SLEEP                    (1U << 10)
+#define R12EXT_MCU_PM_WFI                     (1U << 11)
+#define R12EXT_SSPM_IDLE                      (1U << 12)
+#define R12EXT_CONN_SRCCLKENB                 (1U << 13)
+#define R12EXT_DRAMC_MD32_WFI_MERGE           (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE                (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE              (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE              (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE               (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK          (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK         (1U << 20)
+#define R12EXT_BIT21				(1U << 21)
+#define R12EXT_BIT22				(1U << 22)
+#define R12EXT_BIT23				(1U << 23)
+#define R12EXT_BIT24				(1U << 24)
+#define R12EXT_BIT25				(1U << 25)
+#define R12EXT_BIT26                          (1U << 26)
+#define R12EXT_BIT27                          (1U << 27)
+#define R12EXT_BIT28                          (1U << 28)
+#define R12EXT_BIT29                          (1U << 29)
+#define R12EXT_BIT30                          (1U << 30)
+#define R12EXT_BIT31                          (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0                        (1U << 0)
+#define R13_SRCCLKENI1                        (1U << 1)
+#define R13_MD_0_SRCCLKENA                    (1U << 2)
+#define R13_MD_0_APSRC_REQ                    (1U << 3)
+#define R13_CONN_DDREN                        (1U << 4)
+#define R13_MD_1_SRCCLKENA                    (1U << 5)
+#define R13_SSPM_SRCCLKENA                    (1U << 6)
+#define R13_SSPM_APSRC_REQ                    (1U << 7)
+#define R13_MD_1_STATE                        (1U << 8)
+#define R13_RC_SRCCLKENO_ACK                  (1U << 9)
+#define R13_MM_STATE                          (1U << 10)
+#define R13_SSPM_STATE                        (1U << 11)
+#define R13_MD_0_DDREN                        (1U << 12)
+#define R13_CONN_STATE                        (1U << 13)
+#define R13_CONN_SRCCLKENA                    (1U << 14)
+#define R13_CONN_APSRC_REQ                    (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL                (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL          (1U << 17)
+#define R13_SCP_STATE                         (1U << 18)
+#define R13_CSYSPWRUPREQ                      (1U << 19)
+#define R13_PWRAP_SLEEP_ACK                   (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL            (1U << 21)
+#define R13_AUDIO_DSP_STATE                   (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL             (1U << 23)
+#define R13_CONN_SRCCLKENB                    (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL           (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0              (1U << 26)
+#define R13_DVFS_STATE                        (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL       (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL        (1U << 29)
+#define R13_MD_0_VRF18_REQ                    (1U << 30)
+#define R13_DDR_EN_STATE                      (1U << 31)
+#endif /* __pcm_def_h__ */
+
+
+
+enum SPM_WAKE_SRC_LIST {
+	WAKE_SRC_STA1_PCM_TIMER = (1U << 0),
+	WAKE_SRC_STA1_RESERVED_DEBUG_B = (1U << 1),
+	WAKE_SRC_STA1_KP_IRQ_B = (1U << 2),
+	WAKE_SRC_STA1_APWDT_EVENT_B = (1U << 3),
+	WAKE_SRC_STA1_APXGPT1_EVENT_B = (1U << 4),
+	WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B = (1U << 5),
+	WAKE_SRC_STA1_EINT_EVENT_B = (1U << 6),
+	WAKE_SRC_STA1_CONN_WDT_IRQ_B = (1U << 7),
+	WAKE_SRC_STA1_CCIF0_EVENT_B = (1U << 8),
+	WAKE_SRC_STA1_LOWBATTERY_IRQ_B = (1U << 9),
+	WAKE_SRC_STA1_SC_SSPM2SPM_WAKEUP_B = (1U << 10),
+	WAKE_SRC_STA1_SC_SCP2SPM_WAKEUP_B = (1U << 11),
+	WAKE_SRC_STA1_SC_ADSP2SPM_WAKEUP_B = (1U << 12),
+	WAKE_SRC_STA1_PCM_WDT_WAKEUP_B = (1U << 13),
+	WAKE_SRC_STA1_USB_CDSC_B = (1U << 14),
+	WAKE_SRC_STA1_USB_POWERDWN_B = (1U << 15),
+	WAKE_SRC_STA1_SYS_TIMER_EVENT_B = (1U << 16),
+	WAKE_SRC_STA1_EINT_EVENT_SECURE_B = (1U << 17),
+	WAKE_SRC_STA1_CCIF1_EVENT_B = (1U << 18),
+	WAKE_SRC_STA1_UART0_IRQ_B = (1U << 19),
+	WAKE_SRC_STA1_AFE_IRQ_MCU_B = (1U << 20),
+	WAKE_SRC_STA1_THERM_CTRL_EVENT_B = (1U << 21),
+	WAKE_SRC_STA1_SYS_CIRQ_IRQ_B = (1U << 22),
+	WAKE_SRC_STA1_MD2AP_PEER_EVENT_B = (1U << 23),
+	WAKE_SRC_STA1_CSYSPWREQ_B = (1U << 24),
+	WAKE_SRC_STA1_MD1_WDT_B = (1U << 25),
+	WAKE_SRC_STA1_AP2AP_PEER_WAKEUPEVENT_B = (1U << 26),
+	WAKE_SRC_STA1_SEJ_EVENT_B = (1U << 27),
+	WAKE_SRC_STA1_SPM_CPU_WAKEUPEVENT_B = (1U << 28),
+	WAKE_SRC_STA1_CPU_IRQOUT = (1U << 29),
+	WAKE_SRC_STA1_CPU_WFI = (1U << 30),
+	WAKE_SRC_STA1_MCUSYS_IDLE = (1U << 31)
+};
+
+extern const char *wakesrc_str[32];
+
+/* define WAKE_SRC_CONN2AP for conn use */
+#define WAKE_SRC_CONN2AP WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B

drivers/misc/mediatek/lpm/modules/include/mt6781/mt6781_pwr_ctrl.h

@@ -0,0 +1,403 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __PWR_CTRL_H__
+#define __PWR_CTRL_H__
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP              0x3FF  /* bit0 ~ bit9 */
+#define WAKE_MISC_DVFSRC_IRQ	         (1U << 16)
+#define WAKE_MISC_REG_CPU_WAKEUP         (1U << 17)
+#define WAKE_MISC_PCM_TIMER_EVENT        (1U << 18)
+#define WAKE_MISC_PMIC_OUT_B		     ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B             (1U << 21)
+#define WAKE_MISC_PMSR_IRQ_B_SET0        (1U << 22)
+#define WAKE_MISC_PMSR_IRQ_B_SET1        (1U << 23)
+#define WAKE_MISC_PMSR_IRQ_B_SET2        (1U << 24)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0   (1U << 25)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1	 (1U << 26)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2	 (1U << 27)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3	 (1U << 28)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL (1U << 29)
+#define WAKE_MISC_PMIC_IRQ_ACK			 (1U << 30)
+#define WAKE_MISC_PMIC_SCP_IRQ			 (1U << 31)
+
+struct pwr_ctrl {
+
+	/* for SPM */
+	uint32_t pcm_flags;
+	uint32_t pcm_flags_cust;
+	uint32_t pcm_flags_cust_set;
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	uint32_t pcm_flags1_cust;
+	uint32_t pcm_flags1_cust_set;
+	uint32_t pcm_flags1_cust_clr;
+	uint32_t timer_val;
+	uint32_t timer_val_cust;
+	uint32_t timer_val_ramp_en;
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	uint32_t wake_src_cust;
+	uint32_t wakelock_timer_val;
+	uint8_t wdt_disable;
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	uint8_t reg_wfi_op;
+	uint8_t reg_wfi_type;
+	uint8_t reg_mp0_cputop_idle_mask;
+	uint8_t reg_mp1_cputop_idle_mask;
+	uint8_t reg_mcusys_idle_mask;
+	uint8_t reg_md_apsrc_1_sel;
+	uint8_t reg_md_apsrc_0_sel;
+	uint8_t reg_conn_apsrc_sel;
+
+	/* SPM_SRC6_MASK */
+	uint32_t reg_ccif_event_infra_req_mask_b;
+	uint32_t reg_ccif_event_apsrc_req_mask_b;
+
+	/* SPM_WAKEUP_EVENT_SENS */
+	uint32_t reg_wakeup_event_sens;
+
+	/* SPM_SRC_REQ */
+	uint8_t reg_spm_apsrc_req;
+	uint8_t reg_spm_f26m_req;
+	uint8_t reg_spm_infra_req;
+	uint8_t reg_spm_vrf18_req;
+	uint8_t reg_spm_ddren_req;
+	uint8_t reg_spm_dvfs_req;
+	uint8_t reg_spm_sw_mailbox_req;
+	uint8_t reg_spm_sspm_mailbox_req;
+	uint8_t reg_spm_adsp_mailbox_req;
+	uint8_t reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	uint8_t reg_md_0_srcclkena_mask_b;
+	uint8_t reg_md_0_infra_req_mask_b;
+	uint8_t reg_md_0_apsrc_req_mask_b;
+	uint8_t reg_md_0_vrf18_req_mask_b;
+	uint8_t reg_md_0_ddren_req_mask_b;
+	uint8_t reg_md_1_srcclkena_mask_b;
+	uint8_t reg_md_1_infra_req_mask_b;
+	uint8_t reg_md_1_apsrc_req_mask_b;
+	uint8_t reg_md_1_vrf18_req_mask_b;
+	uint8_t reg_md_1_ddren_req_mask_b;
+	uint8_t reg_conn_srcclkena_mask_b;
+	uint8_t reg_conn_srcclkenb_mask_b;
+	uint8_t reg_conn_infra_req_mask_b;
+	uint8_t reg_conn_apsrc_req_mask_b;
+	uint8_t reg_conn_vrf18_req_mask_b;
+	uint8_t reg_conn_ddren_req_mask_b;
+	uint8_t reg_conn_vfe28_mask_b;
+	uint8_t reg_srcclkeni_srcclkena_mask_b;
+	uint8_t reg_srcclkeni_infra_req_mask_b;
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	uint8_t reg_infrasys_ddren_req_mask_b;
+	uint8_t reg_sspm_srcclkena_mask_b;
+	uint8_t reg_sspm_infra_req_mask_b;
+	uint8_t reg_sspm_apsrc_req_mask_b;
+	uint8_t reg_sspm_vrf18_req_mask_b;
+	uint8_t reg_sspm_ddren_req_mask_b;
+
+	/* SPM_SRC2_MASK */
+	uint8_t reg_scp_srcclkena_mask_b;
+	uint8_t reg_scp_infra_req_mask_b;
+	uint8_t reg_scp_apsrc_req_mask_b;
+	uint8_t reg_scp_vrf18_req_mask_b;
+	uint8_t reg_scp_ddren_req_mask_b;
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	uint8_t reg_audio_dsp_ddren_req_mask_b;
+	uint8_t reg_ufs_srcclkena_mask_b;
+	uint8_t reg_ufs_infra_req_mask_b;
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	uint8_t reg_ufs_vrf18_req_mask_b;
+	uint8_t reg_ufs_ddren_req_mask_b;
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	uint8_t reg_disp0_ddren_req_mask_b;
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	uint8_t reg_disp1_ddren_req_mask_b;
+	uint8_t reg_gce_infra_req_mask_b;
+	uint8_t reg_gce_apsrc_req_mask_b;
+	uint8_t reg_gce_vrf18_req_mask_b;
+	uint8_t reg_gce_ddren_req_mask_b;
+	uint8_t reg_apu_srcclkena_mask_b;
+	uint8_t reg_apu_infra_req_mask_b;
+	uint8_t reg_apu_apsrc_req_mask_b;
+	uint8_t reg_apu_vrf18_req_mask_b;
+	uint8_t reg_apu_ddren_req_mask_b;
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	uint8_t reg_cg_check_ddren_req_mask_b;
+
+	/* SPM_SRC3_MASK */
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+	uint8_t reg_sw2spm_wakeup_mask_b;
+	uint8_t reg_adsp2spm_wakeup_mask_b;
+	uint8_t reg_sspm2spm_wakeup_mask_b;
+	uint8_t reg_scp2spm_wakeup_mask_b;
+	uint8_t reg_csyspwrup_ack_mask;
+	uint8_t reg_spm_reserved_srcclkena_mask_b;
+	uint8_t reg_spm_reserved_infra_req_mask_b;
+	uint8_t reg_spm_reserved_apsrc_req_mask_b;
+	uint8_t reg_spm_reserved_vrf18_req_mask_b;
+	uint8_t reg_spm_reserved_ddren_req_mask_b;
+	uint8_t reg_mcupm_srcclkena_mask_b;
+	uint8_t reg_mcupm_infra_req_mask_b;
+	uint8_t reg_mcupm_apsrc_req_mask_b;
+	uint8_t reg_mcupm_vrf18_req_mask_b;
+	uint8_t reg_mcupm_ddren_req_mask_b;
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	uint8_t reg_msdc0_infra_req_mask_b;
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	uint8_t reg_msdc0_ddren_req_mask_b;
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	uint8_t reg_msdc1_infra_req_mask_b;
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	uint8_t reg_msdc1_ddren_req_mask_b;
+
+	/* SPM_SRC4_MASK */
+	uint32_t reg_ccif_event_srcclkena_mask_b;
+	uint8_t reg_bak_psri_srcclkena_mask_b;
+	uint8_t reg_bak_psri_infra_req_mask_b;
+	uint8_t reg_bak_psri_apsrc_req_mask_b;
+	uint8_t reg_bak_psri_vrf18_req_mask_b;
+	uint8_t reg_bak_psri_ddren_req_mask_b;
+	uint8_t reg_dramc_md32_infra_req_mask_b;
+	uint8_t reg_dramc_md32_vrf18_req_mask_b;
+	uint8_t reg_conn_srcclkenb2pwrap_mask_b;
+	uint8_t reg_dramc_md32_apsrc_req_mask_b;
+
+	/* SPM_SRC5_MASK */
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	uint32_t reg_mcusys_merge_ddren_req_mask_b;
+	uint8_t reg_afe_srcclkena_mask_b;
+	uint8_t reg_afe_infra_req_mask_b;
+	uint8_t reg_afe_apsrc_req_mask_b;
+	uint8_t reg_afe_vrf18_req_mask_b;
+	uint8_t reg_afe_ddren_req_mask_b;
+	uint8_t reg_msdc2_srcclkena_mask_b;
+	uint8_t reg_msdc2_infra_req_mask_b;
+	uint8_t reg_msdc2_apsrc_req_mask_b;
+	uint8_t reg_msdc2_vrf18_req_mask_b;
+	uint8_t reg_msdc2_ddren_req_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	uint32_t reg_ext_wakeup_event_mask;
+
+	/* SPM_SRC7_MASK */
+	uint8_t reg_pcie_srcclkena_mask_b;
+	uint8_t reg_pcie_infra_req_mask_b;
+	uint8_t reg_pcie_apsrc_req_mask_b;
+	uint8_t reg_pcie_vrf18_req_mask_b;
+	uint8_t reg_pcie_ddren_req_mask_b;
+	uint8_t reg_dpmaif_srcclkena_mask_b;
+	uint8_t reg_dpmaif_infra_req_mask_b;
+	uint8_t reg_dpmaif_apsrc_req_mask_b;
+	uint8_t reg_dpmaif_vrf18_req_mask_b;
+	uint8_t reg_dpmaif_ddren_req_mask_b;
+
+	/* Auto-gen End */
+};
+
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+
+	/* SPM_SRC6_MASK */
+	PW_REG_CCIF_EVENT_INFRA_REQ_MASK_B,
+	PW_REG_CCIF_EVENT_APSRC_REQ_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_SENS */
+	PW_REG_WAKEUP_EVENT_SENS,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDREN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+
+	/* SPM_SRC_MASK */
+	PW_REG_MD_0_SRCCLKENA_MASK_B,
+	PW_REG_MD_0_INFRA_REQ_MASK_B,
+	PW_REG_MD_0_APSRC_REQ_MASK_B,
+	PW_REG_MD_0_VRF18_REQ_MASK_B,
+	PW_REG_MD_0_DDREN_REQ_MASK_B,
+	PW_REG_MD_1_SRCCLKENA_MASK_B,
+	PW_REG_MD_1_INFRA_REQ_MASK_B,
+	PW_REG_MD_1_APSRC_REQ_MASK_B,
+	PW_REG_MD_1_VRF18_REQ_MASK_B,
+	PW_REG_MD_1_DDREN_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_CONN_DDREN_REQ_MASK_B,
+	PW_REG_CONN_VFE28_MASK_B,
+	PW_REG_SRCCLKENI_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI_INFRA_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDREN_REQ_MASK_B,
+	PW_REG_SSPM_SRCCLKENA_MASK_B,
+	PW_REG_SSPM_INFRA_REQ_MASK_B,
+	PW_REG_SSPM_APSRC_REQ_MASK_B,
+	PW_REG_SSPM_VRF18_REQ_MASK_B,
+	PW_REG_SSPM_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC2_MASK */
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDREN_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDREN_REQ_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDREN_REQ_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDREN_REQ_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDREN_REQ_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GCE_DDREN_REQ_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_APU_DDREN_REQ_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC3_MASK */
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_SW2SPM_WAKEUP_MASK_B,
+	PW_REG_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRUP_ACK_MASK,
+	PW_REG_SPM_RESERVED_SRCCLKENA_MASK_B,
+	PW_REG_SPM_RESERVED_INFRA_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_APSRC_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_VRF18_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_DDREN_REQ_MASK_B,
+	PW_REG_MCUPM_SRCCLKENA_MASK_B,
+	PW_REG_MCUPM_INFRA_REQ_MASK_B,
+	PW_REG_MCUPM_APSRC_REQ_MASK_B,
+	PW_REG_MCUPM_VRF18_REQ_MASK_B,
+	PW_REG_MCUPM_DDREN_REQ_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDREN_REQ_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC4_MASK */
+	PW_REG_CCIF_EVENT_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+	PW_REG_BAK_PSRI_DDREN_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+	PW_REG_DRAMC_MD32_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC5_MASK */
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDREN_REQ_MASK_B,
+	PW_REG_AFE_SRCCLKENA_MASK_B,
+	PW_REG_AFE_INFRA_REQ_MASK_B,
+	PW_REG_AFE_APSRC_REQ_MASK_B,
+	PW_REG_AFE_VRF18_REQ_MASK_B,
+	PW_REG_AFE_DDREN_REQ_MASK_B,
+	PW_REG_MSDC2_SRCCLKENA_MASK_B,
+	PW_REG_MSDC2_INFRA_REQ_MASK_B,
+	PW_REG_MSDC2_APSRC_REQ_MASK_B,
+	PW_REG_MSDC2_VRF18_REQ_MASK_B,
+	PW_REG_MSDC2_DDREN_REQ_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+	/* SPM_SRC7_MASK */
+	PW_REG_PCIE_SRCCLKENA_MASK_B,
+	PW_REG_PCIE_INFRA_REQ_MASK_B,
+	PW_REG_PCIE_APSRC_REQ_MASK_B,
+	PW_REG_PCIE_VRF18_REQ_MASK_B,
+	PW_REG_PCIE_DDREN_REQ_MASK_B,
+	PW_REG_DPMAIF_SRCCLKENA_MASK_B,
+	PW_REG_DPMAIF_INFRA_REQ_MASK_B,
+	PW_REG_DPMAIF_APSRC_REQ_MASK_B,
+	PW_REG_DPMAIF_VRF18_REQ_MASK_B,
+	PW_REG_DPMAIF_DDREN_REQ_MASK_B,
+
+
+
+	PW_MAX_COUNT,
+};
+
+
+#endif /* __PWR_CTRL_H__ */

drivers/misc/mediatek/lpm/modules/include/mt6781/mt6781_spm_comm.h

@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+
+#ifndef __MT6781_SPM_COMM_H__
+#define __MT6781_SPM_COMM_H__
+
+struct mt6781_spm_wake_status {
+	u32 r12;			/* SPM_BK_WAKE_EVENT */
+	u32 r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	u32 raw_sta;		/* SPM_WAKEUP_STA */
+	u32 raw_ext_sta;	/* SPM_WAKEUP_EXT_STA */
+	u32 md32pcm_wakeup_sta;/* MD32CPM_WAKEUP_STA */
+	u32 md32pcm_event_sta;/* MD32PCM_EVENT_STA */
+	u32 wake_misc;		/* SPM_BK_WAKE_MISC */
+	u32 timer_out;		/* SPM_BK_PCM_TIMER */
+	u32 r13;			/* PCM_REG13_DATA */
+	u32 idle_sta;		/* SUBSYS_IDLE_STA */
+	u32 req_sta0;		/* SRC_REQ_STA_0 */
+	u32 req_sta1;		/* SRC_REQ_STA_1 */
+	u32 req_sta2;		/* SRC_REQ_STA_2 */
+	u32 req_sta3;		/* SRC_REQ_STA_3 */
+	u32 req_sta4;		/* SRC_REQ_STA_4 */
+	u32 cg_check_sta;	/* SPM_CG_CHECK_STA */
+	u32 debug_flag;		/* PCM_WDT_LATCH_SPARE_0 */
+	u32 debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	u32 b_sw_flag0;		/* SPM_SW_RSV_7 */
+	u32 b_sw_flag1;		/* SPM_SW_RSV_8 */
+	u32 isr;			/* SPM_IRQ_STA */
+	u32 sw_flag0;		/* SPM_SW_FLAG_0 */
+	u32 sw_flag1;		/* SPM_SW_FLAG_1 */
+	u32 clk_settle;		/* SPM_CLK_SETTLE */
+	u32 src_req;	/* SPM_SRC_REQ */
+	u32 log_index;
+	u32 is_abort;
+	u32 rt_req_sta0; /* SPM_SW_RSV_2 */
+	u32 rt_req_sta1; /* SPM_SW_RSV_3 */
+	u32 rt_req_sta2; /* SPM_SW_RSV_4 */
+	u32 rt_req_sta3; /* SPM_SW_RSV_5 */
+	u32 rt_req_sta4; /* SPM_SW_RSV_6 */
+	u32 mcupm_req_sta;
+	u32 gpio200_datain;
+};
+
+struct spm_wakesrc_irq_list {
+	unsigned int wakesrc;
+	const char *name;
+	int order;
+	unsigned int irq_no;
+};
+
+
+enum MTK_LPM_SUSPEND_TYPE {
+	MTK_LPM_SUSPEND_SYSTEM,
+	MTK_LPM_SUSPEND_S2IDLE,
+};
+
+/* MD sleep status */
+
+struct md_sleep_status {
+	u64 sleep_wall_clk;
+	u64 sleep_cnt;
+	u64 sleep_cnt_reserve;
+	u64 sleep_time; // 32k
+	u64 sleep_time_reserve;
+	u64 md_sleep_time; // uS
+	u64 gsm_sleep_time; // uS
+	u64 wcdma_sleep_time; //uS
+	u64 lte_sleep_time; // uS
+	u64 nr_sleep_time; // uS
+};
+
+
+#define MTK_LP_PREPARE_FAIL		(1<<4L)
+
+/* Determine for operand bit */
+
+#define MTK_DUMP_LP_GOLDEN	(1 << 0L)
+#define MTK_DUMP_GPIO		(1 << 1L)
+#define PCM_32K_TICKS_PER_SEC	(32768)
+#define PCM_TICK_TO_SEC(TICK)	(TICK / PCM_32K_TICKS_PER_SEC)
+extern void mtk_suspend_gpio_dbg(void);
+extern void mtk_suspend_clk_dbg(void);
+extern u32 mt_irq_get_pending(unsigned int irq);
+extern u64 spm_26M_off_count;
+extern u64 spm_26M_off_duration;
+extern u64 ap_pd_count;
+extern u64 ap_slp_duration;
+int mtk_lpm_suspend_type_get(void);
+
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN              (1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN            (1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN           (1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS            (1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS            (1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO      (1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF          (1U << 6)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF           (1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH         (1U << 8)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND       (1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO          (1U << 10)
+#define SPM_FLAG_SSPM_INFRA_SLEEP_MODE        (1U << 11)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP      (1U << 12)
+#define SPM_FLAG_USE_SRCCLKENO2               (1U << 13)
+#define SPM_FLAG_RESERVED_BIT14               (1U << 14)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND        (1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP         (1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP      (1U << 17)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP     (1U << 18)
+#define SPM_FLAG_RESERVED_BIT19               (1U << 19)
+#define SPM_FLAG_RESERVED_BIT20               (1U << 20)
+#define SPM_FLAG_RESERVED_BIT21               (1U << 21)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
+#define SPM_FLAG_DISABLE_SRAM_EVENT           (1U << 23)
+#define SPM_FLAG_RESERVED_BIT24               (1U << 24)
+#define SPM_FLAG_RESERVED_BIT25               (1U << 25)
+#define SPM_FLAG_RESERVED_BIT26               (1U << 26)
+#define SPM_FLAG_DDREN_STATE                  (1U << 27)
+#define SPM_FLAG_VTCXO_STATE                  (1U << 28)
+#define SPM_FLAG_INFRA_STATE                  (1U << 29)
+#define SPM_FLAG_VRF18_STATE                  (1U << 30)
+#define SPM_FLAG_APSRC_STATE                  (1U << 31)
+#define SPM_FLAG_SYSTEM_POWER_STATE           (1U << 28)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M      (1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF          (1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH    (1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF          (1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON            (1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5               (1U << 5)
+#define SPM_FLAG1_ENABLE_REKICK               (1U << 6)
+#define SPM_FLAG1_RESERVED_BIT7               (1U << 7)
+#define SPM_FLAG1_RESERVED_BIT8               (1U << 8)
+#define SPM_FLAG1_RESERVED_BIT9               (1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW         (1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH      (1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12              (1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13              (1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14              (1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15              (1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16              (1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17              (1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18              (1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19              (1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP   (1U << 20)
+#define SPM_FLAG1_RESERVED_BIT21              (1U << 21)
+#define SPM_FLAG1_RESERVED_BIT22              (1U << 22)
+#define SPM_FLAG1_RESERVED_BIT23              (1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL   (1U << 24)
+#define SPM_FLAG1_RESERVED_BIT25              (1U << 25)
+#define SPM_FLAG1_RESERVED_BIT26              (1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27              (1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28              (1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29              (1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30              (1U << 30)
+#define SPM_FLAG1_ENABLE_MCUPM_OFF            (1U << 31)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE            (1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP           (1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE          (1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP         (1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE          (1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP         (1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE          (1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP         (1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE          (1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP         (1U << 9)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC    (1U << 10)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE    (1U << 11)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE     (1U << 12)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN    (1U << 13)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE   (1U << 14)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP          (1U << 15)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON           (1U << 16)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP      (1U << 17)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON       (1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP       (1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON        (1U << 20)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP    (1U << 21)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON    (1U << 22)
+/*
+ * #define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V    (1U << 23)
+ * #define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V    (1U << 24)
+ * #define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V    (1U << 25)
+ * #define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V    (1U << 26)
+ */
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP_ABORT   (1U << 23)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW   (1U << 27)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE         (1U << 28)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE         (1U << 29)
+#define SPM_DBG_DEBUG_IDX_VRR18_STATE         (1U << 30)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE         (1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP      (1U << 0)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START   (1U << 1)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF         (1U << 2)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON          (1U << 3)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS   (1U << 4)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF   (1U << 5)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON    (1U << 6)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT  (1U << 7)
+#define SPM_DBG1_RESERVED_BIT8                (1U << 8)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC   (1U << 11)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M   (1U << 12)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K     (1U << 13)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M     (1U << 14)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF        (1U << 15)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON         (1U << 16)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW       (1U << 17)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH      (1U << 18)
+#define SPM_DBG1_DEBUG_IDX_MCUPM_WAKE_IRQ     (1U << 19)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON   (1U << 20)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT   (1U << 23)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT   (1U << 24)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT   (1U << 25)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT   (1U << 26)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT   (1U << 27)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT   (1U << 28)
+#define SPM_DBG1_DEBUG_IDX_SPM_TIMER_RST_DVFS       (1U << 29)
+#define SPM_DBG1_DEBUG_IDX_SPM_DISABLE_DDREN_EVENT  (1U << 30)
+#define MCUPM_RESTORE				    (1U << 31)
+
+
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC \
+	| SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN \
+	| SPM_DBG_DEBUG_IDX_APSRC_SLEEP_ABORT)
+
+#define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6781/mtk_lp_plat_apmcu.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+#ifndef __MTK_LP_PLAT_APMCU_H__
+#define __MTK_LP_PLAT_APMCU_H__
+
+#include <linux/types.h>
+
+#define nr_cluster_ids                  (1)
+#define get_physical_cluster_id(cpu)    (0)
+
+#define LP_PM_SYSRAM_INFO_OFS  0x8
+#define LP_PM_SYSRAM_SIZE      0x500
+
+extern void __iomem *cpu_pm_syssram_base;
+/* 0x11B000 */
+#define MT_CPU_PM_KERNEL_SRAMBASE	(cpu_pm_syssram_base + 0x100)
+#define MT_CPU_PM_KERNEL_SRAM(slot)	(MT_CPU_PM_KERNEL_SRAMBASE + (slot<<2))
+
+
+#define cpu_pm_sync_writel(v, a)				\
+do {								\
+	__raw_writel((v), (void __force __iomem *)((a)));	\
+	mb(); /*make sure register access in order */		\
+} while (0)
+
+#define MT_CPU_PM_KERNEL_SRAM_WR(slot, val) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			cpu_pm_sync_writel(val,\
+				MT_CPU_PM_KERNEL_SRAM(slot)); uval; })
+
+
+#define MT_CPU_PM_KERNEL_SRAM_RD(slot) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			uval = __raw_readl(MT_CPU_PM_KERNEL_SRAM(slot));\
+		uval; })
+
+void mtk_lp_plat_set_mcusys_off(int cpu);
+void mtk_lp_plat_clr_mcusys_off(int cpu);
+
+void mtk_lp_plat_set_cluster_off(int cpu);
+void mtk_lp_plat_clr_cluster_off(int cpu);
+
+bool mtk_lp_plat_is_mcusys_off(void);
+bool mtk_lp_plat_is_cluster_off(int cpu);
+
+int mtk_lp_plat_apmcu_init(void);
+int mtk_lp_plat_apmcu_early_init(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6781/mtk_lp_plat_apmcu_mbox.h

@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_LP_PLAT_APMCU_MBOX_H__
+#define __MTK_LP_PLAT_APMCU_MBOX_H__
+
+enum {
+	MBOX_SSPM,
+	MBOX_MCUPM,
+
+	NF_MBOX,
+};
+
+
+enum APMCU_PM_IPI_UID {
+	APMCU_PM_IPI_PMSR = 0,
+	APMCU_PM_IPI_UID_LPM,
+	APMCU_PM_IPI_UID_MCDI,
+	APMCU_PM_IPI_UID_MAX,
+};
+
+
+/* mcdi ipi id definition */
+enum MCDI_IPI_ID_TLB {
+	MCDI_IPI_SHARE_SRAM_INFO_GET = 0,
+	MCDI_IPI_ID_MAX
+};
+
+#define MCDI_IPI_MAGIC_NUM	0x4d
+
+/* SSPM Mbox */
+#define APMCU_SSPM_MBOX_ID           3
+#define APMCU_SSPM_MBOX_SPM_CMD_SIZE 8
+
+#define APMCU_SSPM_MBOX_SPM_CMD      0
+#define APMCU_SSPM_MBOX_SPM_ARGS1    1
+#define APMCU_SSPM_MBOX_SPM_ARGS2    2
+#define APMCU_SSPM_MBOX_SPM_ARGS3    3
+#define APMCU_SSPM_MBOX_SPM_ARGS4    4
+#define APMCU_SSPM_MBOX_SPM_ARGS5    5
+#define APMCU_SSPM_MBOX_SPM_ARGS6    6
+#define APMCU_SSPM_MBOX_SPM_ARGS7    7
+#define APMCU_SSPM_MBOX_AP_READY     17
+
+
+
+/* MCUPM Mbox */
+
+#define APMCU_MCUPM_MBOX_ID             3
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY       0
+#define APMCU_MCUPM_MBOX_RESERVED_1     1
+#define APMCU_MCUPM_MBOX_RESERVED_2     2
+#define APMCU_MCUPM_MBOX_RESERVED_3     3
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN    4
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE  5
+#define APMCU_MCUPM_MBOX_BUCK_MODE      6
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE    7
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA       8
+#define APMCU_MCUPM_MBOX_RESERVED_9     9
+#define APMCU_MCUPM_MBOX_RESERVED_10    10
+#define APMCU_MCUPM_MBOX_RESERVED_11    11
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU     12
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN (4) */
+#define MCUPM_MCUSYS_CTRL               (1 << 0)
+#define MCUPM_BUCK_CTRL                 (1 << 1)
+#define MCUPM_ARMPLL_CTRL               (1 << 2)
+#define MCUPM_CM_CTRL                   (1 << 3)
+#define MCUPM_PWR_CTRL_MASK             ((1 << 4) - 1)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_L3_CACHE_MODE (5) */
+#define MCUPM_L3_OFF_MODE               0 /* default */
+#define MCUPM_L3_DORMANT_MODE           1
+#define NF_MCUPM_L3_MODE                2U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE (6) */
+#define MCUPM_BUCK_NORMAL_MODE          0 /* default */
+#define MCUPM_BUCK_LP_MODE              1
+#define MCUPM_BUCK_OFF_MODE             2
+#define NF_MCUPM_BUCK_MODE              3U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE (7) */
+#define MCUPM_ARMPLL_ON                 0 /* default */
+#define MCUPM_ARMPLL_GATING             1
+#define MCUPM_ARMPLL_OFF                2
+#define NF_MCUPM_ARMPLL_MODE            3U
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA (9) */
+#define MCUPM_TASK_UNINIT               0
+#define MCUPM_TASK_INIT                 1
+#define MCUPM_TASK_INIT_FINISH          2
+#define MCUPM_TASK_WAIT                 3
+#define MCUPM_TASK_RUN                  4
+#define MCUPM_TASK_PAUSE                5
+
+bool mtk_lp_apmcu_cm_is_notified(void);
+
+void mtk_set_lp_apmcu_pll_mode(unsigned int mode);
+int mtk_get_lp_apmcu_pll_mode(void);
+
+void mtk_set_lp_apmcu_buck_mode(unsigned int mode);
+int mtk_get_lp_apmcu_buck_mode(void);
+
+void mtk_set_preferred_cpu_wakeup(int cpu);
+int mtk_get_preferred_cpu_wakeup(void);
+
+bool mtk_lp_apmcu_is_ready(void);
+
+void mtk_wait_mbox_init_done(void);
+void mtk_notify_subsys_ap_ready(void);
+
+int mtk_apmcu_mbox_init(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6781/mtk_lp_plat_reg.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef __MTK_PLAT_CPC_REG_H__
+#define __MTK_PLAT_CPC_REG_H__
+
+/**************************************
+ * CPC related register
+ * base address = 0x0C53A000
+ **************************************/
+#define CPC_FLOW_CTRL_CFG              (0x814)
+#define CPC_MCUSYS_LAST_CORE_REQ       (0x818)
+#define CPC_CPUSYS_LAST_CORE_RESP      (0x81C)
+#define CPC_MCUSYS_LAST_CORE_RESP      (0x824)
+#define CPC_PWR_ON_MASK                (0x828)
+#define CPC_SPMC_PWR_STATUS            (0x840)
+#define CPC_CPUSYS_CPU_ON_SW_HINT_CLR  (0x8AC)
+
+#define SPMC_DBG_SETTING               (0xB00)
+
+#define CPC_TRACE_DATA_SEL             (0xB14)
+
+#define CPC_CPU0_LATENCY               (0xB40)
+#define CPC_CPU1_LATENCY               (0xB44)
+#define CPC_CPU2_LATENCY               (0xB48)
+#define CPC_CPU3_LATENCY               (0xB4C)
+#define CPC_CPU4_LATENCY               (0xB50)
+#define CPC_CPU5_LATENCY               (0xB54)
+#define CPC_CPU6_LATENCY               (0xB58)
+#define CPC_CPU7_LATENCY               (0xB5C)
+#define CPC_CLUSTER_OFF_LATENCY        (0xB60)
+#define CPC_CLUSTER_ON_LATENCY         (0xB64)
+#define CPC_MCUSYS_LATENCY             (0xB68)
+#define CPC_DORMANT_COUNTER            (0xB70)
+#define CPC_DORMANT_COUNTER_CLR        (0xB74)
+#define CPC_CPU_LATENCY(cpu)           ((CPC_CPU0_LATENCY) + 4 * (cpu))
+
+/**************************************
+ * system sram for apmcu debug
+ * base address = 0x0011B000
+ **************************************/
+#define SYSRAM_CPUSYS_CNT              (0x1E8)
+#define SYSRAM_MCUSYS_CNT              (0x1EC)
+#define SYSRAM_CPC_CPUSYS_CNT_BACKUP   (0x1F0)
+#define SYSRAM_MCUPM_MCUSYS_COUNTER    (0x1F4)
+#define SYSRAM_CPU_ONLINE              (0x1F8)
+
+/* Run time information. The registers may be cleared in db dump flow */
+#define SYSRAM_RECENT_CPU_CNT(i)       (4 * (i) + 0x1B0)
+#define SYSRAM_RECENT_CPUSYS_CNT       (0x1D0)
+#define SYSRAM_RECENT_MCUSYS_CNT       (0x1D4)
+#define SYSRAM_RECENT_CNT_TS_L         (0x1D8)
+#define SYSRAM_RECENT_CNT_TS_H         (0x1DC)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6781/mtk_power_gs_array.h

@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+#ifndef MTK_POWER_GS_ARRAY_H
+#define MTK_POWER_GS_ARRAY_H
+
+extern void mt_power_gs_sp_dump(void);
+extern unsigned int golden_read_reg(unsigned int addr);
+
+/* PMIC 6366 */
+extern const unsigned int *AP_PMIC_REG_6366_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_6366_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_6366_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_6366_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_6366_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_6366_gs_suspend_32kless_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_dpidle;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_dpidle_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_suspend;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_suspend_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_sodi;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_sodi_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_dpidle;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_dpidle_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_suspend;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_suspend_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_sodi;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_sodi_len;
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6833/mt6833_cond.h

@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MT6833_COND_H__
+#define __MT6833_COND_H__
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]    : idle condition check fail
+ */
+
+#define SPM_COND_BLOCKED_CG_IDX		(0)
+#define SPM_COND_BLOCKED_PLL_IDX	(16)
+#define SPM_COND_BLOCKED_PLL		(1<<30L)
+#define SPM_COND_CHECK_FAIL		(1<<31L)
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS_0 = 0,
+	PLAT_SPM_COND_CG_INFRA_0,
+	PLAT_SPM_COND_CG_INFRA_1,
+	PLAT_SPM_COND_CG_INFRA_2,
+	PLAT_SPM_COND_CG_INFRA_3,
+	PLAT_SPM_COND_CG_INFRA_4,
+	PLAT_SPM_COND_CG_INFRA_5,
+	PLAT_SPM_COND_CG_MMSYS_0,
+	PLAT_SPM_COND_CG_MMSYS_1,
+	PLAT_SPM_COND_CG_MMSYS_2,
+	PLAT_SPM_COND_CG_MMSYS_3,
+	PLAT_SPM_COND_MAX,
+};
+
+enum PLAT_SPM_PLL_COND {
+	PLAT_SPM_COND_UNIVPLL = 0,
+	PLAT_SPM_COND_MFGPLL,
+	PLAT_SPM_COND_MSDCPLL,
+	PLAT_SPM_COND_TVPLL,
+	PLAT_SPM_COND_MMPLL,
+	PLAT_SPM_COND_PLL_MAX,
+};
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6833/mt6833_pcm_def.h

@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __pcm_def_h__
+#define __pcm_def_h__
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF                      (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN               (1U << 1)
+#define R0_SC_MEM_CK_OFF                      (1U << 2)
+#define R0_SC_AXI_CK_OFF                      (1U << 3)
+#define R0_SC_DR_SRAM_LOAD                    (1U << 4)
+#define R0_SC_MD26M_CK_OFF                    (1U << 5)
+#define R0_SC_DPY_MODE_SW                     (1U << 6)
+#define R0_SC_DMSUS_OFF                       (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN                  (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE                 (1U << 9)
+#define R0_SC_MPLLOUT_OFF                     (1U << 10)
+#define R0_SC_TX_TRACKING_DIS                 (1U << 11)
+#define R0_SC_DPY_DLL_EN                      (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN                   (1U << 13)
+#define R0_SC_DPY_VREF_EN                     (1U << 14)
+#define R0_SC_PHYPLL_EN                       (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN                 (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE                 (1U << 17)
+#define R0_SC_MPLL_OFF                        (1U << 18)
+#define R0_SC_SHU_RESTORE                     (1U << 19)
+#define R0_SC_CKSQ0_OFF                       (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH         (1U << 21)
+#define R0_SC_DR_SHU_EN                       (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP                  (1U << 23)
+#define R0_SC_MPLL_S_OFF                      (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN             (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN                   (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN                  (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW                  (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW                 (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0                   (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1                   (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ                    (1U << 0)
+#define R7_EMI_CLK_OFF_REQ                    (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ                (1U << 2)
+#define R7_SPM_CK_UPDATE                      (1U << 3)
+#define R7_SPM_CK_SEL0                        (1U << 4)
+#define R7_SPM_CK_SEL1                        (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ             (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL                  (1U << 7)
+#define R7_SC_26M_CK_SEL                      (1U << 8)
+#define R7_PCM_TIMER_SET                      (1U << 9)
+#define R7_PCM_TIMER_CLR                      (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ              (1U << 11)
+#define R7_CSYSPWRUPACK                       (1U << 12)
+#define R7_PCM_IM_SLP_EN                      (1U << 13)
+#define R7_SRCCLKENO0                         (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE                  (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK             (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL              (1U << 17)
+#define R7_SC_AXI_DCM_DIS                     (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM                   (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN                  (1U << 20)
+#define R7_SRCCLKENO1                         (1U << 21)
+#define R7_PCM_WDT_KICK_P                     (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC              (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM                 (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM           (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN                    (1U << 26)
+#define R7_FORCE_F26M_WAKE                    (1U << 27)
+#define R7_FORCE_APSRC_WAKE                   (1U << 28)
+#define R7_FORCE_INFRA_WAKE                   (1U << 29)
+#define R7_FORCE_VRF18_WAKE                   (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK            (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER                         (1U << 0)
+#define R12_TWAM_IRQ_B                        (1U << 1)
+#define R12_KP_IRQ_B                          (1U << 2)
+#define R12_APWDT_EVENT_B                     (1U << 3)
+#define R12_APXGPT1_EVENT_B                   (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B              (1U << 5)
+#define R12_EINT_EVENT_B                      (1U << 6)
+#define R12_CONN_WDT_IRQ_B                    (1U << 7)
+#define R12_CCIF0_EVENT_B                     (1U << 8)
+#define R12_LOWBATTERY_IRQ_B                  (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B                 (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B                  (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B                 (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B                  (1U << 13)
+#define R12_USBX_CDSC_B                       (1U << 14)
+#define R12_USBX_POWERDWN_B                   (1U << 15)
+#define R12_SYS_TIMER_EVENT_B                 (1U << 16)
+#define R12_EINT_EVENT_SECURE_B               (1U << 17)
+#define R12_CCIF1_EVENT_B                     (1U << 18)
+#define R12_UART0_IRQ_B                       (1U << 19)
+#define R12_AFE_IRQ_MCU_B                     (1U << 20)
+#define R12_THERM_CTRL_EVENT_B                (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B                    (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B                (1U << 23)
+#define R12_CSYSPWREQ_B                       (1U << 24)
+#define R12_MD1_WDT_B                         (1U << 25)
+#define R12_CLDMA_EVENT_B                     (1U << 26)
+#define R12_SEJ_EVENT_B                       (1U << 27)
+#define R12_REG_CPU_WAKEUP                    (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B                (1U << 29)
+#define R12_PCIE_BRIDGE_IRQ                   (1U << 30)
+#define R12_PCIE_IRQ                          (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE                       (1U << 0)
+#define R12EXT_26M_SLEEP                      (1U << 1)
+#define R12EXT_INFRA_WAKE                     (1U << 2)
+#define R12EXT_INFRA_SLEEP                    (1U << 3)
+#define R12EXT_APSRC_WAKE                     (1U << 4)
+#define R12EXT_APSRC_SLEEP                    (1U << 5)
+#define R12EXT_VRF18_WAKE                     (1U << 6)
+#define R12EXT_VRF18_SLEEP                    (1U << 7)
+#define R12EXT_DVFS_WAKE                      (1U << 8)
+#define R12EXT_DDREN_WAKE                     (1U << 9)
+#define R12EXT_DDREN_SLEEP                    (1U << 10)
+#define R12EXT_MCU_PM_WFI                     (1U << 11)
+#define R12EXT_SSPM_IDLE                      (1U << 12)
+#define R12EXT_CONN_SRCCLKENB                 (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE           (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE                (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE              (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE              (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE               (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK          (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK         (1U << 20)
+#define R12EXT_BIT21                          (1U << 21)
+#define R12EXT_BIT22                          (1U << 22)
+#define R12EXT_BIT23                          (1U << 23)
+#define R12EXT_BIT24                          (1U << 24)
+#define R12EXT_BIT25                          (1U << 25)
+#define R12EXT_BIT26                          (1U << 26)
+#define R12EXT_BIT27                          (1U << 27)
+#define R12EXT_BIT28                          (1U << 28)
+#define R12EXT_BIT29                          (1U << 29)
+#define R12EXT_BIT30                          (1U << 30)
+#define R12EXT_BIT31                          (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0                        (1U << 0)
+#define R13_SRCCLKENI1                        (1U << 1)
+#define R13_MD_0_SRCCLKENA                    (1U << 2)
+#define R13_MD_0_APSRC_REQ                    (1U << 3)
+#define R13_CONN_DDREN                        (1U << 4)
+#define R13_MD_1_SRCCLKENA                    (1U << 5)
+#define R13_SSPM_SRCCLKENA                    (1U << 6)
+#define R13_SSPM_APSRC_REQ                    (1U << 7)
+#define R13_MD_1_STATE                        (1U << 8)
+#define R13_RC_SRCCLKENO_ACK                  (1U << 9)
+#define R13_MM_STATE                          (1U << 10)
+#define R13_SSPM_STATE                        (1U << 11)
+#define R13_MD_0_DDREN                        (1U << 12)
+#define R13_CONN_STATE                        (1U << 13)
+#define R13_CONN_SRCCLKENA                    (1U << 14)
+#define R13_CONN_APSRC_REQ                    (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL                (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL          (1U << 17)
+#define R13_SCP_STATE                         (1U << 18)
+#define R13_CSYSPWRUPREQ                      (1U << 19)
+#define R13_PWRAP_SLEEP_ACK                   (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL            (1U << 21)
+#define R13_AUDIO_DSP_STATE                   (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL             (1U << 23)
+#define R13_CONN_SRCCLKENB                    (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL           (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0              (1U << 26)
+#define R13_DVFS_STATE                        (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL       (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL        (1U << 29)
+#define R13_MD_0_VRF18_REQ                    (1U << 30)
+#define R13_DDR_EN_STATE                      (1U << 31)
+
+
+enum SPM_WAKE_SRC_LIST {
+	WAKE_SRC_STA1_PCM_TIMER = (1U << 0),
+	WAKE_SRC_STA1_RESERVED_DEBUG_B = (1U << 1),
+	WAKE_SRC_STA1_KP_IRQ_B = (1U << 2),
+	WAKE_SRC_STA1_APWDT_EVENT_B = (1U << 3),
+	WAKE_SRC_STA1_APXGPT1_EVENT_B = (1U << 4),
+	WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B = (1U << 5),
+	WAKE_SRC_STA1_EINT_EVENT_B = (1U << 6),
+	WAKE_SRC_STA1_CONN_WDT_IRQ_B = (1U << 7),
+	WAKE_SRC_STA1_CCIF0_EVENT_B = (1U << 8),
+	WAKE_SRC_STA1_LOWBATTERY_IRQ_B = (1U << 9),
+	WAKE_SRC_STA1_SC_SSPM2SPM_WAKEUP_B = (1U << 10),
+	WAKE_SRC_STA1_SC_SCP2SPM_WAKEUP_B = (1U << 11),
+	WAKE_SRC_STA1_SC_ADSP2SPM_WAKEUP_B = (1U << 12),
+	WAKE_SRC_STA1_PCM_WDT_WAKEUP_B = (1U << 13),
+	WAKE_SRC_STA1_USB_CDSC_B = (1U << 14),
+	WAKE_SRC_STA1_USB_POWERDWN_B = (1U << 15),
+	WAKE_SRC_STA1_SYS_TIMER_EVENT_B = (1U << 16),
+	WAKE_SRC_STA1_EINT_EVENT_SECURE_B = (1U << 17),
+	WAKE_SRC_STA1_CCIF1_EVENT_B = (1U << 18),
+	WAKE_SRC_STA1_UART0_IRQ_B = (1U << 19),
+	WAKE_SRC_STA1_AFE_IRQ_MCU_B = (1U << 20),
+	WAKE_SRC_STA1_THERM_CTRL_EVENT_B = (1U << 21),
+	WAKE_SRC_STA1_SYS_CIRQ_IRQ_B = (1U << 22),
+	WAKE_SRC_STA1_MD2AP_PEER_EVENT_B = (1U << 23),
+	WAKE_SRC_STA1_CSYSPWREQ_B = (1U << 24),
+	WAKE_SRC_STA1_MD1_WDT_B = (1U << 25),
+	WAKE_SRC_STA1_AP2AP_PEER_WAKEUPEVENT_B = (1U << 26),
+	WAKE_SRC_STA1_SEJ_EVENT_B = (1U << 27),
+	WAKE_SRC_STA1_SPM_CPU_WAKEUPEVENT_B = (1U << 28),
+	WAKE_SRC_STA1_APUSYS = (1U << 29),
+	WAKE_SRC_STA1_PCIE_BRIDGE_IRQ = (1U << 30),
+	WAKE_SRC_STA1_PCIE_IRQ = (1U << 31)
+};
+
+extern const char *wakesrc_str[32];
+
+/* define WAKE_SRC_CONN2AP for conn use */
+#define WAKE_SRC_CONN2AP WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B
+
+#endif /* __pcm_def_h__ */

drivers/misc/mediatek/lpm/modules/include/mt6833/mt6833_pwr_ctrl.h

@@ -0,0 +1,423 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __PWR_CTRL_H__
+#define __PWR_CTRL_H__
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP              0x3FF  /* bit0 ~ bit9 */
+#define WAKE_MISC_DVFSRC_IRQ	         (1U << 16)
+#define WAKE_MISC_REG_CPU_WAKEUP         (1U << 17)
+#define WAKE_MISC_PCM_TIMER_EVENT        (1U << 18)
+#define WAKE_MISC_PMIC_OUT_B		     ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B             (1U << 21)
+#define WAKE_MISC_PMSR_IRQ_B_SET0        (1U << 22)
+#define WAKE_MISC_PMSR_IRQ_B_SET1        (1U << 23)
+#define WAKE_MISC_PMSR_IRQ_B_SET2        (1U << 24)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0   (1U << 25)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1	 (1U << 26)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2	 (1U << 27)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3	 (1U << 28)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL (1U << 29)
+#define WAKE_MISC_PMIC_IRQ_ACK			 (1U << 30)
+#define WAKE_MISC_PMIC_SCP_IRQ			 (1U << 31)
+
+struct pwr_ctrl {
+
+	/* for SPM */
+	uint32_t pcm_flags;
+	uint32_t pcm_flags_cust;
+	uint32_t pcm_flags_cust_set;
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	uint32_t pcm_flags1_cust;
+	uint32_t pcm_flags1_cust_set;
+	uint32_t pcm_flags1_cust_clr;
+	uint32_t timer_val;
+	uint32_t timer_val_cust;
+	uint32_t timer_val_ramp_en;
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	uint32_t wake_src_cust;
+	uint32_t wakelock_timer_val;
+	uint8_t wdt_disable;
+	/* Auto-gen Start */
+
+	/* SPM_CLK_CON */
+	uint8_t reg_srcclken0_ctl;
+	uint8_t reg_srcclken1_ctl;
+	uint8_t reg_spm_lock_infra_dcm;
+	uint8_t reg_srcclken_mask;
+	uint8_t reg_md1_c32rm_en;
+	uint8_t reg_md2_c32rm_en;
+	uint8_t reg_clksq0_sel_ctrl;
+	uint8_t reg_clksq1_sel_ctrl;
+	uint8_t reg_srcclken0_en;
+	uint8_t reg_srcclken1_en;
+	uint32_t reg_sysclk0_src_mask_b;
+	uint32_t reg_sysclk1_src_mask_b;
+
+	/* SPM_AP_STANDBY_CON */
+	uint8_t reg_wfi_op;
+	uint8_t reg_wfi_type;
+	uint8_t reg_mp0_cputop_idle_mask;
+	uint8_t reg_mp1_cputop_idle_mask;
+	uint8_t reg_mcusys_idle_mask;
+	uint8_t reg_md_apsrc_1_sel;
+	uint8_t reg_md_apsrc_0_sel;
+	uint8_t reg_conn_apsrc_sel;
+
+	/* SPM_SRC6_MASK */
+	uint32_t reg_ccif_event_infra_req_mask_b;
+	uint32_t reg_ccif_event_apsrc_req_mask_b;
+
+	/* SPM_SRC_REQ */
+	uint8_t reg_spm_apsrc_req;
+	uint8_t reg_spm_f26m_req;
+	uint8_t reg_spm_infra_req;
+	uint8_t reg_spm_vrf18_req;
+	uint8_t reg_spm_ddren_req;
+	uint8_t reg_spm_dvfs_req;
+	uint8_t reg_spm_sw_mailbox_req;
+	uint8_t reg_spm_sspm_mailbox_req;
+	uint8_t reg_spm_adsp_mailbox_req;
+	uint8_t reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	uint8_t reg_md_0_srcclkena_mask_b;
+	uint8_t reg_md_0_infra_req_mask_b;
+	uint8_t reg_md_0_apsrc_req_mask_b;
+	uint8_t reg_md_0_vrf18_req_mask_b;
+	uint8_t reg_md_0_ddren_req_mask_b;
+	uint8_t reg_md_1_srcclkena_mask_b;
+	uint8_t reg_md_1_infra_req_mask_b;
+	uint8_t reg_md_1_apsrc_req_mask_b;
+	uint8_t reg_md_1_vrf18_req_mask_b;
+	uint8_t reg_md_1_ddren_req_mask_b;
+	uint8_t reg_conn_srcclkena_mask_b;
+	uint8_t reg_conn_srcclkenb_mask_b;
+	uint8_t reg_conn_infra_req_mask_b;
+	uint8_t reg_conn_apsrc_req_mask_b;
+	uint8_t reg_conn_vrf18_req_mask_b;
+	uint8_t reg_conn_ddren_req_mask_b;
+	uint8_t reg_conn_vfe28_mask_b;
+	uint8_t reg_srcclkeni_srcclkena_mask_b;
+	uint8_t reg_srcclkeni_infra_req_mask_b;
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	uint8_t reg_infrasys_ddren_req_mask_b;
+	uint8_t reg_sspm_srcclkena_mask_b;
+	uint8_t reg_sspm_infra_req_mask_b;
+	uint8_t reg_sspm_apsrc_req_mask_b;
+	uint8_t reg_sspm_vrf18_req_mask_b;
+	uint8_t reg_sspm_ddren_req_mask_b;
+
+	/* SPM_SRC2_MASK */
+	uint8_t reg_scp_srcclkena_mask_b;
+	uint8_t reg_scp_infra_req_mask_b;
+	uint8_t reg_scp_apsrc_req_mask_b;
+	uint8_t reg_scp_vrf18_req_mask_b;
+	uint8_t reg_scp_ddren_req_mask_b;
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	uint8_t reg_audio_dsp_ddren_req_mask_b;
+	uint8_t reg_ufs_srcclkena_mask_b;
+	uint8_t reg_ufs_infra_req_mask_b;
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	uint8_t reg_ufs_vrf18_req_mask_b;
+	uint8_t reg_ufs_ddren_req_mask_b;
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	uint8_t reg_disp0_ddren_req_mask_b;
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	uint8_t reg_disp1_ddren_req_mask_b;
+	uint8_t reg_gce_infra_req_mask_b;
+	uint8_t reg_gce_apsrc_req_mask_b;
+	uint8_t reg_gce_vrf18_req_mask_b;
+	uint8_t reg_gce_ddren_req_mask_b;
+	uint8_t reg_apu_srcclkena_mask_b;
+	uint8_t reg_apu_infra_req_mask_b;
+	uint8_t reg_apu_apsrc_req_mask_b;
+	uint8_t reg_apu_vrf18_req_mask_b;
+	uint8_t reg_apu_ddren_req_mask_b;
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	uint8_t reg_cg_check_ddren_req_mask_b;
+
+	/* SPM_SRC3_MASK */
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+	uint8_t reg_sw2spm_wakeup_mask_b;
+	uint8_t reg_adsp2spm_wakeup_mask_b;
+	uint8_t reg_sspm2spm_wakeup_mask_b;
+	uint8_t reg_scp2spm_wakeup_mask_b;
+	uint8_t reg_csyspwrup_ack_mask;
+	uint8_t reg_spm_reserved_srcclkena_mask_b;
+	uint8_t reg_spm_reserved_infra_req_mask_b;
+	uint8_t reg_spm_reserved_apsrc_req_mask_b;
+	uint8_t reg_spm_reserved_vrf18_req_mask_b;
+	uint8_t reg_spm_reserved_ddren_req_mask_b;
+	uint8_t reg_mcupm_srcclkena_mask_b;
+	uint8_t reg_mcupm_infra_req_mask_b;
+	uint8_t reg_mcupm_apsrc_req_mask_b;
+	uint8_t reg_mcupm_vrf18_req_mask_b;
+	uint8_t reg_mcupm_ddren_req_mask_b;
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	uint8_t reg_msdc0_infra_req_mask_b;
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	uint8_t reg_msdc0_ddren_req_mask_b;
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	uint8_t reg_msdc1_infra_req_mask_b;
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	uint8_t reg_msdc1_ddren_req_mask_b;
+
+	/* SPM_SRC4_MASK */
+	uint32_t reg_ccif_event_srcclkena_mask_b;
+	uint8_t reg_bak_psri_srcclkena_mask_b;
+	uint8_t reg_bak_psri_infra_req_mask_b;
+	uint8_t reg_bak_psri_apsrc_req_mask_b;
+	uint8_t reg_bak_psri_vrf18_req_mask_b;
+	uint8_t reg_bak_psri_ddren_req_mask_b;
+	uint8_t reg_dramc_md32_infra_req_mask_b;
+	uint8_t reg_dramc_md32_vrf18_req_mask_b;
+	uint8_t reg_conn_srcclkenb2pwrap_mask_b;
+	uint8_t reg_dramc_md32_apsrc_req_mask_b;
+
+	/* SPM_SRC5_MASK */
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	uint32_t reg_mcusys_merge_ddren_req_mask_b;
+	uint8_t reg_afe_srcclkena_mask_b;
+	uint8_t reg_afe_infra_req_mask_b;
+	uint8_t reg_afe_apsrc_req_mask_b;
+	uint8_t reg_afe_vrf18_req_mask_b;
+	uint8_t reg_afe_ddren_req_mask_b;
+	uint8_t reg_msdc2_srcclkena_mask_b;
+	uint8_t reg_msdc2_infra_req_mask_b;
+	uint8_t reg_msdc2_apsrc_req_mask_b;
+	uint8_t reg_msdc2_vrf18_req_mask_b;
+	uint8_t reg_msdc2_ddren_req_mask_b;
+
+	/* SPM_SRC7_MASK */
+	uint8_t reg_pcie_srcclkena_mask_b;
+	uint8_t reg_pcie_infra_req_mask_b;
+	uint8_t reg_pcie_apsrc_req_mask_b;
+	uint8_t reg_pcie_vrf18_req_mask_b;
+	uint8_t reg_pcie_ddren_req_mask_b;
+	uint8_t reg_dpmaif_srcclkena_mask_b;
+	uint8_t reg_dpmaif_infra_req_mask_b;
+	uint8_t reg_dpmaif_apsrc_req_mask_b;
+	uint8_t reg_dpmaif_vrf18_req_mask_b;
+	uint8_t reg_dpmaif_ddren_req_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	uint32_t reg_ext_wakeup_event_mask;
+
+	/* Auto-gen End */
+};
+
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+
+	/* SPM_CLK_CON */
+	PW_REG_SRCCLKEN0_CTL,
+	PW_REG_SRCCLKEN1_CTL,
+	PW_REG_SPM_LOCK_INFRA_DCM,
+	PW_REG_SRCCLKEN_MASK,
+	PW_REG_MD1_C32RM_EN,
+	PW_REG_MD2_C32RM_EN,
+	PW_REG_CLKSQ0_SEL_CTRL,
+	PW_REG_CLKSQ1_SEL_CTRL,
+	PW_REG_SRCCLKEN0_EN,
+	PW_REG_SRCCLKEN1_EN,
+	PW_REG_SYSCLK0_SRC_MASK_B,
+	PW_REG_SYSCLK1_SRC_MASK_B,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+
+	/* SPM_SRC6_MASK */
+	PW_REG_CCIF_EVENT_INFRA_REQ_MASK_B,
+	PW_REG_CCIF_EVENT_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDREN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+
+	/* SPM_SRC_MASK */
+	PW_REG_MD_0_SRCCLKENA_MASK_B,
+	PW_REG_MD_0_INFRA_REQ_MASK_B,
+	PW_REG_MD_0_APSRC_REQ_MASK_B,
+	PW_REG_MD_0_VRF18_REQ_MASK_B,
+	PW_REG_MD_0_DDREN_REQ_MASK_B,
+	PW_REG_MD_1_SRCCLKENA_MASK_B,
+	PW_REG_MD_1_INFRA_REQ_MASK_B,
+	PW_REG_MD_1_APSRC_REQ_MASK_B,
+	PW_REG_MD_1_VRF18_REQ_MASK_B,
+	PW_REG_MD_1_DDREN_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_CONN_DDREN_REQ_MASK_B,
+	PW_REG_CONN_VFE28_MASK_B,
+	PW_REG_SRCCLKENI_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI_INFRA_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDREN_REQ_MASK_B,
+	PW_REG_SSPM_SRCCLKENA_MASK_B,
+	PW_REG_SSPM_INFRA_REQ_MASK_B,
+	PW_REG_SSPM_APSRC_REQ_MASK_B,
+	PW_REG_SSPM_VRF18_REQ_MASK_B,
+	PW_REG_SSPM_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC2_MASK */
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDREN_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDREN_REQ_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDREN_REQ_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDREN_REQ_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDREN_REQ_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GCE_DDREN_REQ_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_APU_DDREN_REQ_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC3_MASK */
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_SW2SPM_WAKEUP_MASK_B,
+	PW_REG_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRUP_ACK_MASK,
+	PW_REG_SPM_RESERVED_SRCCLKENA_MASK_B,
+	PW_REG_SPM_RESERVED_INFRA_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_APSRC_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_VRF18_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_DDREN_REQ_MASK_B,
+	PW_REG_MCUPM_SRCCLKENA_MASK_B,
+	PW_REG_MCUPM_INFRA_REQ_MASK_B,
+	PW_REG_MCUPM_APSRC_REQ_MASK_B,
+	PW_REG_MCUPM_VRF18_REQ_MASK_B,
+	PW_REG_MCUPM_DDREN_REQ_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDREN_REQ_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC4_MASK */
+	PW_REG_CCIF_EVENT_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+	PW_REG_BAK_PSRI_DDREN_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+	PW_REG_DRAMC_MD32_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC5_MASK */
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDREN_REQ_MASK_B,
+	PW_REG_AFE_SRCCLKENA_MASK_B,
+	PW_REG_AFE_INFRA_REQ_MASK_B,
+	PW_REG_AFE_APSRC_REQ_MASK_B,
+	PW_REG_AFE_VRF18_REQ_MASK_B,
+	PW_REG_AFE_DDREN_REQ_MASK_B,
+	PW_REG_MSDC2_SRCCLKENA_MASK_B,
+	PW_REG_MSDC2_INFRA_REQ_MASK_B,
+	PW_REG_MSDC2_APSRC_REQ_MASK_B,
+	PW_REG_MSDC2_VRF18_REQ_MASK_B,
+	PW_REG_MSDC2_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC7_MASK */
+	PW_REG_PCIE_SRCCLKENA_MASK_B,
+	PW_REG_PCIE_INFRA_REQ_MASK_B,
+	PW_REG_PCIE_APSRC_REQ_MASK_B,
+	PW_REG_PCIE_VRF18_REQ_MASK_B,
+	PW_REG_PCIE_DDREN_REQ_MASK_B,
+	PW_REG_DPMAIF_SRCCLKENA_MASK_B,
+	PW_REG_DPMAIF_INFRA_REQ_MASK_B,
+	PW_REG_DPMAIF_APSRC_REQ_MASK_B,
+	PW_REG_DPMAIF_VRF18_REQ_MASK_B,
+	PW_REG_DPMAIF_DDREN_REQ_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+	PW_MAX_COUNT,
+};
+
+
+#endif /* __PWR_CTRL_H__ */

drivers/misc/mediatek/lpm/modules/include/mt6833/mt6833_spm_comm.h

@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MT6833_SPM_COMM_H__
+#define __MT6833_SPM_COMM_H__
+
+struct mt6833_spm_wake_status {
+	u32 r12;			/* SPM_BK_WAKE_EVENT */
+	u32 r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	u32 raw_sta;		/* SPM_WAKEUP_STA */
+	u32 raw_ext_sta;	/* SPM_WAKEUP_EXT_STA */
+	u32 md32pcm_wakeup_sta;/* MD32CPM_WAKEUP_STA */
+	u32 md32pcm_event_sta;/* MD32PCM_EVENT_STA */
+	u32 wake_misc;		/* SPM_BK_WAKE_MISC */
+	u32 timer_out;		/* SPM_BK_PCM_TIMER */
+	u32 r13;			/* PCM_REG13_DATA */
+	u32 idle_sta;		/* SUBSYS_IDLE_STA */
+	u32 req_sta0;		/* SRC_REQ_STA_0 */
+	u32 req_sta1;		/* SRC_REQ_STA_1 */
+	u32 req_sta2;		/* SRC_REQ_STA_2 */
+	u32 req_sta3;		/* SRC_REQ_STA_3 */
+	u32 req_sta4;		/* SRC_REQ_STA_4 */
+	u32 cg_check_sta;	/* SPM_CG_CHECK_STA */
+	u32 debug_flag;		/* PCM_WDT_LATCH_SPARE_0 */
+	u32 debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	u32 b_sw_flag0;		/* SPM_SW_RSV_7 */
+	u32 b_sw_flag1;		/* SPM_SW_RSV_8 */
+	u32 isr;			/* SPM_IRQ_STA */
+	u32 sw_flag0;		/* SPM_SW_FLAG_0 */
+	u32 sw_flag1;		/* SPM_SW_FLAG_1 */
+	u32 clk_settle;		/* SPM_CLK_SETTLE */
+	u32 src_req;	/* SPM_SRC_REQ */
+	u32 log_index;
+	u32 is_abort;
+	u32 rt_req_sta0; /* SPM_SW_RSV_2 */
+	u32 rt_req_sta1; /* SPM_SW_RSV_3 */
+	u32 rt_req_sta2; /* SPM_SW_RSV_4 */
+	u32 rt_req_sta3; /* SPM_SW_RSV_5 */
+	u32 rt_req_sta4; /* SPM_SW_RSV_6 */
+	u32 mcupm_req_sta;
+};
+
+struct spm_wakesrc_irq_list {
+	unsigned int wakesrc;
+	const char *name;
+	int order;
+	unsigned int irq_no;
+};
+
+enum MTK_LPM_SUSPEND_TYPE {
+	MTK_LPM_SUSPEND_SYSTEM,
+	MTK_LPM_SUSPEND_S2IDLE,
+};
+
+/* MD sleep status */
+
+struct md_sleep_status {
+	u64 sleep_wall_clk;
+	u64 sleep_cnt;
+	u64 sleep_cnt_reserve;
+	u64 sleep_time; // 32k
+	u64 sleep_time_reserve;
+	u64 md_sleep_time; // uS
+	u64 gsm_sleep_time; // uS
+	u64 wcdma_sleep_time; //uS
+	u64 lte_sleep_time; // uS
+	u64 nr_sleep_time; // uS
+};
+
+
+#define MTK_LP_PREPARE_FAIL		(1<<4L)
+
+/* Determine for operand bit */
+
+#define MTK_DUMP_LP_GOLDEN	(1 << 0L)
+#define MTK_DUMP_GPIO		(1 << 1L)
+#define PCM_32K_TICKS_PER_SEC	(32768)
+#define PCM_TICK_TO_SEC(TICK)	(TICK / PCM_32K_TICKS_PER_SEC)
+extern void mtk_suspend_gpio_dbg(void);
+extern void mtk_suspend_clk_dbg(void);
+extern u32 mt_irq_get_pending(unsigned int irq);
+extern u64 spm_26M_off_count;
+extern u64 spm_26M_off_duration;
+extern u64 ap_pd_count;
+extern u64 ap_slp_duration;
+int mtk_lpm_suspend_type_get(void);
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ * From Legacy sleep_def.h
+ */
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN		(1 << 0u)
+#define SPM_FLAG_DISABLE_INFRA_PDN		(1 << 1u)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN		(1 << 2u)
+#define SPM_FLAG_DISABLE_VCORE_DVS		(1 << 3u)
+#define SPM_FLAG_DISABLE_VCORE_DFS		(1 << 4u)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO	(1 << 5u)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF		(1 << 6u)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF		(1 << 7u)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH		(1 << 8u)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND		(1 << 9u)
+#define SPM_FLAG_RUN_COMMON_SCENARIO		(1 << 10u)
+#define SPM_FLAG_SSPM_INFRA_SLEEP_MODE		(1 << 11u)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP	(1 << 12u)
+#define SPM_FLAG_USE_SRCCLKENO2			(1 << 13u)
+#define SPM_FLAG_ENABLE_6315_CTRL		(1 << 14u)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND		(1 << 15u)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP		(1 << 16u)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP	(1 << 17u)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP	(1 << 18u)
+#define SPM_FLAG_ENABLE_MD_MUMTAS			(1 << 19u)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN			(1 << 20u)
+#define SPM_FLAG_ENABLE_6362_CTRL			(1 << 21u)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP	(1 << 22u)
+#define SPM_FLAG_DISABLE_SRAM_EVENT			(1 << 23u)
+#define SPM_FLAG_DISABLE_6360_SRCLKENO2_CTRL			(1 << 24u)
+#define SPM_FLAG_DISABLE_6360_VDDQ_CTRL			(1 << 25u)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_OFF			(1 << 26u)
+#define SPM_FLAG_VTCXO_STATE			(1 << 27u)
+#define SPM_FLAG_INFRA_STATE			(1 << 28u)
+#define SPM_FLAG_APSRC_STATE			(1 << 29u)
+#define SPM_FLAG_VRF18_STATE			(1 << 30u)
+#define SPM_FLAG_DDREN_STATE			(1 << 31u)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M      (1 << 0u)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF          (1 << 1u)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH    (1 << 2u)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF          (1 << 3u)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON            (1 << 4u)
+#define SPM_FLAG1_RESERVED_BIT5               (1 << 5u)
+#define SPM_FLAG1_ENABLE_REKICK               (1 << 6u)
+#define SPM_FLAG1_RESERVED_BIT7               (1 << 7u)
+#define SPM_FLAG1_RESERVED_BIT8               (1 << 8u)
+#define SPM_FLAG1_RESERVED_BIT9               (1 << 9u)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW         (1 << 10u)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH      (1 << 11u)
+#define SPM_FLAG1_RESERVED_BIT12              (1 << 12u)
+#define SPM_FLAG1_RESERVED_BIT13              (1 << 13u)
+#define SPM_FLAG1_RESERVED_BIT14              (1 << 14u)
+#define SPM_FLAG1_RESERVED_BIT15              (1 << 15u)
+#define SPM_FLAG1_RESERVED_BIT16              (1 << 16u)
+#define SPM_FLAG1_RESERVED_BIT17              (1 << 17u)
+#define SPM_FLAG1_RESERVED_BIT18              (1 << 18u)
+#define SPM_FLAG1_RESERVED_BIT19              (1 << 19u)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP   (1 << 20u)
+#define SPM_FLAG1_RESERVED_BIT21              (1 << 21u)
+#define SPM_FLAG1_ENABLE_VS1_VOTER            (1 << 22u)
+#define SPM_FLAG1_ENABLE_VS2_VOTER            (1 << 23u)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL   (1 << 24u)
+#define SPM_FLAG1_RESERVED_BIT25              (1 << 25u)
+#define SPM_FLAG1_RESERVED_BIT26              (1 << 26u)
+#define SPM_FLAG1_RESERVED_BIT27              (1 << 27u)
+#define SPM_FLAG1_RESERVED_BIT28              (1 << 28u)
+#define SPM_FLAG1_RESERVED_BIT29              (1 << 29u)
+#define SPM_FLAG1_RESERVED_BIT30              (1 << 30u)
+#define SPM_FLAG1_ENABLE_MCUPM_OFF              (1 << 31u)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE			(1 << 0u)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP			(1 << 1u)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE			(1 << 2u)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP			(1 << 3u)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE			(1 << 4u)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP			(1 << 5u)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE			(1 << 6u)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP			(1 << 7u)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE			(1 << 8u)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP			(1 << 9u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC	(1 << 10u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE		(1 << 11u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE		(1 << 12u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN	(1 << 13u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE		(1 << 14u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP			(1 << 15u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON			(1 << 16u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP		(1 << 17u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON			(1 << 18u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP			(1 << 19u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON			(1 << 20u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP		(1 << 21u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON		(1 << 22u)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP_ABORT		(1 << 23u)
+#define SPM_DBG_DEBUG_IDX_6360_VMDDR_LP_MODE		(1 << 24u)
+#define SPM_DBG_DEBUG_IDX__6360_VDDQ_LP_MODE		(1 << 25u)
+#define SPM_DBG_DEBUG_IDX_I2C5_NO_CLK		(1 << 26u)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW		(1 << 27u)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE			(1 << 28u)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE			(1 << 29u)
+#define SPM_DBG_DEBUG_IDX_VRF18_STATE			(1 << 30u)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE			(1 << 31u)
+
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP		(1 << 0u)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START		(1 << 1u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF			(1 << 2u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON			(1 << 3u)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS	(1 << 4u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF		(1 << 5u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON		(1 << 6u)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT		(1 << 7u)
+#define SPM_DBG1_NOISE_IRQ				(1 << 8u)
+#define SPM_DBG1_DEBUG_IDX_6360_SRCLKEN2_LOW		(1 << 9u)
+#define SPM_DBG1_DEBUG_IDX_6360_SRCLKEN2_HIGH		(1 << 10u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC		(1 << 11u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M		(1 << 12u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K		(1 << 13u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M		(1 << 14u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF			(1 << 15u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON			(1 << 16u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW			(1 << 17u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH		(1 << 18u)
+#define SPM_DBG1_DEBUG_IDX_MCUPM_WAKE_IRQ		(1 << 19u)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	(1 << 20u)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW			(1 << 21u)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH                    (1 << 22u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT    (1 << 23u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT   (1 << 24u)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT           (1 << 25u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT        (1 << 26u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT       (1 << 27u)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT       (1 << 28u)
+#define SPM_DBG1_DEBUG_IDX_SPM_TIMER_RST_DVFS			(1 << 29u)
+#define SPM_DBG1_DEBUG_IDX_SPM_DISABLE_DDREN_EVENT		(1 << 30u)
+#define SPM_DBG1_MCUPM_RESTORE				(1 << 31u)
+
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC \
+	| SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN \
+	| SPM_DBG_DEBUG_IDX_APSRC_SLEEP_ABORT)
+
+#define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6833/mtk_lp_plat_apmcu.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef __MTK_LP_PLAT_APMCU_H__
+#define __MTK_LP_PLAT_APMCU_H__
+
+#include <linux/types.h>
+
+#define nr_cluster_ids                  (1)
+#define get_physical_cluster_id(cpu)    (0)
+
+#define LP_PM_SYSRAM_INFO_OFS  0x8
+#define LP_PM_SYSRAM_SIZE      0x500
+
+extern void __iomem *cpu_pm_syssram_base;
+/* 0x11B000 */
+#define MT_CPU_PM_KERNEL_SRAMBASE	(cpu_pm_syssram_base + 0x100)
+#define MT_CPU_PM_KERNEL_SRAM(slot)	(MT_CPU_PM_KERNEL_SRAMBASE + (slot<<2))
+
+
+#define cpu_pm_sync_writel(v, a)				\
+do {								\
+	__raw_writel((v), (void __force __iomem *)((a)));	\
+	mb(); /*make sure register access in order */		\
+} while (0)
+
+#define MT_CPU_PM_KERNEL_SRAM_WR(slot, val) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			cpu_pm_sync_writel(val,\
+				MT_CPU_PM_KERNEL_SRAM(slot)); uval; })
+
+
+#define MT_CPU_PM_KERNEL_SRAM_RD(slot) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			uval = __raw_readl(MT_CPU_PM_KERNEL_SRAM(slot));\
+		uval; })
+
+void mtk_lp_plat_set_mcusys_off(int cpu);
+void mtk_lp_plat_clr_mcusys_off(int cpu);
+
+void mtk_lp_plat_set_cluster_off(int cpu);
+void mtk_lp_plat_clr_cluster_off(int cpu);
+
+bool mtk_lp_plat_is_mcusys_off(void);
+bool mtk_lp_plat_is_cluster_off(int cpu);
+
+int mtk_lp_plat_apmcu_init(void);
+int mtk_lp_plat_apmcu_early_init(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6833/mtk_lp_plat_apmcu_mbox.h

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_LP_PLAT_APMCU_MBOX_H__
+#define __MTK_LP_PLAT_APMCU_MBOX_H__
+
+enum {
+	MBOX_SSPM,
+	MBOX_MCUPM,
+
+	NF_MBOX,
+};
+
+/* SSPM Mbox */
+#define APMCU_SSPM_MBOX_ID           3
+#define APMCU_SSPM_MBOX_SPM_CMD_SIZE 8
+
+#define APMCU_SSPM_MBOX_SPM_CMD      0
+#define APMCU_SSPM_MBOX_SPM_ARGS1    1
+#define APMCU_SSPM_MBOX_SPM_ARGS2    2
+#define APMCU_SSPM_MBOX_SPM_ARGS3    3
+#define APMCU_SSPM_MBOX_SPM_ARGS4    4
+#define APMCU_SSPM_MBOX_SPM_ARGS5    5
+#define APMCU_SSPM_MBOX_SPM_ARGS6    6
+#define APMCU_SSPM_MBOX_SPM_ARGS7    7
+#define APMCU_SSPM_MBOX_AP_READY     17
+
+void mtk_set_sspm_lp_cmd(void *buf);
+void mtk_clr_sspm_lp_cmd(void);
+
+
+/* MCUPM Mbox */
+
+#define APMCU_MCUPM_MBOX_ID             3
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY       0
+#define APMCU_MCUPM_MBOX_RESERVED_1     1
+#define APMCU_MCUPM_MBOX_RESERVED_2     2
+#define APMCU_MCUPM_MBOX_RESERVED_3     3
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN    4
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE  5
+#define APMCU_MCUPM_MBOX_BUCK_MODE      6
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE    7
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA       8
+#define APMCU_MCUPM_MBOX_RESERVED_9     9
+#define APMCU_MCUPM_MBOX_RESERVED_10    10
+#define APMCU_MCUPM_MBOX_RESERVED_11    11
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU     12
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN (4) */
+#define MCUPM_MCUSYS_CTRL               (1 << 0)
+#define MCUPM_BUCK_CTRL                 (1 << 1)
+#define MCUPM_ARMPLL_CTRL               (1 << 2)
+#define MCUPM_CM_CTRL                   (1 << 3)
+#define MCUPM_PWR_CTRL_MASK             ((1 << 4) - 1)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_L3_CACHE_MODE (5) */
+#define MCUPM_L3_OFF_MODE               0 /* default */
+#define MCUPM_L3_DORMANT_MODE           1
+#define NF_MCUPM_L3_MODE                2U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE (6) */
+#define MCUPM_BUCK_NORMAL_MODE          0 /* default */
+#define MCUPM_BUCK_LP_MODE              1
+#define MCUPM_BUCK_OFF_MODE             2
+#define NF_MCUPM_BUCK_MODE              3U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE (7) */
+#define MCUPM_ARMPLL_ON                 0 /* default */
+#define MCUPM_ARMPLL_GATING             1
+#define MCUPM_ARMPLL_OFF                2
+#define NF_MCUPM_ARMPLL_MODE            3U
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA (9) */
+#define MCUPM_TASK_UNINIT               0
+#define MCUPM_TASK_INIT                 1
+#define MCUPM_TASK_INIT_FINISH          2
+#define MCUPM_TASK_WAIT                 3
+#define MCUPM_TASK_RUN                  4
+#define MCUPM_TASK_PAUSE                5
+
+bool mtk_mcupm_cm_is_notified(void);
+
+void mtk_set_mcupm_pll_mode(unsigned int mode);
+int mtk_get_mcupm_pll_mode(void);
+
+void mtk_set_mcupm_buck_mode(unsigned int mode);
+int mtk_get_mcupm_buck_mode(void);
+
+void mtk_set_preferred_cpu_wakeup(int cpu);
+int mtk_get_preferred_cpu_wakeup(void);
+
+bool mtk_mcupm_is_ready(void);
+
+void mtk_wait_mbox_init_done(void);
+void mtk_notify_subsys_ap_ready(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6833/mtk_lp_plat_reg.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_PLAT_CPC_REG_H__
+#define __MTK_PLAT_CPC_REG_H__
+
+/**************************************
+ * CPC related register
+ * base address = 0x0C53A000
+ **************************************/
+#define CPC_FLOW_CTRL_CFG              (0x814)
+#define CPC_MCUSYS_LAST_CORE_REQ       (0x818)
+#define CPC_CPUSYS_LAST_CORE_RESP      (0x81C)
+#define CPC_MCUSYS_LAST_CORE_RESP      (0x824)
+#define CPC_PWR_ON_MASK                (0x828)
+#define CPC_SPMC_PWR_STATUS            (0x840)
+#define CPC_CPUSYS_CPU_ON_SW_HINT_CLR  (0x8AC)
+
+#define SPMC_DBG_SETTING               (0xB00)
+
+#define CPC_TRACE_DATA_SEL             (0xB14)
+
+#define CPC_CPU0_LATENCY               (0xB40)
+#define CPC_CPU1_LATENCY               (0xB44)
+#define CPC_CPU2_LATENCY               (0xB48)
+#define CPC_CPU3_LATENCY               (0xB4C)
+#define CPC_CPU4_LATENCY               (0xB50)
+#define CPC_CPU5_LATENCY               (0xB54)
+#define CPC_CPU6_LATENCY               (0xB58)
+#define CPC_CPU7_LATENCY               (0xB5C)
+#define CPC_CLUSTER_OFF_LATENCY        (0xB60)
+#define CPC_CLUSTER_ON_LATENCY         (0xB64)
+#define CPC_MCUSYS_LATENCY             (0xB68)
+#define CPC_DORMANT_COUNTER            (0xB70)
+#define CPC_DORMANT_COUNTER_CLR        (0xB74)
+#define CPC_CPU_LATENCY(cpu)           ((CPC_CPU0_LATENCY) + 4 * (cpu))
+
+/**************************************
+ * system sram for apmcu debug
+ * base address = 0x0011B000
+ **************************************/
+#define SYSRAM_CPUSYS_CNT              (0x1E8)
+#define SYSRAM_MCUSYS_CNT              (0x1EC)
+#define SYSRAM_CPC_CPUSYS_CNT_BACKUP   (0x1F0)
+#define SYSRAM_MCUPM_MCUSYS_COUNTER    (0x1F4)
+#define SYSRAM_CPU_ONLINE              (0x1F8)
+
+/* Run time information. The registers may be cleared in db dump flow */
+#define SYSRAM_RECENT_CPU_CNT(i)       (4 * (i) + 0x1B0)
+#define SYSRAM_RECENT_CPUSYS_CNT       (0x1D0)
+#define SYSRAM_RECENT_MCUSYS_CNT       (0x1D4)
+#define SYSRAM_RECENT_CNT_TS_L         (0x1D8)
+#define SYSRAM_RECENT_CNT_TS_H         (0x1DC)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6833/mtk_power_gs_array.h

@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+#ifndef MTK_POWER_GS_ARRAY_H
+#define MTK_POWER_GS_ARRAY_H
+
+extern void mt_power_gs_sp_dump(void);
+extern unsigned int golden_read_reg(unsigned int addr);
+
+/* PMIC 6365 */
+extern const unsigned int *AP_PMIC_REG_6365_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_6365_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_6365_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_6365_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_6365_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_6365_gs_suspend_32kless_len;
+
+/* PMIC 6315 */
+extern const unsigned int *AP_PMIC_REG_MT6315_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_gs_suspend_32kless_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_dpidle;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_dpidle_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_suspend;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_suspend_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_sodi;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_sodi_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_dpidle;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_dpidle_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_suspend;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_suspend_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_sodi;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_sodi_len;
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6853/mt6853_cond.h

@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MT6853_COND_H__
+#define __MT6853_COND_H__
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]    : idle condition check fail
+ */
+
+#define SPM_COND_BLOCKED_CG_IDX		(0)
+#define SPM_COND_BLOCKED_PLL_IDX	(16)
+#define SPM_COND_BLOCKED_PLL		(1<<30L)
+#define SPM_COND_CHECK_FAIL		(1<<31L)
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS_0 = 0,
+	PLAT_SPM_COND_CG_INFRA_0,
+	PLAT_SPM_COND_CG_INFRA_1,
+	PLAT_SPM_COND_CG_INFRA_2,
+	PLAT_SPM_COND_CG_INFRA_3,
+	PLAT_SPM_COND_CG_INFRA_4,
+	PLAT_SPM_COND_CG_INFRA_5,
+	PLAT_SPM_COND_CG_MMSYS_0,
+	PLAT_SPM_COND_CG_MMSYS_1,
+	PLAT_SPM_COND_CG_MMSYS_2,
+	PLAT_SPM_COND_CG_MMSYS_3,
+	PLAT_SPM_COND_MAX,
+};
+
+enum PLAT_SPM_PLL_COND {
+	PLAT_SPM_COND_UNIVPLL = 0,
+	PLAT_SPM_COND_MFGPLL,
+	PLAT_SPM_COND_MSDCPLL,
+	PLAT_SPM_COND_TVPLL,
+	PLAT_SPM_COND_MMPLL,
+	PLAT_SPM_COND_PLL_MAX,
+};
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6853/mt6853_pcm_def.h

@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __pcm_def_h__
+#define __pcm_def_h__
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF                      (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN               (1U << 1)
+#define R0_SC_MEM_CK_OFF                      (1U << 2)
+#define R0_SC_AXI_CK_OFF                      (1U << 3)
+#define R0_SC_DR_SRAM_LOAD                    (1U << 4)
+#define R0_SC_MD26M_CK_OFF                    (1U << 5)
+#define R0_SC_DPY_MODE_SW                     (1U << 6)
+#define R0_SC_DMSUS_OFF                       (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN                  (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE                 (1U << 9)
+#define R0_SC_MPLLOUT_OFF                     (1U << 10)
+#define R0_SC_TX_TRACKING_DIS                 (1U << 11)
+#define R0_SC_DPY_DLL_EN                      (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN                   (1U << 13)
+#define R0_SC_DPY_VREF_EN                     (1U << 14)
+#define R0_SC_PHYPLL_EN                       (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN                 (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE                 (1U << 17)
+#define R0_SC_MPLL_OFF                        (1U << 18)
+#define R0_SC_SHU_RESTORE                     (1U << 19)
+#define R0_SC_CKSQ0_OFF                       (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH         (1U << 21)
+#define R0_SC_DR_SHU_EN                       (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP                  (1U << 23)
+#define R0_SC_MPLL_S_OFF                      (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN             (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN                   (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN                  (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW                  (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW                 (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0                   (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1                   (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ                    (1U << 0)
+#define R7_EMI_CLK_OFF_REQ                    (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ                (1U << 2)
+#define R7_SPM_CK_UPDATE                      (1U << 3)
+#define R7_SPM_CK_SEL0                        (1U << 4)
+#define R7_SPM_CK_SEL1                        (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ             (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL                  (1U << 7)
+#define R7_SC_26M_CK_SEL                      (1U << 8)
+#define R7_PCM_TIMER_SET                      (1U << 9)
+#define R7_PCM_TIMER_CLR                      (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ              (1U << 11)
+#define R7_CSYSPWRUPACK                       (1U << 12)
+#define R7_PCM_IM_SLP_EN                      (1U << 13)
+#define R7_SRCCLKENO0                         (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE                  (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK             (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL              (1U << 17)
+#define R7_SC_AXI_DCM_DIS                     (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM                   (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN                  (1U << 20)
+#define R7_SRCCLKENO1                         (1U << 21)
+#define R7_PCM_WDT_KICK_P                     (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC              (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM                 (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM           (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN                    (1U << 26)
+#define R7_FORCE_F26M_WAKE                    (1U << 27)
+#define R7_FORCE_APSRC_WAKE                   (1U << 28)
+#define R7_FORCE_INFRA_WAKE                   (1U << 29)
+#define R7_FORCE_VRF18_WAKE                   (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK            (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER                         (1U << 0)
+#define R12_TWAM_IRQ_B                        (1U << 1)
+#define R12_KP_IRQ_B                          (1U << 2)
+#define R12_APWDT_EVENT_B                     (1U << 3)
+#define R12_APXGPT1_EVENT_B                   (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B              (1U << 5)
+#define R12_EINT_EVENT_B                      (1U << 6)
+#define R12_CONN_WDT_IRQ_B                    (1U << 7)
+#define R12_CCIF0_EVENT_B                     (1U << 8)
+#define R12_LOWBATTERY_IRQ_B                  (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B                 (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B                  (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B                 (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B                  (1U << 13)
+#define R12_USBX_CDSC_B                       (1U << 14)
+#define R12_USBX_POWERDWN_B                   (1U << 15)
+#define R12_SYS_TIMER_EVENT_B                 (1U << 16)
+#define R12_EINT_EVENT_SECURE_B               (1U << 17)
+#define R12_CCIF1_EVENT_B                     (1U << 18)
+#define R12_UART0_IRQ_B                       (1U << 19)
+#define R12_AFE_IRQ_MCU_B                     (1U << 20)
+#define R12_THERM_CTRL_EVENT_B                (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B                    (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B                (1U << 23)
+#define R12_CSYSPWREQ_B                       (1U << 24)
+#define R12_MD1_WDT_B                         (1U << 25)
+#define R12_CLDMA_EVENT_B                     (1U << 26)
+#define R12_SEJ_EVENT_B                       (1U << 27)
+#define R12_REG_CPU_WAKEUP                    (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B                (1U << 29)
+#define R12_PCIE_BRIDGE_IRQ                   (1U << 30)
+#define R12_PCIE_IRQ                          (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE                       (1U << 0)
+#define R12EXT_26M_SLEEP                      (1U << 1)
+#define R12EXT_INFRA_WAKE                     (1U << 2)
+#define R12EXT_INFRA_SLEEP                    (1U << 3)
+#define R12EXT_APSRC_WAKE                     (1U << 4)
+#define R12EXT_APSRC_SLEEP                    (1U << 5)
+#define R12EXT_VRF18_WAKE                     (1U << 6)
+#define R12EXT_VRF18_SLEEP                    (1U << 7)
+#define R12EXT_DVFS_WAKE                      (1U << 8)
+#define R12EXT_DDREN_WAKE                     (1U << 9)
+#define R12EXT_DDREN_SLEEP                    (1U << 10)
+#define R12EXT_MCU_PM_WFI                     (1U << 11)
+#define R12EXT_SSPM_IDLE                      (1U << 12)
+#define R12EXT_CONN_SRCCLKENB                 (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE           (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE                (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE              (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE              (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE               (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK          (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK         (1U << 20)
+#define R12EXT_BIT21                          (1U << 21)
+#define R12EXT_BIT22                          (1U << 22)
+#define R12EXT_BIT23                          (1U << 23)
+#define R12EXT_BIT24                          (1U << 24)
+#define R12EXT_BIT25                          (1U << 25)
+#define R12EXT_BIT26                          (1U << 26)
+#define R12EXT_BIT27                          (1U << 27)
+#define R12EXT_BIT28                          (1U << 28)
+#define R12EXT_BIT29                          (1U << 29)
+#define R12EXT_BIT30                          (1U << 30)
+#define R12EXT_BIT31                          (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0                        (1U << 0)
+#define R13_SRCCLKENI1                        (1U << 1)
+#define R13_MD_0_SRCCLKENA                    (1U << 2)
+#define R13_MD_0_APSRC_REQ                    (1U << 3)
+#define R13_CONN_DDREN                        (1U << 4)
+#define R13_MD_1_SRCCLKENA                    (1U << 5)
+#define R13_SSPM_SRCCLKENA                    (1U << 6)
+#define R13_SSPM_APSRC_REQ                    (1U << 7)
+#define R13_MD_1_STATE                        (1U << 8)
+#define R13_RC_SRCCLKENO_ACK                  (1U << 9)
+#define R13_MM_STATE                          (1U << 10)
+#define R13_SSPM_STATE                        (1U << 11)
+#define R13_MD_0_DDREN                        (1U << 12)
+#define R13_CONN_STATE                        (1U << 13)
+#define R13_CONN_SRCCLKENA                    (1U << 14)
+#define R13_CONN_APSRC_REQ                    (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL                (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL          (1U << 17)
+#define R13_SCP_STATE                         (1U << 18)
+#define R13_CSYSPWRUPREQ                      (1U << 19)
+#define R13_PWRAP_SLEEP_ACK                   (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL            (1U << 21)
+#define R13_AUDIO_DSP_STATE                   (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL             (1U << 23)
+#define R13_CONN_SRCCLKENB                    (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL           (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0              (1U << 26)
+#define R13_DVFS_STATE                        (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL       (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL        (1U << 29)
+#define R13_MD_0_VRF18_REQ                    (1U << 30)
+#define R13_DDR_EN_STATE                      (1U << 31)
+
+
+enum SPM_WAKE_SRC_LIST {
+	WAKE_SRC_STA1_PCM_TIMER = (1U << 0),
+	WAKE_SRC_STA1_RESERVED_DEBUG_B = (1U << 1),
+	WAKE_SRC_STA1_KP_IRQ_B = (1U << 2),
+	WAKE_SRC_STA1_APWDT_EVENT_B = (1U << 3),
+	WAKE_SRC_STA1_APXGPT1_EVENT_B = (1U << 4),
+	WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B = (1U << 5),
+	WAKE_SRC_STA1_EINT_EVENT_B = (1U << 6),
+	WAKE_SRC_STA1_CONN_WDT_IRQ_B = (1U << 7),
+	WAKE_SRC_STA1_CCIF0_EVENT_B = (1U << 8),
+	WAKE_SRC_STA1_LOWBATTERY_IRQ_B = (1U << 9),
+	WAKE_SRC_STA1_SC_SSPM2SPM_WAKEUP_B = (1U << 10),
+	WAKE_SRC_STA1_SC_SCP2SPM_WAKEUP_B = (1U << 11),
+	WAKE_SRC_STA1_SC_ADSP2SPM_WAKEUP_B = (1U << 12),
+	WAKE_SRC_STA1_PCM_WDT_WAKEUP_B = (1U << 13),
+	WAKE_SRC_STA1_USB_CDSC_B = (1U << 14),
+	WAKE_SRC_STA1_USB_POWERDWN_B = (1U << 15),
+	WAKE_SRC_STA1_SYS_TIMER_EVENT_B = (1U << 16),
+	WAKE_SRC_STA1_EINT_EVENT_SECURE_B = (1U << 17),
+	WAKE_SRC_STA1_CCIF1_EVENT_B = (1U << 18),
+	WAKE_SRC_STA1_UART0_IRQ_B = (1U << 19),
+	WAKE_SRC_STA1_AFE_IRQ_MCU_B = (1U << 20),
+	WAKE_SRC_STA1_THERM_CTRL_EVENT_B = (1U << 21),
+	WAKE_SRC_STA1_SYS_CIRQ_IRQ_B = (1U << 22),
+	WAKE_SRC_STA1_MD2AP_PEER_EVENT_B = (1U << 23),
+	WAKE_SRC_STA1_CSYSPWREQ_B = (1U << 24),
+	WAKE_SRC_STA1_MD1_WDT_B = (1U << 25),
+	WAKE_SRC_STA1_AP2AP_PEER_WAKEUPEVENT_B = (1U << 26),
+	WAKE_SRC_STA1_SEJ_EVENT_B = (1U << 27),
+	WAKE_SRC_STA1_SPM_CPU_WAKEUPEVENT_B = (1U << 28),
+	WAKE_SRC_STA1_APUSYS = (1U << 29),
+	WAKE_SRC_STA1_PCIE_BRIDGE_IRQ = (1U << 30),
+	WAKE_SRC_STA1_PCIE_IRQ = (1U << 31)
+};
+
+extern const char *wakesrc_str[32];
+
+/* define WAKE_SRC_CONN2AP for conn use */
+#define WAKE_SRC_CONN2AP WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B
+
+#endif /* __pcm_def_h__ */

drivers/misc/mediatek/lpm/modules/include/mt6853/mt6853_pwr_ctrl.h

@@ -0,0 +1,423 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __PWR_CTRL_H__
+#define __PWR_CTRL_H__
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP              0x3FF  /* bit0 ~ bit9 */
+#define WAKE_MISC_DVFSRC_IRQ	         (1U << 16)
+#define WAKE_MISC_REG_CPU_WAKEUP         (1U << 17)
+#define WAKE_MISC_PCM_TIMER_EVENT        (1U << 18)
+#define WAKE_MISC_PMIC_OUT_B		     ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B             (1U << 21)
+#define WAKE_MISC_PMSR_IRQ_B_SET0        (1U << 22)
+#define WAKE_MISC_PMSR_IRQ_B_SET1        (1U << 23)
+#define WAKE_MISC_PMSR_IRQ_B_SET2        (1U << 24)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0   (1U << 25)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1	 (1U << 26)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2	 (1U << 27)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3	 (1U << 28)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL (1U << 29)
+#define WAKE_MISC_PMIC_IRQ_ACK			 (1U << 30)
+#define WAKE_MISC_PMIC_SCP_IRQ			 (1U << 31)
+
+struct pwr_ctrl {
+
+	/* for SPM */
+	uint32_t pcm_flags;
+	uint32_t pcm_flags_cust;
+	uint32_t pcm_flags_cust_set;
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	uint32_t pcm_flags1_cust;
+	uint32_t pcm_flags1_cust_set;
+	uint32_t pcm_flags1_cust_clr;
+	uint32_t timer_val;
+	uint32_t timer_val_cust;
+	uint32_t timer_val_ramp_en;
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	uint32_t wake_src_cust;
+	uint32_t wakelock_timer_val;
+	uint8_t wdt_disable;
+	/* Auto-gen Start */
+
+	/* SPM_CLK_CON */
+	uint8_t reg_srcclken0_ctl;
+	uint8_t reg_srcclken1_ctl;
+	uint8_t reg_spm_lock_infra_dcm;
+	uint8_t reg_srcclken_mask;
+	uint8_t reg_md1_c32rm_en;
+	uint8_t reg_md2_c32rm_en;
+	uint8_t reg_clksq0_sel_ctrl;
+	uint8_t reg_clksq1_sel_ctrl;
+	uint8_t reg_srcclken0_en;
+	uint8_t reg_srcclken1_en;
+	uint32_t reg_sysclk0_src_mask_b;
+	uint32_t reg_sysclk1_src_mask_b;
+
+	/* SPM_AP_STANDBY_CON */
+	uint8_t reg_wfi_op;
+	uint8_t reg_wfi_type;
+	uint8_t reg_mp0_cputop_idle_mask;
+	uint8_t reg_mp1_cputop_idle_mask;
+	uint8_t reg_mcusys_idle_mask;
+	uint8_t reg_md_apsrc_1_sel;
+	uint8_t reg_md_apsrc_0_sel;
+	uint8_t reg_conn_apsrc_sel;
+
+	/* SPM_SRC6_MASK */
+	uint32_t reg_ccif_event_infra_req_mask_b;
+	uint32_t reg_ccif_event_apsrc_req_mask_b;
+
+	/* SPM_SRC_REQ */
+	uint8_t reg_spm_apsrc_req;
+	uint8_t reg_spm_f26m_req;
+	uint8_t reg_spm_infra_req;
+	uint8_t reg_spm_vrf18_req;
+	uint8_t reg_spm_ddren_req;
+	uint8_t reg_spm_dvfs_req;
+	uint8_t reg_spm_sw_mailbox_req;
+	uint8_t reg_spm_sspm_mailbox_req;
+	uint8_t reg_spm_adsp_mailbox_req;
+	uint8_t reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	uint8_t reg_md_0_srcclkena_mask_b;
+	uint8_t reg_md_0_infra_req_mask_b;
+	uint8_t reg_md_0_apsrc_req_mask_b;
+	uint8_t reg_md_0_vrf18_req_mask_b;
+	uint8_t reg_md_0_ddren_req_mask_b;
+	uint8_t reg_md_1_srcclkena_mask_b;
+	uint8_t reg_md_1_infra_req_mask_b;
+	uint8_t reg_md_1_apsrc_req_mask_b;
+	uint8_t reg_md_1_vrf18_req_mask_b;
+	uint8_t reg_md_1_ddren_req_mask_b;
+	uint8_t reg_conn_srcclkena_mask_b;
+	uint8_t reg_conn_srcclkenb_mask_b;
+	uint8_t reg_conn_infra_req_mask_b;
+	uint8_t reg_conn_apsrc_req_mask_b;
+	uint8_t reg_conn_vrf18_req_mask_b;
+	uint8_t reg_conn_ddren_req_mask_b;
+	uint8_t reg_conn_vfe28_mask_b;
+	uint8_t reg_srcclkeni_srcclkena_mask_b;
+	uint8_t reg_srcclkeni_infra_req_mask_b;
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	uint8_t reg_infrasys_ddren_req_mask_b;
+	uint8_t reg_sspm_srcclkena_mask_b;
+	uint8_t reg_sspm_infra_req_mask_b;
+	uint8_t reg_sspm_apsrc_req_mask_b;
+	uint8_t reg_sspm_vrf18_req_mask_b;
+	uint8_t reg_sspm_ddren_req_mask_b;
+
+	/* SPM_SRC2_MASK */
+	uint8_t reg_scp_srcclkena_mask_b;
+	uint8_t reg_scp_infra_req_mask_b;
+	uint8_t reg_scp_apsrc_req_mask_b;
+	uint8_t reg_scp_vrf18_req_mask_b;
+	uint8_t reg_scp_ddren_req_mask_b;
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	uint8_t reg_audio_dsp_ddren_req_mask_b;
+	uint8_t reg_ufs_srcclkena_mask_b;
+	uint8_t reg_ufs_infra_req_mask_b;
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	uint8_t reg_ufs_vrf18_req_mask_b;
+	uint8_t reg_ufs_ddren_req_mask_b;
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	uint8_t reg_disp0_ddren_req_mask_b;
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	uint8_t reg_disp1_ddren_req_mask_b;
+	uint8_t reg_gce_infra_req_mask_b;
+	uint8_t reg_gce_apsrc_req_mask_b;
+	uint8_t reg_gce_vrf18_req_mask_b;
+	uint8_t reg_gce_ddren_req_mask_b;
+	uint8_t reg_apu_srcclkena_mask_b;
+	uint8_t reg_apu_infra_req_mask_b;
+	uint8_t reg_apu_apsrc_req_mask_b;
+	uint8_t reg_apu_vrf18_req_mask_b;
+	uint8_t reg_apu_ddren_req_mask_b;
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	uint8_t reg_cg_check_ddren_req_mask_b;
+
+	/* SPM_SRC3_MASK */
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+	uint8_t reg_sw2spm_wakeup_mask_b;
+	uint8_t reg_adsp2spm_wakeup_mask_b;
+	uint8_t reg_sspm2spm_wakeup_mask_b;
+	uint8_t reg_scp2spm_wakeup_mask_b;
+	uint8_t reg_csyspwrup_ack_mask;
+	uint8_t reg_spm_reserved_srcclkena_mask_b;
+	uint8_t reg_spm_reserved_infra_req_mask_b;
+	uint8_t reg_spm_reserved_apsrc_req_mask_b;
+	uint8_t reg_spm_reserved_vrf18_req_mask_b;
+	uint8_t reg_spm_reserved_ddren_req_mask_b;
+	uint8_t reg_mcupm_srcclkena_mask_b;
+	uint8_t reg_mcupm_infra_req_mask_b;
+	uint8_t reg_mcupm_apsrc_req_mask_b;
+	uint8_t reg_mcupm_vrf18_req_mask_b;
+	uint8_t reg_mcupm_ddren_req_mask_b;
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	uint8_t reg_msdc0_infra_req_mask_b;
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	uint8_t reg_msdc0_ddren_req_mask_b;
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	uint8_t reg_msdc1_infra_req_mask_b;
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	uint8_t reg_msdc1_ddren_req_mask_b;
+
+	/* SPM_SRC4_MASK */
+	uint32_t reg_ccif_event_srcclkena_mask_b;
+	uint8_t reg_bak_psri_srcclkena_mask_b;
+	uint8_t reg_bak_psri_infra_req_mask_b;
+	uint8_t reg_bak_psri_apsrc_req_mask_b;
+	uint8_t reg_bak_psri_vrf18_req_mask_b;
+	uint8_t reg_bak_psri_ddren_req_mask_b;
+	uint8_t reg_dramc_md32_infra_req_mask_b;
+	uint8_t reg_dramc_md32_vrf18_req_mask_b;
+	uint8_t reg_conn_srcclkenb2pwrap_mask_b;
+	uint8_t reg_dramc_md32_apsrc_req_mask_b;
+
+	/* SPM_SRC5_MASK */
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	uint32_t reg_mcusys_merge_ddren_req_mask_b;
+	uint8_t reg_afe_srcclkena_mask_b;
+	uint8_t reg_afe_infra_req_mask_b;
+	uint8_t reg_afe_apsrc_req_mask_b;
+	uint8_t reg_afe_vrf18_req_mask_b;
+	uint8_t reg_afe_ddren_req_mask_b;
+	uint8_t reg_msdc2_srcclkena_mask_b;
+	uint8_t reg_msdc2_infra_req_mask_b;
+	uint8_t reg_msdc2_apsrc_req_mask_b;
+	uint8_t reg_msdc2_vrf18_req_mask_b;
+	uint8_t reg_msdc2_ddren_req_mask_b;
+
+	/* SPM_SRC7_MASK */
+	uint8_t reg_pcie_srcclkena_mask_b;
+	uint8_t reg_pcie_infra_req_mask_b;
+	uint8_t reg_pcie_apsrc_req_mask_b;
+	uint8_t reg_pcie_vrf18_req_mask_b;
+	uint8_t reg_pcie_ddren_req_mask_b;
+	uint8_t reg_dpmaif_srcclkena_mask_b;
+	uint8_t reg_dpmaif_infra_req_mask_b;
+	uint8_t reg_dpmaif_apsrc_req_mask_b;
+	uint8_t reg_dpmaif_vrf18_req_mask_b;
+	uint8_t reg_dpmaif_ddren_req_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	uint32_t reg_ext_wakeup_event_mask;
+
+	/* Auto-gen End */
+};
+
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+
+	/* SPM_CLK_CON */
+	PW_REG_SRCCLKEN0_CTL,
+	PW_REG_SRCCLKEN1_CTL,
+	PW_REG_SPM_LOCK_INFRA_DCM,
+	PW_REG_SRCCLKEN_MASK,
+	PW_REG_MD1_C32RM_EN,
+	PW_REG_MD2_C32RM_EN,
+	PW_REG_CLKSQ0_SEL_CTRL,
+	PW_REG_CLKSQ1_SEL_CTRL,
+	PW_REG_SRCCLKEN0_EN,
+	PW_REG_SRCCLKEN1_EN,
+	PW_REG_SYSCLK0_SRC_MASK_B,
+	PW_REG_SYSCLK1_SRC_MASK_B,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+
+	/* SPM_SRC6_MASK */
+	PW_REG_CCIF_EVENT_INFRA_REQ_MASK_B,
+	PW_REG_CCIF_EVENT_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDREN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+
+	/* SPM_SRC_MASK */
+	PW_REG_MD_0_SRCCLKENA_MASK_B,
+	PW_REG_MD_0_INFRA_REQ_MASK_B,
+	PW_REG_MD_0_APSRC_REQ_MASK_B,
+	PW_REG_MD_0_VRF18_REQ_MASK_B,
+	PW_REG_MD_0_DDREN_REQ_MASK_B,
+	PW_REG_MD_1_SRCCLKENA_MASK_B,
+	PW_REG_MD_1_INFRA_REQ_MASK_B,
+	PW_REG_MD_1_APSRC_REQ_MASK_B,
+	PW_REG_MD_1_VRF18_REQ_MASK_B,
+	PW_REG_MD_1_DDREN_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_CONN_DDREN_REQ_MASK_B,
+	PW_REG_CONN_VFE28_MASK_B,
+	PW_REG_SRCCLKENI_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI_INFRA_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDREN_REQ_MASK_B,
+	PW_REG_SSPM_SRCCLKENA_MASK_B,
+	PW_REG_SSPM_INFRA_REQ_MASK_B,
+	PW_REG_SSPM_APSRC_REQ_MASK_B,
+	PW_REG_SSPM_VRF18_REQ_MASK_B,
+	PW_REG_SSPM_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC2_MASK */
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDREN_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDREN_REQ_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDREN_REQ_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDREN_REQ_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDREN_REQ_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GCE_DDREN_REQ_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_APU_DDREN_REQ_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC3_MASK */
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_SW2SPM_WAKEUP_MASK_B,
+	PW_REG_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRUP_ACK_MASK,
+	PW_REG_SPM_RESERVED_SRCCLKENA_MASK_B,
+	PW_REG_SPM_RESERVED_INFRA_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_APSRC_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_VRF18_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_DDREN_REQ_MASK_B,
+	PW_REG_MCUPM_SRCCLKENA_MASK_B,
+	PW_REG_MCUPM_INFRA_REQ_MASK_B,
+	PW_REG_MCUPM_APSRC_REQ_MASK_B,
+	PW_REG_MCUPM_VRF18_REQ_MASK_B,
+	PW_REG_MCUPM_DDREN_REQ_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDREN_REQ_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC4_MASK */
+	PW_REG_CCIF_EVENT_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+	PW_REG_BAK_PSRI_DDREN_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+	PW_REG_DRAMC_MD32_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC5_MASK */
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDREN_REQ_MASK_B,
+	PW_REG_AFE_SRCCLKENA_MASK_B,
+	PW_REG_AFE_INFRA_REQ_MASK_B,
+	PW_REG_AFE_APSRC_REQ_MASK_B,
+	PW_REG_AFE_VRF18_REQ_MASK_B,
+	PW_REG_AFE_DDREN_REQ_MASK_B,
+	PW_REG_MSDC2_SRCCLKENA_MASK_B,
+	PW_REG_MSDC2_INFRA_REQ_MASK_B,
+	PW_REG_MSDC2_APSRC_REQ_MASK_B,
+	PW_REG_MSDC2_VRF18_REQ_MASK_B,
+	PW_REG_MSDC2_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC7_MASK */
+	PW_REG_PCIE_SRCCLKENA_MASK_B,
+	PW_REG_PCIE_INFRA_REQ_MASK_B,
+	PW_REG_PCIE_APSRC_REQ_MASK_B,
+	PW_REG_PCIE_VRF18_REQ_MASK_B,
+	PW_REG_PCIE_DDREN_REQ_MASK_B,
+	PW_REG_DPMAIF_SRCCLKENA_MASK_B,
+	PW_REG_DPMAIF_INFRA_REQ_MASK_B,
+	PW_REG_DPMAIF_APSRC_REQ_MASK_B,
+	PW_REG_DPMAIF_VRF18_REQ_MASK_B,
+	PW_REG_DPMAIF_DDREN_REQ_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+	PW_MAX_COUNT,
+};
+
+
+#endif /* __PWR_CTRL_H__ */

drivers/misc/mediatek/lpm/modules/include/mt6853/mt6853_spm_comm.h

@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MT6853_SPM_COMM_H__
+#define __MT6853_SPM_COMM_H__
+
+struct mt6853_spm_wake_status {
+	u32 r12;			/* SPM_BK_WAKE_EVENT */
+	u32 r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	u32 raw_sta;		/* SPM_WAKEUP_STA */
+	u32 raw_ext_sta;	/* SPM_WAKEUP_EXT_STA */
+	u32 md32pcm_wakeup_sta;/* MD32CPM_WAKEUP_STA */
+	u32 md32pcm_event_sta;/* MD32PCM_EVENT_STA */
+	u32 wake_misc;		/* SPM_BK_WAKE_MISC */
+	u32 timer_out;		/* SPM_BK_PCM_TIMER */
+	u32 r13;			/* PCM_REG13_DATA */
+	u32 idle_sta;		/* SUBSYS_IDLE_STA */
+	u32 req_sta0;		/* SRC_REQ_STA_0 */
+	u32 req_sta1;		/* SRC_REQ_STA_1 */
+	u32 req_sta2;		/* SRC_REQ_STA_2 */
+	u32 req_sta3;		/* SRC_REQ_STA_3 */
+	u32 req_sta4;		/* SRC_REQ_STA_4 */
+	u32 cg_check_sta;	/* SPM_CG_CHECK_STA */
+	u32 debug_flag;		/* PCM_WDT_LATCH_SPARE_0 */
+	u32 debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	u32 b_sw_flag0;		/* SPM_SW_RSV_7 */
+	u32 b_sw_flag1;		/* SPM_SW_RSV_8 */
+	u32 isr;			/* SPM_IRQ_STA */
+	u32 sw_flag0;		/* SPM_SW_FLAG_0 */
+	u32 sw_flag1;		/* SPM_SW_FLAG_1 */
+	u32 clk_settle;		/* SPM_CLK_SETTLE */
+	u32 src_req;	/* SPM_SRC_REQ */
+	u32 log_index;
+	u32 is_abort;
+	u32 rt_req_sta0; /* SPM_SW_RSV_2 */
+	u32 rt_req_sta1; /* SPM_SW_RSV_3 */
+	u32 rt_req_sta2; /* SPM_SW_RSV_4 */
+	u32 rt_req_sta3; /* SPM_SW_RSV_5 */
+	u32 rt_req_sta4; /* SPM_SW_RSV_6 */
+	u32 mcupm_req_sta;
+};
+
+struct spm_wakesrc_irq_list {
+	unsigned int wakesrc;
+	const char *name;
+	int order;
+	unsigned int irq_no;
+};
+
+enum MTK_LPM_SUSPEND_TYPE {
+	MTK_LPM_SUSPEND_SYSTEM,
+	MTK_LPM_SUSPEND_S2IDLE,
+};
+
+/* MD sleep status */
+
+struct md_sleep_status {
+	u64 sleep_wall_clk;
+	u64 sleep_cnt;
+	u64 sleep_cnt_reserve;
+	u64 sleep_time; // 32k
+	u64 sleep_time_reserve;
+	u64 md_sleep_time; // uS
+	u64 gsm_sleep_time; // uS
+	u64 wcdma_sleep_time; //uS
+	u64 lte_sleep_time; // uS
+	u64 nr_sleep_time; // uS
+};
+
+#define MTK_LP_PREPARE_FAIL		(1<<4L)
+
+extern u32 mt_irq_get_pending(unsigned int irq);
+int mtk_lpm_suspend_type_get(void);
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ * From Legacy sleep_def.h
+ */
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN		(1 << 0u)
+#define SPM_FLAG_DISABLE_INFRA_PDN		(1 << 1u)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN		(1 << 2u)
+#define SPM_FLAG_DISABLE_VCORE_DVS		(1 << 3u)
+#define SPM_FLAG_DISABLE_VCORE_DFS		(1 << 4u)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO	(1 << 5u)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF		(1 << 6u)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF		(1 << 7u)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH		(1 << 8u)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND		(1 << 9u)
+#define SPM_FLAG_RUN_COMMON_SCENARIO		(1 << 10u)
+#define SPM_FLAG_RESERVED_BIT11			(1 << 11u)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP	(1 << 12u)
+#define SPM_FLAG_USE_SRCCLKENO2			(1 << 13u)
+#define SPM_FLAG_ENABLE_6315_CTRL		(1 << 14u)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND		(1 << 15u)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP		(1 << 16u)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP	(1 << 17u)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP	(1 << 18u)
+#define SPM_FLAG_RESERVED_BIT19			(1 << 19u)
+#define SPM_FLAG_RESERVED_BIT20			(1 << 20u)
+#define SPM_FLAG_RESERVED_BIT21			(1 << 21u)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP	(1 << 22u)
+#define SPM_FLAG_RESERVED_BIT23			(1 << 23u)
+#define SPM_FLAG_RESERVED_BIT24			(1 << 24u)
+#define SPM_FLAG_RESERVED_BIT25			(1 << 25u)
+#define SPM_FLAG_RESERVED_BIT26			(1 << 26u)
+#define SPM_FLAG_VTCXO_STATE			(1 << 27u)
+#define SPM_FLAG_INFRA_STATE			(1 << 28u)
+#define SPM_FLAG_APSRC_STATE			(1 << 29u)
+#define SPM_FLAG_VRF18_STATE			(1 << 30u)
+#define SPM_FLAG_DDREN_STATE			(1 << 31u)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M      (1 << 0u)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF          (1 << 1u)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH    (1 << 2u)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF          (1 << 3u)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON            (1 << 4u)
+#define SPM_FLAG1_RESERVED_BIT5               (1 << 5u)
+#define SPM_FLAG1_ENABLE_REKICK               (1 << 6u)
+#define SPM_FLAG1_RESERVED_BIT7               (1 << 7u)
+#define SPM_FLAG1_RESERVED_BIT8               (1 << 8u)
+#define SPM_FLAG1_RESERVED_BIT9               (1 << 9u)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW         (1 << 10u)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH      (1 << 11u)
+#define SPM_FLAG1_RESERVED_BIT12              (1 << 12u)
+#define SPM_FLAG1_RESERVED_BIT13              (1 << 13u)
+#define SPM_FLAG1_RESERVED_BIT14              (1 << 14u)
+#define SPM_FLAG1_RESERVED_BIT15              (1 << 15u)
+#define SPM_FLAG1_RESERVED_BIT16              (1 << 16u)
+#define SPM_FLAG1_RESERVED_BIT17              (1 << 17u)
+#define SPM_FLAG1_RESERVED_BIT18              (1 << 18u)
+#define SPM_FLAG1_RESERVED_BIT19              (1 << 19u)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP   (1 << 20u)
+#define SPM_FLAG1_RESERVED_BIT21              (1 << 21u)
+#define SPM_FLAG1_ENABLE_VS1_VOTER            (1 << 22u)
+#define SPM_FLAG1_ENABLE_VS2_VOTER            (1 << 23u)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL   (1 << 24u)
+#define SPM_FLAG1_RESERVED_BIT25              (1 << 25u)
+#define SPM_FLAG1_RESERVED_BIT26              (1 << 26u)
+#define SPM_FLAG1_RESERVED_BIT27              (1 << 27u)
+#define SPM_FLAG1_RESERVED_BIT28              (1 << 28u)
+#define SPM_FLAG1_RESERVED_BIT29              (1 << 29u)
+#define SPM_FLAG1_RESERVED_BIT30              (1 << 30u)
+#define SPM_FLAG1_DISABLE_CPUTOEB_OFF              (1 << 31u)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE			(1 << 0u)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP			(1 << 1u)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE			(1 << 2u)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP			(1 << 3u)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE			(1 << 4u)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP			(1 << 5u)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE			(1 << 6u)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP			(1 << 7u)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE			(1 << 8u)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP			(1 << 9u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC	(1 << 10u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE		(1 << 11u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE		(1 << 12u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN	(1 << 13u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE		(1 << 14u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP			(1 << 15u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON			(1 << 16u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP		(1 << 17u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON			(1 << 18u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP			(1 << 19u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON			(1 << 20u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP		(1 << 21u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON		(1 << 22u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V		(1 << 23u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V		(1 << 24u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V		(1 << 25u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V		(1 << 26u)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW		(1 << 27u)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE			(1 << 28u)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE			(1 << 29u)
+#define SPM_DBG_DEBUG_IDX_VRF18_STATE			(1 << 30u)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE			(1 << 31u)
+
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP		(1 << 0u)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START		(1 << 1u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF			(1 << 2u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON			(1 << 3u)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS	(1 << 4u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF		(1 << 5u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON		(1 << 6u)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT		(1 << 7u)
+#define SPM_DBG1_RESERVED_BIT8				(1 << 8u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF		(1 << 9u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON		(1 << 10u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC		(1 << 11u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M		(1 << 12u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K		(1 << 13u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M		(1 << 14u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF			(1 << 15u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON			(1 << 16u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW			(1 << 17u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH		(1 << 18u)
+#define SPM_DBG1_RESERVED_BIT19				(1 << 19u)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	(1 << 20u)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW			(1 << 21u)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH                    (1 << 22u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT    (1 << 23u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT   (1 << 24u)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT           (1 << 25u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT        (1 << 26u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT       (1 << 27u)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT       (1 << 28u)
+#define SPM_DBG1_RESERVED_BIT29				(1 << 29u)
+#define SPM_DBG1_RESERVED_BIT30				(1 << 30u)
+#define SPM_DBG1_RESERVED_BIT31				(1 << 31u)
+
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC \
+	| SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6853/mtk_lp_plat_apmcu.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef __MTK_LP_PLAT_APMCU_H__
+#define __MTK_LP_PLAT_APMCU_H__
+
+#include <linux/types.h>
+
+#define nr_cluster_ids                  (1)
+#define get_physical_cluster_id(cpu)    (0)
+
+#define LP_PM_SYSRAM_INFO_OFS  0x8
+#define LP_PM_SYSRAM_SIZE      0x500
+
+extern void __iomem *cpu_pm_syssram_base;
+/* 0x11B000 */
+#define MT_CPU_PM_KERNEL_SRAMBASE	(cpu_pm_syssram_base + 0x100)
+#define MT_CPU_PM_KERNEL_SRAM(slot)	(MT_CPU_PM_KERNEL_SRAMBASE + (slot<<2))
+
+
+#define cpu_pm_sync_writel(v, a)				\
+do {								\
+	__raw_writel((v), (void __force __iomem *)((a)));	\
+	mb(); /*make sure register access in order */		\
+} while (0)
+
+#define MT_CPU_PM_KERNEL_SRAM_WR(slot, val) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			cpu_pm_sync_writel(val,\
+				MT_CPU_PM_KERNEL_SRAM(slot)); uval; })
+
+
+#define MT_CPU_PM_KERNEL_SRAM_RD(slot) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			uval = __raw_readl(MT_CPU_PM_KERNEL_SRAM(slot));\
+		uval; })
+
+void mtk_lp_plat_set_mcusys_off(int cpu);
+void mtk_lp_plat_clr_mcusys_off(int cpu);
+
+void mtk_lp_plat_set_cluster_off(int cpu);
+void mtk_lp_plat_clr_cluster_off(int cpu);
+
+bool mtk_lp_plat_is_mcusys_off(void);
+bool mtk_lp_plat_is_cluster_off(int cpu);
+
+int mtk_lp_plat_apmcu_init(void);
+int mtk_lp_plat_apmcu_early_init(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6853/mtk_lp_plat_apmcu_mbox.h

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_LP_PLAT_APMCU_MBOX_H__
+#define __MTK_LP_PLAT_APMCU_MBOX_H__
+
+enum {
+	MBOX_SSPM,
+	MBOX_MCUPM,
+
+	NF_MBOX,
+};
+
+/* SSPM Mbox */
+#define APMCU_SSPM_MBOX_ID           3
+#define APMCU_SSPM_MBOX_SPM_CMD_SIZE 8
+
+#define APMCU_SSPM_MBOX_SPM_CMD      0
+#define APMCU_SSPM_MBOX_SPM_ARGS1    1
+#define APMCU_SSPM_MBOX_SPM_ARGS2    2
+#define APMCU_SSPM_MBOX_SPM_ARGS3    3
+#define APMCU_SSPM_MBOX_SPM_ARGS4    4
+#define APMCU_SSPM_MBOX_SPM_ARGS5    5
+#define APMCU_SSPM_MBOX_SPM_ARGS6    6
+#define APMCU_SSPM_MBOX_SPM_ARGS7    7
+#define APMCU_SSPM_MBOX_AP_READY     17
+
+void mtk_set_sspm_lp_cmd(void *buf);
+void mtk_clr_sspm_lp_cmd(void);
+
+
+/* MCUPM Mbox */
+
+#define APMCU_MCUPM_MBOX_ID             3
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY       0
+#define APMCU_MCUPM_MBOX_RESERVED_1     1
+#define APMCU_MCUPM_MBOX_RESERVED_2     2
+#define APMCU_MCUPM_MBOX_RESERVED_3     3
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN    4
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE  5
+#define APMCU_MCUPM_MBOX_BUCK_MODE      6
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE    7
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA       8
+#define APMCU_MCUPM_MBOX_RESERVED_9     9
+#define APMCU_MCUPM_MBOX_RESERVED_10    10
+#define APMCU_MCUPM_MBOX_RESERVED_11    11
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU     12
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN (4) */
+#define MCUPM_MCUSYS_CTRL               (1 << 0)
+#define MCUPM_BUCK_CTRL                 (1 << 1)
+#define MCUPM_ARMPLL_CTRL               (1 << 2)
+#define MCUPM_CM_CTRL                   (1 << 3)
+#define MCUPM_PWR_CTRL_MASK             ((1 << 4) - 1)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_L3_CACHE_MODE (5) */
+#define MCUPM_L3_OFF_MODE               0 /* default */
+#define MCUPM_L3_DORMANT_MODE           1
+#define NF_MCUPM_L3_MODE                2U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE (6) */
+#define MCUPM_BUCK_NORMAL_MODE          0 /* default */
+#define MCUPM_BUCK_LP_MODE              1
+#define MCUPM_BUCK_OFF_MODE             2
+#define NF_MCUPM_BUCK_MODE              3U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE (7) */
+#define MCUPM_ARMPLL_ON                 0 /* default */
+#define MCUPM_ARMPLL_GATING             1
+#define MCUPM_ARMPLL_OFF                2
+#define NF_MCUPM_ARMPLL_MODE            3U
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA (9) */
+#define MCUPM_TASK_UNINIT               0
+#define MCUPM_TASK_INIT                 1
+#define MCUPM_TASK_INIT_FINISH          2
+#define MCUPM_TASK_WAIT                 3
+#define MCUPM_TASK_RUN                  4
+#define MCUPM_TASK_PAUSE                5
+
+bool mtk_mcupm_cm_is_notified(void);
+
+void mtk_set_mcupm_pll_mode(unsigned int mode);
+int mtk_get_mcupm_pll_mode(void);
+
+void mtk_set_mcupm_buck_mode(unsigned int mode);
+int mtk_get_mcupm_buck_mode(void);
+
+void mtk_set_preferred_cpu_wakeup(int cpu);
+int mtk_get_preferred_cpu_wakeup(void);
+
+bool mtk_mcupm_is_ready(void);
+
+void mtk_wait_mbox_init_done(void);
+void mtk_notify_subsys_ap_ready(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6853/mtk_lp_plat_reg.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_PLAT_CPC_REG_H__
+#define __MTK_PLAT_CPC_REG_H__
+
+/**************************************
+ * CPC related register
+ * base address = 0x0C53A000
+ **************************************/
+#define CPC_FLOW_CTRL_CFG              (0x814)
+#define CPC_MCUSYS_LAST_CORE_REQ       (0x818)
+#define CPC_CPUSYS_LAST_CORE_RESP      (0x81C)
+#define CPC_MCUSYS_LAST_CORE_RESP      (0x824)
+#define CPC_PWR_ON_MASK                (0x828)
+#define CPC_SPMC_PWR_STATUS            (0x840)
+#define CPC_CPUSYS_CPU_ON_SW_HINT_CLR  (0x8AC)
+
+#define SPMC_DBG_SETTING               (0xB00)
+
+#define CPC_TRACE_DATA_SEL             (0xB14)
+
+#define CPC_CPU0_LATENCY               (0xB40)
+#define CPC_CPU1_LATENCY               (0xB44)
+#define CPC_CPU2_LATENCY               (0xB48)
+#define CPC_CPU3_LATENCY               (0xB4C)
+#define CPC_CPU4_LATENCY               (0xB50)
+#define CPC_CPU5_LATENCY               (0xB54)
+#define CPC_CPU6_LATENCY               (0xB58)
+#define CPC_CPU7_LATENCY               (0xB5C)
+#define CPC_CLUSTER_OFF_LATENCY        (0xB60)
+#define CPC_CLUSTER_ON_LATENCY         (0xB64)
+#define CPC_MCUSYS_LATENCY             (0xB68)
+#define CPC_DORMANT_COUNTER            (0xB70)
+#define CPC_DORMANT_COUNTER_CLR        (0xB74)
+#define CPC_CPU_LATENCY(cpu)           ((CPC_CPU0_LATENCY) + 4 * (cpu))
+
+/**************************************
+ * system sram for apmcu debug
+ * base address = 0x0011B000
+ **************************************/
+#define SYSRAM_CPUSYS_CNT              (0x1E8)
+#define SYSRAM_MCUSYS_CNT              (0x1EC)
+#define SYSRAM_CPC_CPUSYS_CNT_BACKUP   (0x1F0)
+#define SYSRAM_MCUPM_MCUSYS_COUNTER    (0x1F4)
+#define SYSRAM_CPU_ONLINE              (0x1F8)
+
+/* Run time information. The registers may be cleared in db dump flow */
+#define SYSRAM_RECENT_CPU_CNT(i)       (4 * (i) + 0x1B0)
+#define SYSRAM_RECENT_CPUSYS_CNT       (0x1D0)
+#define SYSRAM_RECENT_MCUSYS_CNT       (0x1D4)
+#define SYSRAM_RECENT_CNT_TS_L         (0x1D8)
+#define SYSRAM_RECENT_CNT_TS_H         (0x1DC)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6873/mt6873_cond.h

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MT6873_COND_H__
+#define __MT6873_COND_H__
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]    : idle condition check fail
+ */
+
+#define SPM_COND_BLOCKED_CG_IDX		(0)
+#define SPM_COND_BLOCKED_PLL_IDX	(16)
+#define SPM_COND_BLOCKED_PLL		(1<<30L)
+#define SPM_COND_CHECK_FAIL		(1<<31L)
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS_0 = 0,
+	PLAT_SPM_COND_CG_INFRA_0,
+	PLAT_SPM_COND_CG_INFRA_1,
+	PLAT_SPM_COND_CG_INFRA_2,
+	PLAT_SPM_COND_CG_INFRA_3,
+	PLAT_SPM_COND_CG_INFRA_4,
+	PLAT_SPM_COND_CG_INFRA_5,
+	PLAT_SPM_COND_CG_MMSYS_0,
+	PLAT_SPM_COND_CG_MMSYS_1,
+	PLAT_SPM_COND_CG_MMSYS_2,
+	PLAT_SPM_COND_MAX,
+};
+
+enum PLAT_SPM_PLL_COND {
+	PLAT_SPM_COND_UNIVPLL = 0,
+	PLAT_SPM_COND_MFGPLL,
+	PLAT_SPM_COND_MSDCPLL,
+	PLAT_SPM_COND_TVPLL,
+	PLAT_SPM_COND_MMPLL,
+	PLAT_SPM_COND_PLL_MAX,
+};
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6873/mt6873_pcm_def.h

@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __pcm_def_h__
+#define __pcm_def_h__
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF                      (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN               (1U << 1)
+#define R0_SC_MEM_CK_OFF                      (1U << 2)
+#define R0_SC_AXI_CK_OFF                      (1U << 3)
+#define R0_SC_DR_SRAM_LOAD                    (1U << 4)
+#define R0_SC_MD26M_CK_OFF                    (1U << 5)
+#define R0_SC_DPY_MODE_SW                     (1U << 6)
+#define R0_SC_DMSUS_OFF                       (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN                  (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE                 (1U << 9)
+#define R0_SC_MPLLOUT_OFF                     (1U << 10)
+#define R0_SC_TX_TRACKING_DIS                 (1U << 11)
+#define R0_SC_DPY_DLL_EN                      (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN                   (1U << 13)
+#define R0_SC_DPY_VREF_EN                     (1U << 14)
+#define R0_SC_PHYPLL_EN                       (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN                 (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE                 (1U << 17)
+#define R0_SC_MPLL_OFF                        (1U << 18)
+#define R0_SC_SHU_RESTORE                     (1U << 19)
+#define R0_SC_CKSQ0_OFF                       (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH         (1U << 21)
+#define R0_SC_DR_SHU_EN                       (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP                  (1U << 23)
+#define R0_SC_MPLL_S_OFF                      (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN             (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN                   (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN                  (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW                  (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW                 (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0                   (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1                   (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ                    (1U << 0)
+#define R7_EMI_CLK_OFF_REQ                    (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ                (1U << 2)
+#define R7_SPM_CK_UPDATE                      (1U << 3)
+#define R7_SPM_CK_SEL0                        (1U << 4)
+#define R7_SPM_CK_SEL1                        (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ             (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL                  (1U << 7)
+#define R7_SC_26M_CK_SEL                      (1U << 8)
+#define R7_PCM_TIMER_SET                      (1U << 9)
+#define R7_PCM_TIMER_CLR                      (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ              (1U << 11)
+#define R7_CSYSPWRUPACK                       (1U << 12)
+#define R7_PCM_IM_SLP_EN                      (1U << 13)
+#define R7_SRCCLKENO0                         (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE                  (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK             (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL              (1U << 17)
+#define R7_SC_AXI_DCM_DIS                     (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM                   (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN                  (1U << 20)
+#define R7_SRCCLKENO1                         (1U << 21)
+#define R7_PCM_WDT_KICK_P                     (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC              (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM                 (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM           (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN                    (1U << 26)
+#define R7_FORCE_F26M_WAKE                    (1U << 27)
+#define R7_FORCE_APSRC_WAKE                   (1U << 28)
+#define R7_FORCE_INFRA_WAKE                   (1U << 29)
+#define R7_FORCE_VRF18_WAKE                   (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK            (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER                         (1U << 0)
+#define R12_TWAM_IRQ_B                        (1U << 1)
+#define R12_KP_IRQ_B                          (1U << 2)
+#define R12_APWDT_EVENT_B                     (1U << 3)
+#define R12_APXGPT1_EVENT_B                   (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B              (1U << 5)
+#define R12_EINT_EVENT_B                      (1U << 6)
+#define R12_CONN_WDT_IRQ_B                    (1U << 7)
+#define R12_CCIF0_EVENT_B                     (1U << 8)
+#define R12_LOWBATTERY_IRQ_B                  (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B                 (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B                  (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B                 (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B                  (1U << 13)
+#define R12_USBX_CDSC_B                       (1U << 14)
+#define R12_USBX_POWERDWN_B                   (1U << 15)
+#define R12_SYS_TIMER_EVENT_B                 (1U << 16)
+#define R12_EINT_EVENT_SECURE_B               (1U << 17)
+#define R12_CCIF1_EVENT_B                     (1U << 18)
+#define R12_UART0_IRQ_B                       (1U << 19)
+#define R12_AFE_IRQ_MCU_B                     (1U << 20)
+#define R12_THERM_CTRL_EVENT_B                (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B                    (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B                (1U << 23)
+#define R12_CSYSPWREQ_B                       (1U << 24)
+#define R12_MD1_WDT_B                         (1U << 25)
+#define R12_CLDMA_EVENT_B                     (1U << 26)
+#define R12_SEJ_EVENT_B                       (1U << 27)
+#define R12_REG_CPU_WAKEUP                    (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B                (1U << 29)
+#define R12_PCIE_BRIDGE_IRQ                   (1U << 30)
+#define R12_PCIE_IRQ                          (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE                       (1U << 0)
+#define R12EXT_26M_SLEEP                      (1U << 1)
+#define R12EXT_INFRA_WAKE                     (1U << 2)
+#define R12EXT_INFRA_SLEEP                    (1U << 3)
+#define R12EXT_APSRC_WAKE                     (1U << 4)
+#define R12EXT_APSRC_SLEEP                    (1U << 5)
+#define R12EXT_VRF18_WAKE                     (1U << 6)
+#define R12EXT_VRF18_SLEEP                    (1U << 7)
+#define R12EXT_DVFS_WAKE                      (1U << 8)
+#define R12EXT_DDREN_WAKE                     (1U << 9)
+#define R12EXT_DDREN_SLEEP                    (1U << 10)
+#define R12EXT_MCU_PM_WFI                     (1U << 11)
+#define R12EXT_SSPM_IDLE                      (1U << 12)
+#define R12EXT_CONN_SRCCLKENB                 (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE           (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE                (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE              (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE              (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE               (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK          (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK         (1U << 20)
+#define R12EXT_VS1_TRIGGER                    (1U << 21)
+#define R12EXT_VS2_TRIGGER                    (1U << 22)
+#define R12EXT_COROSS_REQ_APU                 (1U << 23)
+#define R12EXT_CROSS_REQ_L3                   (1U << 24)
+#define R12EXT_DDR_PST_ACK                    (1U << 25)
+#define R12EXT_BIT26                          (1U << 26)
+#define R12EXT_BIT27                          (1U << 27)
+#define R12EXT_BIT28                          (1U << 28)
+#define R12EXT_BIT29                          (1U << 29)
+#define R12EXT_BIT30                          (1U << 30)
+#define R12EXT_BIT31                          (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0                        (1U << 0)
+#define R13_SRCCLKENI1                        (1U << 1)
+#define R13_MD_SRCCLKENA_0                    (1U << 2)
+#define R13_MD_APSRC_REQ_0                    (1U << 3)
+#define R13_CONN_DDR_EN                       (1U << 4)
+#define R13_MD_SRCCLKENA_1                    (1U << 5)
+#define R13_SSPM_SRCCLKENA                    (1U << 6)
+#define R13_SSPM_APSRC_REQ                    (1U << 7)
+#define R13_MD1_STATE                         (1U << 8)
+#define R13_BIT9                              (1U << 9)
+#define R13_MM_STATE                          (1U << 10)
+#define R13_SSPM_STATE                        (1U << 11)
+#define R13_MD_DDR_EN_0                       (1U << 12)
+#define R13_CONN_STATE                        (1U << 13)
+#define R13_CONN_SRCCLKENA                    (1U << 14)
+#define R13_CONN_APSRC_REQ                    (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL                (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL          (1U << 17)
+#define R13_SCP_STATE                         (1U << 18)
+#define R13_CSYSPWRUPREQ                      (1U << 19)
+#define R13_PWRAP_SLEEP_ACK                   (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL            (1U << 21)
+#define R13_AUDIO_DSP_STATE                   (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL             (1U << 23)
+#define R13_CONN_SRCCLKENB                    (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL           (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0              (1U << 26)
+#define R13_DVFS_STATE                        (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL       (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL        (1U << 29)
+#define R13_MD_VRF18_REQ_0                    (1U << 30)
+#define R13_DDR_EN_STATE                      (1U << 31)
+
+
+enum SPM_WAKE_SRC_LIST {
+	WAKE_SRC_STA1_PCM_TIMER = (1U << 0),
+	WAKE_SRC_STA1_RESERVED_DEBUG_B = (1U << 1),
+	WAKE_SRC_STA1_KP_IRQ_B = (1U << 2),
+	WAKE_SRC_STA1_APWDT_EVENT_B = (1U << 3),
+	WAKE_SRC_STA1_APXGPT1_EVENT_B = (1U << 4),
+	WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B = (1U << 5),
+	WAKE_SRC_STA1_EINT_EVENT_B = (1U << 6),
+	WAKE_SRC_STA1_CONN_WDT_IRQ_B = (1U << 7),
+	WAKE_SRC_STA1_CCIF0_EVENT_B = (1U << 8),
+	WAKE_SRC_STA1_LOWBATTERY_IRQ_B = (1U << 9),
+	WAKE_SRC_STA1_SC_SSPM2SPM_WAKEUP_B = (1U << 10),
+	WAKE_SRC_STA1_SC_SCP2SPM_WAKEUP_B = (1U << 11),
+	WAKE_SRC_STA1_SC_ADSP2SPM_WAKEUP_B = (1U << 12),
+	WAKE_SRC_STA1_PCM_WDT_WAKEUP_B = (1U << 13),
+	WAKE_SRC_STA1_USB_CDSC_B = (1U << 14),
+	WAKE_SRC_STA1_USB_POWERDWN_B = (1U << 15),
+	WAKE_SRC_STA1_SYS_TIMER_EVENT_B = (1U << 16),
+	WAKE_SRC_STA1_EINT_EVENT_SECURE_B = (1U << 17),
+	WAKE_SRC_STA1_CCIF1_EVENT_B = (1U << 18),
+	WAKE_SRC_STA1_UART0_IRQ_B = (1U << 19),
+	WAKE_SRC_STA1_AFE_IRQ_MCU_B = (1U << 20),
+	WAKE_SRC_STA1_THERM_CTRL_EVENT_B = (1U << 21),
+	WAKE_SRC_STA1_SYS_CIRQ_IRQ_B = (1U << 22),
+	WAKE_SRC_STA1_MD2AP_PEER_EVENT_B = (1U << 23),
+	WAKE_SRC_STA1_CSYSPWREQ_B = (1U << 24),
+	WAKE_SRC_STA1_MD1_WDT_B = (1U << 25),
+	WAKE_SRC_STA1_AP2AP_PEER_WAKEUPEVENT_B = (1U << 26),
+	WAKE_SRC_STA1_SEJ_EVENT_B = (1U << 27),
+	WAKE_SRC_STA1_SPM_CPU_WAKEUPEVENT_B = (1U << 28),
+	WAKE_SRC_STA1_APUSYS = (1U << 29),
+	WAKE_SRC_STA1_PCIE_BRIDGE_IRQ = (1U << 30),
+	WAKE_SRC_STA1_PCIE_IRQ = (1U << 31)
+};
+
+extern const char *wakesrc_str[32];
+
+/* define WAKE_SRC_CONN2AP for conn use */
+#define WAKE_SRC_CONN2AP WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B
+
+#endif /* __pcm_def_h__ */

drivers/misc/mediatek/lpm/modules/include/mt6873/mt6873_pwr_ctrl.h

@@ -0,0 +1,427 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __PWR_CTRL_H__
+#define __PWR_CTRL_H__
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP              0x3FF  /* bit0 ~ bit9 */
+#define WAKE_MISC_DVFSRC_IRQ	         (1U << 16)
+#define WAKE_MISC_REG_CPU_WAKEUP         (1U << 17)
+#define WAKE_MISC_PCM_TIMER_EVENT        (1U << 18)
+#define WAKE_MISC_PMIC_OUT_B		     ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B             (1U << 21)
+#define WAKE_MISC_PMSR_IRQ_B_SET0        (1U << 22)
+#define WAKE_MISC_PMSR_IRQ_B_SET1        (1U << 23)
+#define WAKE_MISC_PMSR_IRQ_B_SET2        (1U << 24)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0   (1U << 25)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1	 (1U << 26)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2	 (1U << 27)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3	 (1U << 28)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL (1U << 29)
+#define WAKE_MISC_PMIC_IRQ_ACK			 (1U << 30)
+#define WAKE_MISC_PMIC_SCP_IRQ			 (1U << 31)
+
+struct pwr_ctrl {
+
+	/* for SPM */
+	uint32_t pcm_flags;
+	uint32_t pcm_flags_cust;
+	uint32_t pcm_flags_cust_set;
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	uint32_t pcm_flags1_cust;
+	uint32_t pcm_flags1_cust_set;
+	uint32_t pcm_flags1_cust_clr;
+	uint32_t timer_val;
+	uint32_t timer_val_cust;
+	uint32_t timer_val_ramp_en;
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	uint32_t wake_src_cust;
+	uint32_t wakelock_timer_val;
+	uint8_t wdt_disable;
+	/* Auto-gen Start */
+
+	/* SPM_CLK_CON */
+	uint8_t reg_srcclken0_ctl;
+	uint8_t reg_srcclken1_ctl;
+	uint8_t reg_spm_lock_infra_dcm;
+	uint8_t reg_srcclken_mask;
+	uint8_t reg_md1_c32rm_en;
+	uint8_t reg_md2_c32rm_en;
+	uint8_t reg_clksq0_sel_ctrl;
+	uint8_t reg_clksq1_sel_ctrl;
+	uint8_t reg_srcclken0_en;
+	uint8_t reg_srcclken1_en;
+	uint32_t reg_sysclk0_src_mask_b;
+	uint32_t reg_sysclk1_src_mask_b;
+
+	/* SPM_AP_STANDBY_CON */
+	uint8_t reg_wfi_op;
+	uint8_t reg_wfi_type;
+	uint8_t reg_mp0_cputop_idle_mask;
+	uint8_t reg_mp1_cputop_idle_mask;
+	uint8_t reg_mcusys_idle_mask;
+	uint8_t reg_md_apsrc_1_sel;
+	uint8_t reg_md_apsrc_0_sel;
+	uint8_t reg_conn_apsrc_sel;
+
+	/* SPM_SRC6_MASK */
+	uint8_t reg_dpmaif_srcclkena_mask_b;
+	uint8_t reg_dpmaif_infra_req_mask_b;
+	uint8_t reg_dpmaif_apsrc_req_mask_b;
+	uint8_t reg_dpmaif_vrf18_req_mask_b;
+	uint8_t reg_dpmaif_ddr_en_mask_b;
+	/* SPM_SRC_REQ */
+	uint8_t reg_spm_apsrc_req;
+	uint8_t reg_spm_f26m_req;
+	uint8_t reg_spm_infra_req;
+	uint8_t reg_spm_vrf18_req;
+	uint8_t reg_spm_ddr_en_req;
+	uint8_t reg_spm_dvfs_req;
+	uint8_t reg_spm_sw_mailbox_req;
+	uint8_t reg_spm_sspm_mailbox_req;
+	uint8_t reg_spm_adsp_mailbox_req;
+	uint8_t reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	uint8_t reg_md_srcclkena_0_mask_b;
+	uint8_t reg_md_srcclkena2infra_req_0_mask_b;
+	uint8_t reg_md_apsrc2infra_req_0_mask_b;
+	uint8_t reg_md_apsrc_req_0_mask_b;
+	uint8_t reg_md_vrf18_req_0_mask_b;
+	uint8_t reg_md_ddr_en_0_mask_b;
+	uint8_t reg_md_srcclkena_1_mask_b;
+	uint8_t reg_md_srcclkena2infra_req_1_mask_b;
+	uint8_t reg_md_apsrc2infra_req_1_mask_b;
+	uint8_t reg_md_apsrc_req_1_mask_b;
+	uint8_t reg_md_vrf18_req_1_mask_b;
+	uint8_t reg_md_ddr_en_1_mask_b;
+	uint8_t reg_conn_srcclkena_mask_b;
+	uint8_t reg_conn_srcclkenb_mask_b;
+	uint8_t reg_conn_infra_req_mask_b;
+	uint8_t reg_conn_apsrc_req_mask_b;
+	uint8_t reg_conn_vrf18_req_mask_b;
+	uint8_t reg_conn_ddr_en_mask_b;
+	uint8_t reg_conn_vfe28_mask_b;
+	uint8_t reg_srcclkeni0_srcclkena_mask_b;
+	uint8_t reg_srcclkeni0_infra_req_mask_b;
+	uint8_t reg_srcclkeni1_srcclkena_mask_b;
+	uint8_t reg_srcclkeni1_infra_req_mask_b;
+	uint8_t reg_srcclkeni2_srcclkena_mask_b;
+	uint8_t reg_srcclkeni2_infra_req_mask_b;
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	uint8_t reg_infrasys_ddr_en_mask_b;
+	uint8_t reg_md32_srcclkena_mask_b;
+	uint8_t reg_md32_infra_req_mask_b;
+	uint8_t reg_md32_apsrc_req_mask_b;
+	uint8_t reg_md32_vrf18_req_mask_b;
+	uint8_t reg_md32_ddr_en_mask_b;
+
+	/* SPM_SRC2_MASK */
+	uint8_t reg_scp_srcclkena_mask_b;
+	uint8_t reg_scp_infra_req_mask_b;
+	uint8_t reg_scp_apsrc_req_mask_b;
+	uint8_t reg_scp_vrf18_req_mask_b;
+	uint8_t reg_scp_ddr_en_mask_b;
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	uint8_t reg_audio_dsp_ddr_en_mask_b;
+	uint8_t reg_ufs_srcclkena_mask_b;
+	uint8_t reg_ufs_infra_req_mask_b;
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	uint8_t reg_ufs_vrf18_req_mask_b;
+	uint8_t reg_ufs_ddr_en_mask_b;
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	uint8_t reg_disp0_ddr_en_mask_b;
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	uint8_t reg_disp1_ddr_en_mask_b;
+	uint8_t reg_gce_infra_req_mask_b;
+	uint8_t reg_gce_apsrc_req_mask_b;
+	uint8_t reg_gce_vrf18_req_mask_b;
+	uint8_t reg_gce_ddr_en_mask_b;
+	uint8_t reg_apu_srcclkena_mask_b;
+	uint8_t reg_apu_infra_req_mask_b;
+	uint8_t reg_apu_apsrc_req_mask_b;
+	uint8_t reg_apu_vrf18_req_mask_b;
+	uint8_t reg_apu_ddr_en_mask_b;
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	uint8_t reg_cg_check_ddr_en_mask_b;
+
+	/* SPM_SRC3_MASK */
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+	uint8_t reg_sw2spm_int0_mask_b;
+	uint8_t reg_sw2spm_int1_mask_b;
+	uint8_t reg_sw2spm_int2_mask_b;
+	uint8_t reg_sw2spm_int3_mask_b;
+	uint8_t reg_sc_adsp2spm_wakeup_mask_b;
+	uint8_t reg_sc_sspm2spm_wakeup_mask_b;
+	uint8_t reg_sc_scp2spm_wakeup_mask_b;
+	uint8_t reg_csyspwrreq_mask;
+	uint8_t reg_spm_srcclkena_reserved_mask_b;
+	uint8_t reg_spm_infra_req_reserved_mask_b;
+	uint8_t reg_spm_apsrc_req_reserved_mask_b;
+	uint8_t reg_spm_vrf18_req_reserved_mask_b;
+	uint8_t reg_spm_ddr_en_reserved_mask_b;
+	uint8_t reg_mcupm_srcclkena_mask_b;
+	uint8_t reg_mcupm_infra_req_mask_b;
+	uint8_t reg_mcupm_apsrc_req_mask_b;
+	uint8_t reg_mcupm_vrf18_req_mask_b;
+	uint8_t reg_mcupm_ddr_en_mask_b;
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	uint8_t reg_msdc0_infra_req_mask_b;
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	uint8_t reg_msdc0_ddr_en_mask_b;
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	uint8_t reg_msdc1_infra_req_mask_b;
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	uint8_t reg_msdc1_ddr_en_mask_b;
+
+	/* SPM_SRC4_MASK */
+	uint32_t ccif_event_mask_b;
+	uint8_t reg_bak_psri_srcclkena_mask_b;
+	uint8_t reg_bak_psri_infra_req_mask_b;
+	uint8_t reg_bak_psri_apsrc_req_mask_b;
+	uint8_t reg_bak_psri_vrf18_req_mask_b;
+	uint8_t reg_bak_psri_ddr_en_mask_b;
+	uint8_t reg_dramc0_md32_infra_req_mask_b;
+	uint8_t reg_dramc0_md32_vrf18_req_mask_b;
+	uint8_t reg_dramc1_md32_infra_req_mask_b;
+	uint8_t reg_dramc1_md32_vrf18_req_mask_b;
+	uint8_t reg_conn_srcclkenb2pwrap_mask_b;
+	uint8_t reg_dramc0_md32_wakeup_mask;
+	uint8_t reg_dramc1_md32_wakeup_mask;
+
+	/* SPM_SRC5_MASK */
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	uint32_t reg_mcusys_merge_ddr_en_mask_b;
+	uint8_t reg_msdc2_srcclkena_mask_b;
+	uint8_t reg_msdc2_infra_req_mask_b;
+	uint8_t reg_msdc2_apsrc_req_mask_b;
+	uint8_t reg_msdc2_vrf18_req_mask_b;
+	uint8_t reg_msdc2_ddr_en_mask_b;
+	uint8_t reg_pcie_srcclkena_mask_b;
+	uint8_t reg_pcie_infra_req_mask_b;
+	uint8_t reg_pcie_apsrc_req_mask_b;
+	uint8_t reg_pcie_vrf18_req_mask_b;
+	uint8_t reg_pcie_ddr_en_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	uint32_t reg_ext_wakeup_event_mask;
+
+	/* Auto-gen End */
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+
+	/* SPM_CLK_CON */
+	PW_REG_SRCCLKEN0_CTL,
+	PW_REG_SRCCLKEN1_CTL,
+	PW_REG_SPM_LOCK_INFRA_DCM,
+	PW_REG_SRCCLKEN_MASK,
+	PW_REG_MD1_C32RM_EN,
+	PW_REG_MD2_C32RM_EN,
+	PW_REG_CLKSQ0_SEL_CTRL,
+	PW_REG_CLKSQ1_SEL_CTRL,
+	PW_REG_SRCCLKEN0_EN,
+	PW_REG_SRCCLKEN1_EN,
+	PW_REG_SYSCLK0_SRC_MASK_B,
+	PW_REG_SYSCLK1_SRC_MASK_B,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+
+	/* SPM_SRC6_MASK */
+	PW_REG_DPMAIF_SRCCLKENA_MASK_B,
+	PW_REG_DPMAIF_INFRA_REQ_MASK_B,
+	PW_REG_DPMAIF_APSRC_REQ_MASK_B,
+	PW_REG_DPMAIF_VRF18_REQ_MASK_B,
+	PW_REG_DPMAIF_DDR_EN_MASK_B,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDR_EN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+
+	/* SPM_SRC_MASK */
+	PW_REG_MD_SRCCLKENA_0_MASK_B,
+	PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
+	PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
+	PW_REG_MD_APSRC_REQ_0_MASK_B,
+	PW_REG_MD_VRF18_REQ_0_MASK_B,
+	PW_REG_MD_DDR_EN_0_MASK_B,
+	PW_REG_MD_SRCCLKENA_1_MASK_B,
+	PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
+	PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
+	PW_REG_MD_APSRC_REQ_1_MASK_B,
+	PW_REG_MD_VRF18_REQ_1_MASK_B,
+	PW_REG_MD_DDR_EN_1_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_CONN_DDR_EN_MASK_B,
+	PW_REG_CONN_VFE28_MASK_B,
+	PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
+	PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
+	PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDR_EN_MASK_B,
+	PW_REG_MD32_SRCCLKENA_MASK_B,
+	PW_REG_MD32_INFRA_REQ_MASK_B,
+	PW_REG_MD32_APSRC_REQ_MASK_B,
+	PW_REG_MD32_VRF18_REQ_MASK_B,
+	PW_REG_MD32_DDR_EN_MASK_B,
+
+	/* SPM_SRC2_MASK */
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDR_EN_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDR_EN_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDR_EN_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDR_EN_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GCE_DDR_EN_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_APU_DDR_EN_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDR_EN_MASK_B,
+
+	/* SPM_SRC3_MASK */
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_SW2SPM_INT0_MASK_B,
+	PW_REG_SW2SPM_INT1_MASK_B,
+	PW_REG_SW2SPM_INT2_MASK_B,
+	PW_REG_SW2SPM_INT3_MASK_B,
+	PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRREQ_MASK,
+	PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
+	PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
+	PW_REG_MCUPM_SRCCLKENA_MASK_B,
+	PW_REG_MCUPM_INFRA_REQ_MASK_B,
+	PW_REG_MCUPM_APSRC_REQ_MASK_B,
+	PW_REG_MCUPM_VRF18_REQ_MASK_B,
+	PW_REG_MCUPM_DDR_EN_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDR_EN_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDR_EN_MASK_B,
+
+	/* SPM_SRC4_MASK */
+	PW_CCIF_EVENT_MASK_B,
+	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+	PW_REG_BAK_PSRI_DDR_EN_MASK_B,
+	PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
+	PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+	PW_REG_DRAMC0_MD32_WAKEUP_MASK,
+	PW_REG_DRAMC1_MD32_WAKEUP_MASK,
+
+	/* SPM_SRC5_MASK */
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
+	PW_REG_MSDC2_SRCCLKENA_MASK_B,
+	PW_REG_MSDC2_INFRA_REQ_MASK_B,
+	PW_REG_MSDC2_APSRC_REQ_MASK_B,
+	PW_REG_MSDC2_VRF18_REQ_MASK_B,
+	PW_REG_MSDC2_DDR_EN_MASK_B,
+	PW_REG_PCIE_SRCCLKENA_MASK_B,
+	PW_REG_PCIE_INFRA_REQ_MASK_B,
+	PW_REG_PCIE_APSRC_REQ_MASK_B,
+	PW_REG_PCIE_VRF18_REQ_MASK_B,
+	PW_REG_PCIE_DDR_EN_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+	PW_MAX_COUNT,
+};
+
+
+#endif /* __PWR_CTRL_H__ */

drivers/misc/mediatek/lpm/modules/include/mt6873/mt6873_spm_comm.h

@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MT6873_SPM_COMM_H__
+#define __MT6873_SPM_COMM_H__
+
+struct mt6873_spm_wake_status {
+	u32 r12;			/* SPM_BK_WAKE_EVENT */
+	u32 r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	u32 raw_sta;		/* SPM_WAKEUP_STA */
+	u32 raw_ext_sta;	/* SPM_WAKEUP_EXT_STA */
+	u32 md32pcm_wakeup_sta;/* MD32CPM_WAKEUP_STA */
+	u32 md32pcm_event_sta;/* MD32PCM_EVENT_STA */
+	u32 wake_misc;		/* SPM_BK_WAKE_MISC */
+	u32 timer_out;		/* SPM_BK_PCM_TIMER */
+	u32 r13;			/* PCM_REG13_DATA */
+	u32 idle_sta;		/* SUBSYS_IDLE_STA */
+	u32 req_sta0;		/* SRC_REQ_STA_0 */
+	u32 req_sta1;		/* SRC_REQ_STA_1 */
+	u32 req_sta2;		/* SRC_REQ_STA_2 */
+	u32 req_sta3;		/* SRC_REQ_STA_3 */
+	u32 req_sta4;		/* SRC_REQ_STA_4 */
+	u32 cg_check_sta;	/* SPM_CG_CHECK_STA */
+	u32 debug_flag;		/* PCM_WDT_LATCH_SPARE_0 */
+	u32 debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	u32 b_sw_flag0;		/* SPM_SW_RSV_7 */
+	u32 b_sw_flag1;		/* SPM_SW_RSV_8 */
+	u32 isr;			/* SPM_IRQ_STA */
+	u32 sw_flag0;		/* SPM_SW_FLAG_0 */
+	u32 sw_flag1;		/* SPM_SW_FLAG_1 */
+	u32 clk_settle;		/* SPM_CLK_SETTLE */
+	u32 src_req;	/* SPM_SRC_REQ */
+	u32 log_index;
+	u32 is_abort;
+	u32 rt_req_sta0; /* SPM_SW_RSV_2 */
+	u32 rt_req_sta1; /* SPM_SW_RSV_3 */
+	u32 rt_req_sta2; /* SPM_SW_RSV_4 */
+	u32 rt_req_sta3; /* SPM_SW_RSV_5 */
+	u32 rt_req_sta4; /* SPM_SW_RSV_6 */
+	u32 mcupm_req_sta;
+};
+
+struct spm_wakesrc_irq_list {
+	unsigned int wakesrc;
+	const char *name;
+	int order;
+	unsigned int irq_no;
+};
+
+enum MTK_LPM_SUSPEND_TYPE {
+	MTK_LPM_SUSPEND_SYSTEM,
+	MTK_LPM_SUSPEND_S2IDLE,
+};
+
+/* MD sleep status */
+
+struct md_sleep_status {
+	u64 sleep_wall_clk;
+	u64 sleep_cnt;
+	u64 sleep_cnt_reserve;
+	u64 sleep_time; // 32k
+	u64 sleep_time_reserve;
+	u64 md_sleep_time; // uS
+	u64 gsm_sleep_time; // uS
+	u64 wcdma_sleep_time; //uS
+	u64 lte_sleep_time; // uS
+	u64 nr_sleep_time; // uS
+};
+
+#define MTK_LP_PREPARE_FAIL		(1<<4L)
+
+extern u32 mt_irq_get_pending(unsigned int irq);
+int mtk_lpm_suspend_type_get(void);
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ * From Legacy sleep_def.h
+ */
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN		(1 << 0u)
+#define SPM_FLAG_DISABLE_INFRA_PDN		(1 << 1u)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN		(1 << 2u)
+#define SPM_FLAG_DISABLE_VCORE_DVS		(1 << 3u)
+#define SPM_FLAG_DISABLE_VCORE_DFS		(1 << 4u)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO	(1 << 5u)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF		(1 << 6u)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF		(1 << 7u)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH		(1 << 8u)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND		(1 << 9u)
+#define SPM_FLAG_RUN_COMMON_SCENARIO		(1 << 10u)
+#define SPM_FLAG_RESERVED_BIT11			(1 << 11u)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP	(1 << 12u)
+#define SPM_FLAG_USE_SRCCLKENO2			(1 << 13u)
+#define SPM_FLAG_ENABLE_6315_CTRL		(1 << 14u)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND		(1 << 15u)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP		(1 << 16u)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP	(1 << 17u)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP	(1 << 18u)
+#define SPM_FLAG_RESERVED_BIT19			(1 << 19u)
+#define SPM_FLAG_RESERVED_BIT20			(1 << 20u)
+#define SPM_FLAG_RESERVED_BIT21			(1 << 21u)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP	(1 << 22u)
+#define SPM_FLAG_RESERVED_BIT23			(1 << 23u)
+#define SPM_FLAG_RESERVED_BIT24			(1 << 24u)
+#define SPM_FLAG_RESERVED_BIT25			(1 << 25u)
+#define SPM_FLAG_RESERVED_BIT26			(1 << 26u)
+#define SPM_FLAG_VTCXO_STATE			(1 << 27u)
+#define SPM_FLAG_INFRA_STATE			(1 << 28u)
+#define SPM_FLAG_APSRC_STATE			(1 << 29u)
+#define SPM_FLAG_VRF18_STATE			(1 << 30u)
+#define SPM_FLAG_DDREN_STATE			(1 << 31u)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M      (1 << 0u)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF          (1 << 1u)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH    (1 << 2u)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF          (1 << 3u)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON            (1 << 4u)
+#define SPM_FLAG1_RESERVED_BIT5               (1 << 5u)
+#define SPM_FLAG1_ENABLE_REKICK               (1 << 6u)
+#define SPM_FLAG1_RESERVED_BIT7               (1 << 7u)
+#define SPM_FLAG1_RESERVED_BIT8               (1 << 8u)
+#define SPM_FLAG1_RESERVED_BIT9               (1 << 9u)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW         (1 << 10u)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH      (1 << 11u)
+#define SPM_FLAG1_RESERVED_BIT12              (1 << 12u)
+#define SPM_FLAG1_RESERVED_BIT13              (1 << 13u)
+#define SPM_FLAG1_RESERVED_BIT14              (1 << 14u)
+#define SPM_FLAG1_RESERVED_BIT15              (1 << 15u)
+#define SPM_FLAG1_RESERVED_BIT16              (1 << 16u)
+#define SPM_FLAG1_RESERVED_BIT17              (1 << 17u)
+#define SPM_FLAG1_RESERVED_BIT18              (1 << 18u)
+#define SPM_FLAG1_RESERVED_BIT19              (1 << 19u)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP   (1 << 20u)
+#define SPM_FLAG1_RESERVED_BIT21              (1 << 21u)
+#define SPM_FLAG1_ENABLE_VS1_VOTER            (1 << 22u)
+#define SPM_FLAG1_ENABLE_VS2_VOTER            (1 << 23u)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL   (1 << 24u)
+#define SPM_FLAG1_RESERVED_BIT25              (1 << 25u)
+#define SPM_FLAG1_RESERVED_BIT26              (1 << 26u)
+#define SPM_FLAG1_RESERVED_BIT27              (1 << 27u)
+#define SPM_FLAG1_RESERVED_BIT28              (1 << 28u)
+#define SPM_FLAG1_RESERVED_BIT29              (1 << 29u)
+#define SPM_FLAG1_RESERVED_BIT30              (1 << 30u)
+#define SPM_FLAG1_DISABLE_CPUTOEB_OFF              (1 << 31u)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE			(1 << 0u)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP			(1 << 1u)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE			(1 << 2u)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP			(1 << 3u)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE			(1 << 4u)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP			(1 << 5u)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE			(1 << 6u)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP			(1 << 7u)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE			(1 << 8u)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP			(1 << 9u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC	(1 << 10u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE		(1 << 11u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE		(1 << 12u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN	(1 << 13u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE		(1 << 14u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP			(1 << 15u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON			(1 << 16u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP		(1 << 17u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON			(1 << 18u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP			(1 << 19u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON			(1 << 20u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP		(1 << 21u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON		(1 << 22u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V		(1 << 23u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V		(1 << 24u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V		(1 << 25u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V		(1 << 26u)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW		(1 << 27u)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE			(1 << 28u)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE			(1 << 29u)
+#define SPM_DBG_DEBUG_IDX_VRF18_STATE			(1 << 30u)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE			(1 << 31u)
+
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP		(1 << 0u)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START		(1 << 1u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF			(1 << 2u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON			(1 << 3u)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS	(1 << 4u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF		(1 << 5u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON		(1 << 6u)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT		(1 << 7u)
+#define SPM_DBG1_RESERVED_BIT8				(1 << 8u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF		(1 << 9u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON		(1 << 10u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC		(1 << 11u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M		(1 << 12u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K		(1 << 13u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M		(1 << 14u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF			(1 << 15u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON			(1 << 16u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW			(1 << 17u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH		(1 << 18u)
+#define SPM_DBG1_RESERVED_BIT19				(1 << 19u)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	(1 << 20u)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW			(1 << 21u)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH                    (1 << 22u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT    (1 << 23u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT   (1 << 24u)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT           (1 << 25u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT        (1 << 26u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT       (1 << 27u)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT       (1 << 28u)
+#define SPM_DBG1_RESERVED_BIT29				(1 << 29u)
+#define SPM_DBG1_RESERVED_BIT30				(1 << 30u)
+#define SPM_DBG1_RESERVED_BIT31				(1 << 31u)
+
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC \
+	| SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6873/mtk_lp_plat_apmcu.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef __MTK_LP_PLAT_APMCU_H__
+#define __MTK_LP_PLAT_APMCU_H__
+
+#include <linux/types.h>
+
+#define nr_cluster_ids                  (1)
+#define get_physical_cluster_id(cpu)    (0)
+
+#define LP_PM_SYSRAM_INFO_OFS  0x8
+#define LP_PM_SYSRAM_SIZE      0x500
+
+extern void __iomem *cpu_pm_syssram_base;
+/* 0x11B000 */
+#define MT_CPU_PM_KERNEL_SRAMBASE	(cpu_pm_syssram_base + 0x100)
+#define MT_CPU_PM_KERNEL_SRAM(slot)	(MT_CPU_PM_KERNEL_SRAMBASE + (slot<<2))
+
+
+#define cpu_pm_sync_writel(v, a)				\
+do {								\
+	__raw_writel((v), (void __force __iomem *)((a)));	\
+	mb(); /*make sure register access in order */		\
+} while (0)
+
+#define MT_CPU_PM_KERNEL_SRAM_WR(slot, val) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			cpu_pm_sync_writel(val,\
+				MT_CPU_PM_KERNEL_SRAM(slot)); uval; })
+
+
+#define MT_CPU_PM_KERNEL_SRAM_RD(slot) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			uval = __raw_readl(MT_CPU_PM_KERNEL_SRAM(slot));\
+		uval; })
+
+void mtk_lp_plat_set_mcusys_off(int cpu);
+void mtk_lp_plat_clr_mcusys_off(int cpu);
+
+void mtk_lp_plat_set_cluster_off(int cpu);
+void mtk_lp_plat_clr_cluster_off(int cpu);
+
+bool mtk_lp_plat_is_mcusys_off(void);
+bool mtk_lp_plat_is_cluster_off(int cpu);
+
+int mtk_lp_plat_apmcu_init(void);
+int mtk_lp_plat_apmcu_early_init(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6873/mtk_lp_plat_apmcu_mbox.h

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_LP_PLAT_APMCU_MBOX_H__
+#define __MTK_LP_PLAT_APMCU_MBOX_H__
+
+enum {
+	MBOX_SSPM,
+	MBOX_MCUPM,
+
+	NF_MBOX,
+};
+
+/* SSPM Mbox */
+#define APMCU_SSPM_MBOX_ID           3
+#define APMCU_SSPM_MBOX_SPM_CMD_SIZE 8
+
+#define APMCU_SSPM_MBOX_SPM_CMD      0
+#define APMCU_SSPM_MBOX_SPM_ARGS1    1
+#define APMCU_SSPM_MBOX_SPM_ARGS2    2
+#define APMCU_SSPM_MBOX_SPM_ARGS3    3
+#define APMCU_SSPM_MBOX_SPM_ARGS4    4
+#define APMCU_SSPM_MBOX_SPM_ARGS5    5
+#define APMCU_SSPM_MBOX_SPM_ARGS6    6
+#define APMCU_SSPM_MBOX_SPM_ARGS7    7
+#define APMCU_SSPM_MBOX_AP_READY     17
+
+void mtk_set_sspm_lp_cmd(void *buf);
+void mtk_clr_sspm_lp_cmd(void);
+
+
+/* MCUPM Mbox */
+
+#define APMCU_MCUPM_MBOX_ID             3
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY       0
+#define APMCU_MCUPM_MBOX_RESERVED_1     1
+#define APMCU_MCUPM_MBOX_RESERVED_2     2
+#define APMCU_MCUPM_MBOX_RESERVED_3     3
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN    4
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE  5
+#define APMCU_MCUPM_MBOX_BUCK_MODE      6
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE    7
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA       8
+#define APMCU_MCUPM_MBOX_RESERVED_9     9
+#define APMCU_MCUPM_MBOX_RESERVED_10    10
+#define APMCU_MCUPM_MBOX_RESERVED_11    11
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU     12
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN (4) */
+#define MCUPM_MCUSYS_CTRL               (1 << 0)
+#define MCUPM_BUCK_CTRL                 (1 << 1)
+#define MCUPM_ARMPLL_CTRL               (1 << 2)
+#define MCUPM_CM_CTRL                   (1 << 3)
+#define MCUPM_PWR_CTRL_MASK             ((1 << 4) - 1)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_L3_CACHE_MODE (5) */
+#define MCUPM_L3_OFF_MODE               0 /* default */
+#define MCUPM_L3_DORMANT_MODE           1
+#define NF_MCUPM_L3_MODE                2U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE (6) */
+#define MCUPM_BUCK_NORMAL_MODE          0 /* default */
+#define MCUPM_BUCK_LP_MODE              1
+#define MCUPM_BUCK_OFF_MODE             2
+#define NF_MCUPM_BUCK_MODE              3U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE (7) */
+#define MCUPM_ARMPLL_ON                 0 /* default */
+#define MCUPM_ARMPLL_GATING             1
+#define MCUPM_ARMPLL_OFF                2
+#define NF_MCUPM_ARMPLL_MODE            3U
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA (9) */
+#define MCUPM_TASK_UNINIT               0
+#define MCUPM_TASK_INIT                 1
+#define MCUPM_TASK_INIT_FINISH          2
+#define MCUPM_TASK_WAIT                 3
+#define MCUPM_TASK_RUN                  4
+#define MCUPM_TASK_PAUSE                5
+
+bool mtk_mcupm_cm_is_notified(void);
+
+void mtk_set_mcupm_pll_mode(unsigned int mode);
+int mtk_get_mcupm_pll_mode(void);
+
+void mtk_set_mcupm_buck_mode(unsigned int mode);
+int mtk_get_mcupm_buck_mode(void);
+
+void mtk_set_preferred_cpu_wakeup(int cpu);
+int mtk_get_preferred_cpu_wakeup(void);
+
+bool mtk_mcupm_is_ready(void);
+
+void mtk_wait_mbox_init_done(void);
+void mtk_notify_subsys_ap_ready(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6873/mtk_lp_plat_reg.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_PLAT_CPC_REG_H__
+#define __MTK_PLAT_CPC_REG_H__
+
+/**************************************
+ * CPC related register
+ * base address = 0x0C53A000
+ **************************************/
+#define CPC_FLOW_CTRL_CFG              (0x814)
+#define CPC_MCUSYS_LAST_CORE_REQ       (0x818)
+#define CPC_CPUSYS_LAST_CORE_RESP      (0x81C)
+#define CPC_MCUSYS_LAST_CORE_RESP      (0x824)
+#define CPC_PWR_ON_MASK                (0x828)
+#define CPC_SPMC_PWR_STATUS            (0x840)
+#define CPC_CPUSYS_CPU_ON_SW_HINT_CLR  (0x8AC)
+
+#define SPMC_DBG_SETTING               (0xB00)
+
+#define CPC_TRACE_DATA_SEL             (0xB14)
+
+#define CPC_CPU0_LATENCY               (0xB40)
+#define CPC_CPU1_LATENCY               (0xB44)
+#define CPC_CPU2_LATENCY               (0xB48)
+#define CPC_CPU3_LATENCY               (0xB4C)
+#define CPC_CPU4_LATENCY               (0xB50)
+#define CPC_CPU5_LATENCY               (0xB54)
+#define CPC_CPU6_LATENCY               (0xB58)
+#define CPC_CPU7_LATENCY               (0xB5C)
+#define CPC_CLUSTER_OFF_LATENCY        (0xB60)
+#define CPC_CLUSTER_ON_LATENCY         (0xB64)
+#define CPC_MCUSYS_LATENCY             (0xB68)
+#define CPC_DORMANT_COUNTER            (0xB70)
+#define CPC_DORMANT_COUNTER_CLR        (0xB74)
+#define CPC_CPU_LATENCY(cpu)           ((CPC_CPU0_LATENCY) + 4 * (cpu))
+
+/**************************************
+ * system sram for apmcu debug
+ * base address = 0x0011B000
+ **************************************/
+#define SYSRAM_CPUSYS_CNT              (0x1E8)
+#define SYSRAM_MCUSYS_CNT              (0x1EC)
+#define SYSRAM_CPC_CPUSYS_CNT_BACKUP   (0x1F0)
+#define SYSRAM_MCUPM_MCUSYS_COUNTER    (0x1F4)
+#define SYSRAM_CPU_ONLINE              (0x1F8)
+
+/* Run time information. The registers may be cleared in db dump flow */
+#define SYSRAM_RECENT_CPU_CNT(i)       (4 * (i) + 0x1B0)
+#define SYSRAM_RECENT_CPUSYS_CNT       (0x1D0)
+#define SYSRAM_RECENT_MCUSYS_CNT       (0x1D4)
+#define SYSRAM_RECENT_CNT_TS_L         (0x1D8)
+#define SYSRAM_RECENT_CNT_TS_H         (0x1DC)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6877/mt6877_cond.h

@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MT6877_COND_H__
+#define __MT6877_COND_H__
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]    : idle condition check fail
+ */
+
+#define SPM_COND_BLOCKED_CG_IDX		(0)
+#define SPM_COND_BLOCKED_PLL_IDX	(16)
+#define SPM_COND_BLOCKED_PLL		(1<<30L)
+#define SPM_COND_CHECK_FAIL		(1<<31L)
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS_1 = 0,
+	PLAT_SPM_COND_MTCMOS_2,
+	PLAT_SPM_COND_CG_INFRA_0,
+	PLAT_SPM_COND_CG_INFRA_1,
+	PLAT_SPM_COND_CG_INFRA_2,
+	PLAT_SPM_COND_CG_INFRA_3,
+	PLAT_SPM_COND_CG_INFRA_4,
+	PLAT_SPM_COND_CG_INFRA_5,
+	PLAT_SPM_COND_CG_MMSYS_0,
+	PLAT_SPM_COND_CG_MMSYS_1,
+	PLAT_SPM_COND_CG_MMSYS_2,
+	PLAT_SPM_COND_CG_MMSYS_3,
+	PLAT_SPM_COND_CG_MMSYS_4,
+	PLAT_SPM_COND_CG_MMSYS_5,
+	PLAT_SPM_COND_CG_MMSYS_6,
+	PLAT_SPM_COND_CG_MMSYS_7,
+	PLAT_SPM_COND_MAX,
+};
+
+enum PLAT_SPM_PLL_COND {
+	PLAT_SPM_COND_UNIVPLL = 0,
+	PLAT_SPM_COND_PLL_MFGPLL1,
+	PLAT_SPM_COND_PLL_MFGPLL4,
+	PLAT_SPM_COND_MSDCPLL,
+	PLAT_SPM_COND_TVPLL,
+	PLAT_SPM_COND_MMPLL,
+	PLAT_SPM_COND_PLL_MAX,
+};
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6877/mt6877_pcm_def.h

@@ -0,0 +1,189 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __pcm_def_h__
+#define __pcm_def_h__
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define CTRL0_SC_26M_CK_OFF                   (1U << 0)
+#define CTRL0_SC_EMI_CK_OFF                   (1U << 2)
+#define CTRL0_SC_AXI_CK_OFF                   (1U << 3)
+#define CTRL0_SC_AXI_MEM_CK_OFF               (1U << 4)
+#define CTRL0_SC_MD26M_CK_OFF                 (1U << 5)
+#define CTRL0_SC_MD32K_CK_OFF                 (1U << 6)
+#define CTRL0_SC_26M_CK_SEL                   (1U << 8)
+#define CTRL0_SC_MEM_CK_26M_SEL               (1U << 9)
+#define CTRL0_CPU_SYS_TIMER_CLK_SEL           (1U << 10)
+#define CTRL0_SC_CIRQ_CLK_32K_SEL             (1U << 11)
+#define CTRL0_SC_AXI_DCM_DIS                  (1U << 12)
+#define CTRL0_SC_CKSQ0_OFF                    (1U << 20)
+#define CTRL0_SC_CKSQ1_OFF                    (1U << 21)
+/* --- R7 Define --- */
+#define CTRL1_PWRAP_SLEEP_REQ                 (1U << 0)
+#define CTRL1_BUS_PROTECT_REQ                 (1U << 2)
+#define CTRL1_SPM_CK_SEL0                     (1U << 4)
+#define CTRL1_SPM_CK_SEL1                     (1U << 5)
+#define CTRL1_PCM_TIMER_SET                   (1U << 8)
+#define CTRL1_PCM_TIMER_CLR                   (1U << 9)
+#define CTRL1_SPM_LEAVE_DEEPIDLE_REQ          (1U << 10)
+#define CTRL1_SPM_LEAVE_SUSPEND_REQ           (1U << 11)
+#define CTRL1_CSYSPWRUPACK                    (1U << 12)
+#define CTRL1_IM_SLEEP_ENABLE                 (1U << 13)
+#define CTRL1_SRCCLKENO                       (1U << 14)
+#define CTRL1_SRCCLKENO1                      (1U << 15)
+#define CTRL1_SPM_APSRC_INTERNAL_ACK          (1U << 16)
+#define CTRL1_SPM_DDR_EN_INTERNAL_ACK         (1U << 17)
+#define CTRL1_SPM_INFRA_INTERNAL_ACK          (1U << 18)
+#define CTRL1_SPM_VRF18_INTERNAL_ACK          (1U << 19)
+#define CTRL1_PMIC_IRQ_REQ_EN                 (1U << 20)
+#define CTRL1_WDT_KICK_P                      (1U << 22)
+#define CTRL1_SC_DDR_PST_REQ                  (1U << 24)
+#define CTRL1_SC_DDR_PST_ABORT_REQ            (1U << 25)
+#define CTRL1_FORCE_DDREN_ON                  (1U << 26)
+#define CTRL1_FORCE_F26M_ON                   (1U << 27)
+#define CTRL1_FORCE_APSRC_ON                  (1U << 28)
+#define CTRL1_FORCE_INFRA_ON                  (1U << 29)
+#define CTRL1_FORCE_VRF18_ON                  (1U << 30)
+#define CTRL1_FORCE_VCORE_ON                  (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER_B                       (1U << 0)
+#define R12_SPM_DEBUG_B                       (1U << 1)
+#define R12_KP_IRQ_B                          (1U << 2)
+#define R12_APWDT_EVENT_B                     (1U << 3)
+#define R12_APXGPT_EVENT_B                    (1U << 4)
+#define R12_CONN2AP_WAKEUP_B                  (1U << 5)
+#define R12_EINT_EVENT_B                      (1U << 6)
+#define R12_CONN_WDT_IRQ_B                    (1U << 7)
+#define R12_CCIF0_EVENT_B                     (1U << 8)
+#define R12_LOWBATTERY_IRQ_B                  (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B                 (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B                  (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B                 (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B                  (1U << 13)
+#define R12_USB0_CDSC_B                       (1U << 14)
+#define R12_USB0_POWERDWN_B                   (1U << 15)
+#define R12_SYS_TIMER_EVENT_B                 (1U << 16)
+#define R12_EINT_EVENT_SECURE_B               (1U << 17)
+#define R12_CCIF1_EVENT_B                     (1U << 18)
+#define R12_UART0_IRQ_B                       (1U << 19)
+#define R12_AFE_IRQ_MCU_B                     (1U << 20)
+#define R12_THERM_CTRL_EVENT_B                (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B                    (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B                (1U << 23)
+#define R12_CSYSPWREQ_B                       (1U << 24)
+#define R12_MD_WDT_B                          (1U << 25)
+#define R12_AP2AP_PEER_WAKEUP_B               (1U << 26)
+#define R12_SEJ_B                             (1U << 27)
+#define R12_CPU_WAKEUP                        (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B                (1U << 29)
+#define R12_CPU_IRQOUT_B                      (1U << 30)
+#define R12_MCUSYS_IDLE_B                     (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE                       (1U << 0)
+#define R12EXT_26M_SLEEP                      (1U << 1)
+#define R12EXT_INFRA_WAKE                     (1U << 2)
+#define R12EXT_INFRA_SLEEP                    (1U << 3)
+#define R12EXT_APSRC_WAKE                     (1U << 4)
+#define R12EXT_APSRC_SLEEP                    (1U << 5)
+#define R12EXT_VRF18_WAKE                     (1U << 6)
+#define R12EXT_VRF18_SLEEP                    (1U << 7)
+#define R12EXT_DVFS_WAKE                      (1U << 8)
+#define R12EXT_DDREN_WAKE                     (1U << 9)
+#define R12EXT_DDREN_SLEEP                    (1U << 10)
+#define R12EXT_MCU_PM_WFI                     (1U << 11)
+#define R12EXT_SSPM_IDLE                      (1U << 12)
+#define R12EXT_CONN_SRCCLKENB                 (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE           (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE                (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE              (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE              (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE               (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK          (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK         (1U << 20)
+#define R12EXT_BIT21                          (1U << 21)
+#define R12EXT_BIT22                          (1U << 22)
+#define R12EXT_BIT23                          (1U << 23)
+#define R12EXT_BIT24                          (1U << 24)
+#define R12EXT_BIT25                          (1U << 25)
+#define R12EXT_BIT26                          (1U << 26)
+#define R12EXT_BIT27                          (1U << 27)
+#define R12EXT_BIT28                          (1U << 28)
+#define R12EXT_BIT29                          (1U << 29)
+#define R12EXT_BIT30                          (1U << 30)
+#define R12EXT_BIT31                          (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0                        (1U << 0)
+#define R13_SRCCLKENI1                        (1U << 1)
+#define R13_MD_SRCCLKENA_0                    (1U << 2)
+#define R13_MD_SRCCLKENA_1                    (1U << 3)
+#define R13_MD_DDR_EN_0                       (1U << 4)
+#define R13_CONN_DDR_EN                       (1U << 5)
+#define R13_MD32_SRCCLKENA                    (1U << 6)
+#define R13_MD32_APSRC_REQ                    (1U << 7)
+#define R13_MD1_STATE                         (1U << 8)
+#define R13_RC2SPM_SRCCLKENO_0_ACK            (1U << 9)
+#define R13_MM_STATE                          (1U << 10)
+#define R13_MD32_STATE                        (1U << 11)
+#define R13_CONN_STATE                        (1U << 13)
+#define R13_CONN_SRCCKENA                     (1U << 14)
+#define R13_CONN_APSRC_REQ                    (1U << 15)
+#define R13_SC_DDR_PST_ACK                    (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK              (1U << 17)
+#define R13_SCP_STATE                         (1U << 18)
+#define R13_CSYSPWRUPREQ                      (1U << 19)
+#define R13_PWRAP_SLEEP_ACK                   (1U << 20)
+#define R13_AUDIO_DSP_STATE                   (1U << 22)
+#define R13_CONN_SRCCLKENB                    (1U << 24)
+#define R13_INFRA_AUX_IDLE                    (1U << 26)
+#define R13_DVFS_STATE                        (1U << 27)
+#define R13_MD_VRF18_REQ_0                    (1U << 30)
+#define R13_DDR_EN_STATE                      (1U << 31)
+
+enum SPM_WAKE_SRC_LIST {
+	WAKE_SRC_STA1_PCM_TIMER = (1U << 0),
+	WAKE_SRC_STA1_RESERVED_DEBUG_B = (1U << 1),
+	WAKE_SRC_STA1_KP_IRQ_B = (1U << 2),
+	WAKE_SRC_STA1_APWDT_EVENT_B = (1U << 3),
+	WAKE_SRC_STA1_APXGPT1_EVENT_B = (1U << 4),
+	WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B = (1U << 5),
+	WAKE_SRC_STA1_EINT_EVENT_B = (1U << 6),
+	WAKE_SRC_STA1_CONN_WDT_IRQ_B = (1U << 7),
+	WAKE_SRC_STA1_CCIF0_EVENT_B = (1U << 8),
+	WAKE_SRC_STA1_LOWBATTERY_IRQ_B = (1U << 9),
+	WAKE_SRC_STA1_SC_SSPM2SPM_WAKEUP_B = (1U << 10),
+	WAKE_SRC_STA1_SC_SCP2SPM_WAKEUP_B = (1U << 11),
+	WAKE_SRC_STA1_SC_ADSP2SPM_WAKEUP_B = (1U << 12),
+	WAKE_SRC_STA1_PCM_WDT_WAKEUP_B = (1U << 13),
+	WAKE_SRC_STA1_USB_CDSC_B = (1U << 14),
+	WAKE_SRC_STA1_USB_POWERDWN_B = (1U << 15),
+	WAKE_SRC_STA1_SYS_TIMER_EVENT_B = (1U << 16),
+	WAKE_SRC_STA1_EINT_EVENT_SECURE_B = (1U << 17),
+	WAKE_SRC_STA1_CCIF1_EVENT_B = (1U << 18),
+	WAKE_SRC_STA1_UART0_IRQ_B = (1U << 19),
+	WAKE_SRC_STA1_AFE_IRQ_MCU_B = (1U << 20),
+	WAKE_SRC_STA1_THERM_CTRL_EVENT_B = (1U << 21),
+	WAKE_SRC_STA1_SYS_CIRQ_IRQ_B = (1U << 22),
+	WAKE_SRC_STA1_MD2AP_PEER_EVENT_B = (1U << 23),
+	WAKE_SRC_STA1_CSYSPWREQ_B = (1U << 24),
+	WAKE_SRC_STA1_MD1_WDT_B = (1U << 25),
+	WAKE_SRC_STA1_AP2AP_PEER_WAKEUPEVENT_B = (1U << 26),
+	WAKE_SRC_STA1_SEJ_EVENT_B = (1U << 27),
+	WAKE_SRC_STA1_SPM_CPU_WAKEUPEVENT_B = (1U << 28),
+	WAKE_SRC_STA1_APUSYS = (1U << 29),
+	WAKE_SRC_STA1_PCIE_BRIDGE_IRQ = (1U << 30),
+	WAKE_SRC_STA1_PCIE_IRQ = (1U << 31)
+};
+
+extern const char *wakesrc_str[32];
+
+/* define WAKE_SRC_CONN2AP for conn use */
+#define WAKE_SRC_CONN2AP WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B
+
+#endif /* __pcm_def_h__ */

drivers/misc/mediatek/lpm/modules/include/mt6877/mt6877_pwr_ctrl.h

@@ -0,0 +1,406 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __PWR_CTRL_H__
+#define __PWR_CTRL_H__
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP              0x3FF  /* bit0 ~ bit9 */
+#define WAKE_MISC_DVFSRC_IRQ	         (1U << 16)
+#define WAKE_MISC_REG_CPU_WAKEUP         (1U << 17)
+#define WAKE_MISC_PCM_TIMER_EVENT        (1U << 18)
+#define WAKE_MISC_PMIC_OUT_B		     ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B             (1U << 21)
+#define WAKE_MISC_PMSR_IRQ_B_SET0        (1U << 22)
+#define WAKE_MISC_PMSR_IRQ_B_SET1        (1U << 23)
+#define WAKE_MISC_PMSR_IRQ_B_SET2        (1U << 24)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0   (1U << 25)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1	 (1U << 26)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2	 (1U << 27)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3	 (1U << 28)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL (1U << 29)
+#define WAKE_MISC_PMIC_IRQ_ACK			 (1U << 30)
+#define WAKE_MISC_PMIC_SCP_IRQ			 (1U << 31)
+
+struct pwr_ctrl {
+
+	/* for SPM */
+	uint32_t pcm_flags;
+	uint32_t pcm_flags_cust;
+	uint32_t pcm_flags_cust_set;
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	uint32_t pcm_flags1_cust;
+	uint32_t pcm_flags1_cust_set;
+	uint32_t pcm_flags1_cust_clr;
+	uint32_t timer_val;
+	uint32_t timer_val_cust;
+	uint32_t timer_val_ramp_en;
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	uint32_t wake_src_cust;
+	uint32_t wakelock_timer_val;
+	uint8_t wdt_disable;
+	/* Auto-gen Start */
+
+	/* SPM_CLK_CON */
+	uint8_t reg_spm_lock_infra_dcm_lsb;
+	uint8_t reg_md1_c32rm_en_lsb;
+	uint8_t reg_spm_leave_suspend_merge_mask_lsb;
+	uint8_t reg_sysclk0_src_mask_b_lsb;
+	uint8_t reg_sysclk1_src_mask_b_lsb;
+
+	/* SPM_AP_STANDBY_CON */
+	uint8_t reg_wfi_op;
+	uint8_t reg_wfi_type;
+	uint8_t reg_mp0_cputop_idle_mask;
+	uint8_t reg_mp1_cputop_idle_mask;
+	uint8_t reg_mcusys_idle_mask;
+	uint8_t reg_wfi_af_sel;
+	uint8_t reg_cpu_sleep_wfi;
+
+	/* SPM_SRC_REQ */
+	uint8_t reg_spm_adsp_mailbox_req;
+	uint8_t reg_spm_apsrc_req;
+	uint8_t reg_spm_ddren_req;
+	uint8_t reg_spm_dvfs_req;
+	uint8_t reg_spm_f26m_req;
+	uint8_t reg_spm_infra_req;
+	uint8_t reg_spm_scp_mailbox_req;
+	uint8_t reg_spm_sspm_mailbox_req;
+	uint8_t reg_spm_sw_mailbox_req;
+	uint8_t reg_spm_vcore_req;
+	uint8_t reg_spm_vrf18_req;
+
+	/* SPM_SRC_MASK_0 */
+	uint8_t reg_afe_apsrc_req_mask_b;
+	uint8_t reg_afe_ddren_req_mask_b;
+	uint8_t reg_afe_infra_req_mask_b;
+	uint8_t reg_afe_srcclkena_mask_b;
+	uint8_t reg_afe_vrf18_req_mask_b;
+	uint8_t reg_apu_apsrc_req_mask_b;
+	uint8_t reg_apu_ddren_req_mask_b;
+	uint8_t reg_apu_infra_req_mask_b;
+	uint8_t reg_apu_srcclkena_mask_b;
+	uint8_t reg_apu_vrf18_req_mask_b;
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	uint8_t reg_audio_dsp_ddren_req_mask_b;
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	uint32_t reg_ccif_event_apsrc_req_mask_b;
+
+	/* SPM_SRC_MASK_1 */
+	uint32_t reg_ccif_event_infra_req_mask_b;
+	uint32_t reg_ccif_event_srcclkena_mask_b;
+
+	/* SPM_SRC_MASK_2 */
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	uint8_t reg_cg_check_ddren_req_mask_b;
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	uint8_t reg_cg_check_vcore_req_mask_b;
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	uint8_t reg_conn_apsrc_req_mask_b;
+	uint8_t reg_conn_ddren_req_mask_b;
+	uint8_t reg_conn_infra_req_mask_b;
+	uint8_t reg_conn_srcclkena_mask_b;
+	uint8_t reg_conn_srcclkenb_mask_b;
+	uint8_t reg_conn_vrf18_req_mask_b;
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	uint8_t reg_disp0_ddren_req_mask_b;
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	uint8_t reg_disp1_ddren_req_mask_b;
+	uint8_t reg_dpmaif_apsrc_req_mask_b;
+	uint8_t reg_dpmaif_ddren_req_mask_b;
+	uint8_t reg_dpmaif_infra_req_mask_b;
+	uint8_t reg_dpmaif_srcclkena_mask_b;
+	uint8_t reg_dpmaif_vrf18_req_mask_b;
+	uint8_t reg_dramc_md32_apsrc_req_mask_b;
+	uint8_t reg_dramc_md32_infra_req_mask_b;
+	uint8_t reg_dramc_md32_vrf18_req_mask_b;
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+	uint8_t reg_gce_apsrc_req_mask_b;
+	uint8_t reg_gce_ddren_req_mask_b;
+	uint8_t reg_gce_infra_req_mask_b;
+	uint8_t reg_gce_vrf18_req_mask_b;
+	uint8_t reg_gpueb_apsrc_req_mask_b;
+
+	/* SPM_SRC_MASK_3 */
+	uint8_t reg_gpueb_ddren_req_mask_b;
+	uint8_t reg_gpueb_idle_mask_b;
+	uint8_t reg_gpueb_infra_req_mask_b;
+	uint8_t reg_gpueb_srcclkena_mask_b;
+	uint8_t reg_gpueb_vrf18_req_mask_b;
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	uint8_t reg_infrasys_ddren_req_mask_b;
+	uint8_t reg_mcupm_apsrc_req_mask_b;
+	uint8_t reg_mcupm_ddren_req_mask_b;
+	uint8_t reg_mcupm_idle_mask_b;
+	uint8_t reg_mcupm_infra_req_mask_b;
+	uint8_t reg_mcupm_srcclkena_mask_b;
+	uint8_t reg_mcupm_vrf18_req_mask_b;
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	uint32_t reg_mcusys_merge_ddren_req_mask_b;
+	uint8_t reg_md_apsrc_req_mask_b;
+
+	/* SPM_SRC_MASK_4 */
+	uint8_t reg_md_ddren_req_mask_b;
+	uint8_t reg_md_infra_req_mask_b;
+	uint8_t reg_md_srcclkena_mask_b;
+	uint8_t reg_md_srcclkena1_mask_b;
+	uint8_t reg_md_vrf18_req_mask_b;
+	uint8_t reg_mmsys_apsrc_req_mask_b;
+	uint8_t reg_mmsys_ddren_req_mask_b;
+	uint8_t reg_mmsys_vrf18_req_mask_b;
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	uint8_t reg_msdc0_ddren_req_mask_b;
+	uint8_t reg_msdc0_infra_req_mask_b;
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	uint8_t reg_msdc1_ddren_req_mask_b;
+	uint8_t reg_msdc1_infra_req_mask_b;
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	uint8_t reg_msdc2_apsrc_req_mask_b;
+	uint8_t reg_msdc2_ddren_req_mask_b;
+	uint8_t reg_msdc2_infra_req_mask_b;
+	uint8_t reg_msdc2_srcclkena_mask_b;
+	uint8_t reg_msdc2_vrf18_req_mask_b;
+	uint8_t reg_pcie_apsrc_req_mask_b;
+	uint8_t reg_pcie_ddren_req_mask_b;
+	uint8_t reg_pcie_infra_req_mask_b;
+	uint8_t reg_pcie_srcclkena_mask_b;
+	uint8_t reg_pcie_vrf18_req_mask_b;
+	uint8_t reg_scp_apsrc_req_mask_b;
+	uint8_t reg_scp_ddren_req_mask_b;
+	uint8_t reg_scp_infra_req_mask_b;
+	uint8_t reg_scp_srcclkena_mask_b;
+
+	/* SPM_SRC_MASK_5 */
+	uint8_t reg_scp_vrf18_req_mask_b;
+	uint8_t reg_spm_reserved_apsrc_req_mask_b;
+	uint8_t reg_spm_reserved_ddren_req_mask_b;
+	uint8_t reg_spm_reserved_infra_req_mask_b;
+	uint8_t reg_spm_reserved_srcclkena_mask_b;
+	uint8_t reg_spm_reserved_vrf18_req_mask_b;
+	uint8_t reg_srcclkeni_infra_req_mask_b;
+	uint8_t reg_srcclkeni_srcclkena_mask_b;
+	uint8_t reg_sspm_apsrc_req_mask_b;
+	uint8_t reg_sspm_ddren_req_mask_b;
+	uint8_t reg_sspm_idle_mask_b;
+	uint8_t reg_sspm_infra_req_mask_b;
+	uint8_t reg_sspm_srcclkena_mask_b;
+	uint8_t reg_sspm_vrf18_req_mask_b;
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	uint8_t reg_ufs_ddren_req_mask_b;
+	uint8_t reg_ufs_infra_req_mask_b;
+	uint8_t reg_ufs_srcclkena_mask_b;
+	uint8_t reg_ufs_vrf18_req_mask_b;
+
+	/* SPM_EVENT_CON_MISC */
+	uint8_t reg_srcclken_fast_resp;
+	uint8_t reg_csyspwrup_ack_mask;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	uint32_t reg_ext_wakeup_event_mask;
+
+	/* Auto-gen End */
+};
+
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+
+	/* SPM_CLK_CON */
+	PW_REG_SPM_LOCK_INFRA_DCM_LSB,
+	PW_REG_MD1_C32RM_EN_LSB,
+	PW_REG_SPM_LEAVE_SUSPEND_MERGE_MASK_LSB,
+	PW_REG_SYSCLK0_SRC_MASK_B_LSB,
+	PW_REG_SYSCLK1_SRC_MASK_B_LSB,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_WFI_AF_SEL,
+	PW_REG_CPU_SLEEP_WFI,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_DDREN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_VCORE_REQ,
+	PW_REG_SPM_VRF18_REQ,
+
+	/* SPM_SRC_MASK_0 */
+	PW_REG_AFE_APSRC_REQ_MASK_B,
+	PW_REG_AFE_DDREN_REQ_MASK_B,
+	PW_REG_AFE_INFRA_REQ_MASK_B,
+	PW_REG_AFE_SRCCLKENA_MASK_B,
+	PW_REG_AFE_VRF18_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_DDREN_REQ_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDREN_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_CCIF_EVENT_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC_MASK_1 */
+	PW_REG_CCIF_EVENT_INFRA_REQ_MASK_B,
+	PW_REG_CCIF_EVENT_SRCCLKENA_MASK_B,
+
+	/* SPM_SRC_MASK_2 */
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDREN_REQ_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_VCORE_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_DDREN_REQ_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDREN_REQ_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDREN_REQ_MASK_B,
+	PW_REG_DPMAIF_APSRC_REQ_MASK_B,
+	PW_REG_DPMAIF_DDREN_REQ_MASK_B,
+	PW_REG_DPMAIF_INFRA_REQ_MASK_B,
+	PW_REG_DPMAIF_SRCCLKENA_MASK_B,
+	PW_REG_DPMAIF_VRF18_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_APSRC_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_DDREN_REQ_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GPUEB_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC_MASK_3 */
+	PW_REG_GPUEB_DDREN_REQ_MASK_B,
+	PW_REG_GPUEB_IDLE_MASK_B,
+	PW_REG_GPUEB_INFRA_REQ_MASK_B,
+	PW_REG_GPUEB_SRCCLKENA_MASK_B,
+	PW_REG_GPUEB_VRF18_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDREN_REQ_MASK_B,
+	PW_REG_MCUPM_APSRC_REQ_MASK_B,
+	PW_REG_MCUPM_DDREN_REQ_MASK_B,
+	PW_REG_MCUPM_IDLE_MASK_B,
+	PW_REG_MCUPM_INFRA_REQ_MASK_B,
+	PW_REG_MCUPM_SRCCLKENA_MASK_B,
+	PW_REG_MCUPM_VRF18_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDREN_REQ_MASK_B,
+	PW_REG_MD_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC_MASK_4 */
+	PW_REG_MD_DDREN_REQ_MASK_B,
+	PW_REG_MD_INFRA_REQ_MASK_B,
+	PW_REG_MD_SRCCLKENA_MASK_B,
+	PW_REG_MD_SRCCLKENA1_MASK_B,
+	PW_REG_MD_VRF18_REQ_MASK_B,
+	PW_REG_MMSYS_APSRC_REQ_MASK_B,
+	PW_REG_MMSYS_DDREN_REQ_MASK_B,
+	PW_REG_MMSYS_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_DDREN_REQ_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_DDREN_REQ_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC2_APSRC_REQ_MASK_B,
+	PW_REG_MSDC2_DDREN_REQ_MASK_B,
+	PW_REG_MSDC2_INFRA_REQ_MASK_B,
+	PW_REG_MSDC2_SRCCLKENA_MASK_B,
+	PW_REG_MSDC2_VRF18_REQ_MASK_B,
+	PW_REG_PCIE_APSRC_REQ_MASK_B,
+	PW_REG_PCIE_DDREN_REQ_MASK_B,
+	PW_REG_PCIE_INFRA_REQ_MASK_B,
+	PW_REG_PCIE_SRCCLKENA_MASK_B,
+	PW_REG_PCIE_VRF18_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_DDREN_REQ_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+
+	/* SPM_SRC_MASK_5 */
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_APSRC_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_DDREN_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_INFRA_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_SRCCLKENA_MASK_B,
+	PW_REG_SPM_RESERVED_VRF18_REQ_MASK_B,
+	PW_REG_SRCCLKENI_INFRA_REQ_MASK_B,
+	PW_REG_SRCCLKENI_SRCCLKENA_MASK_B,
+	PW_REG_SSPM_APSRC_REQ_MASK_B,
+	PW_REG_SSPM_DDREN_REQ_MASK_B,
+	PW_REG_SSPM_IDLE_MASK_B,
+	PW_REG_SSPM_INFRA_REQ_MASK_B,
+	PW_REG_SSPM_SRCCLKENA_MASK_B,
+	PW_REG_SSPM_VRF18_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_DDREN_REQ_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+
+	/* SPM_EVENT_CON_MISC */
+	PW_REG_SRCCLKEN_FAST_RESP,
+	PW_REG_CSYSPWRUP_ACK_MASK,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+	PW_MAX_COUNT,
+};
+
+
+
+#endif /* __PWR_CTRL_H__ */

drivers/misc/mediatek/lpm/modules/include/mt6877/mt6877_spm_comm.h

@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MT6877_SPM_COMM_H__
+#define __MT6877_SPM_COMM_H__
+
+struct mt6877_spm_wake_status {
+	u32 r12;			/* SPM_BK_WAKE_EVENT */
+	u32 r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	u32 raw_sta;		/* SPM_WAKEUP_STA */
+	u32 raw_ext_sta;	/* SPM_WAKEUP_EXT_STA */
+	u32 md32pcm_wakeup_sta;/* MD32CPM_WAKEUP_STA */
+	u32 md32pcm_event_sta;/* MD32PCM_EVENT_STA */
+	u32 wake_misc;		/* SPM_BK_WAKE_MISC */
+	u32 timer_out;		/* SPM_BK_PCM_TIMER */
+	u32 r13;			/* PCM_REG13_DATA */
+	u32 idle_sta;		/* SUBSYS_IDLE_STA */
+	u32 req_sta0;		/* SRC_REQ_STA_0 */
+	u32 req_sta1;		/* SRC_REQ_STA_1 */
+	u32 req_sta2;		/* SRC_REQ_STA_2 */
+	u32 req_sta3;		/* SRC_REQ_STA_3 */
+	u32 req_sta4;		/* SRC_REQ_STA_4 */
+	u32 req_sta5;		/* SRC_REQ_STA_5 */
+	u32 cg_check_sta;	/* SPM_CG_CHECK_STA */
+	u32 debug_flag;		/* PCM_WDT_LATCH_SPARE_0 */
+	u32 debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	u32 b_sw_flag0;		/* SPM_SW_RSV_7 */
+	u32 b_sw_flag1;		/* SPM_SW_RSV_8 */
+	u32 isr;			/* SPM_IRQ_STA */
+	u32 sw_flag0;		/* SPM_SW_FLAG_0 */
+	u32 sw_flag1;		/* SPM_SW_FLAG_1 */
+	u32 clk_settle;		/* SPM_CLK_SETTLE */
+	u32 src_req;	/* SPM_SRC_REQ */
+	u32 log_index;
+	u32 is_abort;
+	u32 rt_req_sta0; /* SPM_SW_RSV_2 */
+	u32 rt_req_sta1; /* SPM_SW_RSV_3 */
+	u32 rt_req_sta2; /* SPM_SW_RSV_4 */
+	u32 rt_req_sta3; /* SPM_SW_RSV_5 */
+	u32 rt_req_sta4; /* SPM_SW_RSV_6 */
+	u32 mcupm_req_sta;
+};
+
+struct spm_wakesrc_irq_list {
+	unsigned int wakesrc;
+	const char *name;
+	int order;
+	unsigned int irq_no;
+};
+
+
+enum MTK_LPM_SUSPEND_TYPE {
+	MTK_LPM_SUSPEND_SYSTEM,
+	MTK_LPM_SUSPEND_S2IDLE,
+};
+
+/* MD sleep status */
+
+struct md_sleep_status {
+	u64 sleep_wall_clk;
+	u64 sleep_cnt;
+	u64 sleep_cnt_reserve;
+	u64 sleep_time; // 32k
+	u64 sleep_time_reserve;
+	u64 md_sleep_time; // uS
+	u64 gsm_sleep_time; // uS
+	u64 wcdma_sleep_time; //uS
+	u64 lte_sleep_time; // uS
+	u64 nr_sleep_time; // uS
+};
+
+
+#define MTK_LP_PREPARE_FAIL		(1<<4L)
+
+/* Determine for operand bit */
+
+#define MTK_DUMP_LP_GOLDEN	(1 << 0L)
+#define MTK_DUMP_GPIO		(1 << 1L)
+#define PCM_32K_TICKS_PER_SEC	(32768)
+#define PCM_TICK_TO_SEC(TICK)	(TICK / PCM_32K_TICKS_PER_SEC)
+extern void mtk_suspend_gpio_dbg(void);
+extern void mtk_suspend_clk_dbg(void);
+extern u32 mt_irq_get_pending(unsigned int irq);
+extern u64 spm_26M_off_count;
+extern u64 spm_26M_off_duration;
+extern u64 ap_pd_count;
+extern u64 ap_slp_duration;
+int mtk_lpm_suspend_type_get(void);
+
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ * From Legacy sleep_def.h
+ */
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN		(1 << 0u)
+#define SPM_FLAG_DISABLE_INFRA_PDN		(1 << 1u)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN		(1 << 2u)
+#define SPM_FLAG_DISABLE_VCORE_DVS		(1 << 3u)
+#define SPM_FLAG_DISABLE_VCORE_DFS		(1 << 4u)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO	(1 << 5u)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF		(1 << 6u)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF		(1 << 7u)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH		(1 << 8u)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND		(1 << 9u)
+#define SPM_FLAG_RUN_COMMON_SCENARIO		(1 << 10u)
+#define SPM_FLAG_SSPM_INFRA_SLEEP_MODE		(1 << 11u)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP	(1 << 12u)
+#define SPM_FLAG_USE_SRCCLKENO2			(1 << 13u)
+#define SPM_FLAG_ENABLE_6315_CTRL		(1 << 14u)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND		(1 << 15u)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP		(1 << 16u)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP	(1 << 17u)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP	(1 << 18u)
+#define SPM_FLAG_ENABLE_MD_MUMTAS			(1 << 19u)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN			(1 << 20u)
+#define SPM_FLAG_ENABLE_6362_CTRL			(1 << 21u)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP	(1 << 22u)
+#define SPM_FLAG_DISABLE_SRAM_EVENT			(1 << 23u)
+#define SPM_FLAG_DISABLE_6360_SRCLKENO2_CTRL			(1 << 24u)
+#define SPM_FLAG_DISABLE_6360_VDDQ_CTRL			(1 << 25u)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_OFF			(1 << 26u)
+#define SPM_FLAG_VTCXO_STATE			(1 << 27u)
+#define SPM_FLAG_INFRA_STATE			(1 << 28u)
+#define SPM_FLAG_APSRC_STATE			(1 << 29u)
+#define SPM_FLAG_VRF18_STATE			(1 << 30u)
+#define SPM_FLAG_DDREN_STATE			(1 << 31u)
+#define SPM_FLAG_SYSTEM_POWER_STATE		(1 << 28u)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M      (1 << 0u)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF          (1 << 1u)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH    (1 << 2u)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF          (1 << 3u)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON            (1 << 4u)
+#define SPM_FLAG1_RESERVED_BIT5               (1 << 5u)
+#define SPM_FLAG1_ENABLE_REKICK               (1 << 6u)
+#define SPM_FLAG1_RESERVED_BIT7               (1 << 7u)
+#define SPM_FLAG1_RESERVED_BIT8               (1 << 8u)
+#define SPM_FLAG1_RESERVED_BIT9               (1 << 9u)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW         (1 << 10u)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH      (1 << 11u)
+#define SPM_FLAG1_RESERVED_BIT12              (1 << 12u)
+#define SPM_FLAG1_RESERVED_BIT13              (1 << 13u)
+#define SPM_FLAG1_RESERVED_BIT14              (1 << 14u)
+#define SPM_FLAG1_RESERVED_BIT15              (1 << 15u)
+#define SPM_FLAG1_RESERVED_BIT16              (1 << 16u)
+#define SPM_FLAG1_RESERVED_BIT17              (1 << 17u)
+#define SPM_FLAG1_RESERVED_BIT18              (1 << 18u)
+#define SPM_FLAG1_RESERVED_BIT19              (1 << 19u)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP   (1 << 20u)
+#define SPM_FLAG1_RESERVED_BIT21              (1 << 21u)
+#define SPM_FLAG1_RESERVED_BIT22			(1 << 22u)
+#define SPM_FLAG1_RESERVED_BIT23			(1 << 23u)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL   (1 << 24u)
+#define SPM_FLAG1_RESERVED_BIT25              (1 << 25u)
+#define SPM_FLAG1_RESERVED_BIT26              (1 << 26u)
+#define SPM_FLAG1_RESERVED_BIT27              (1 << 27u)
+#define SPM_FLAG1_RESERVED_BIT28              (1 << 28u)
+#define SPM_FLAG1_RESERVED_BIT29              (1 << 29u)
+#define SPM_FLAG1_RESERVED_BIT30              (1 << 30u)
+#define SPM_FLAG1_ENABLE_MCUPM_OFF              (1 << 31u)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE			(1 << 0u)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP			(1 << 1u)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE			(1 << 2u)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP			(1 << 3u)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE			(1 << 4u)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP			(1 << 5u)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE			(1 << 6u)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP			(1 << 7u)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE			(1 << 8u)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP			(1 << 9u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC	(1 << 10u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE		(1 << 11u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE		(1 << 12u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN	(1 << 13u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE		(1 << 14u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP			(1 << 15u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON			(1 << 16u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP		(1 << 17u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON			(1 << 18u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP			(1 << 19u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON			(1 << 20u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP		(1 << 21u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON		(1 << 22u)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP_ABORT		(1 << 23u)
+#define SPM_DBG_DEBUG_IDX_6360_VMDDR_LP_MODE		(1 << 24u)
+#define SPM_DBG_DEBUG_IDX_6360_VDDQ_LP_MODE	(1 << 25u)
+#define SPM_DBG_DEBUG_IDX_I2C5_NO_CLK		(1 << 26u)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW		(1 << 27u)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE			(1 << 28u)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE			(1 << 29u)
+#define SPM_DBG_DEBUG_IDX_VRF18_STATE			(1 << 30u)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE			(1 << 31u)
+
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP		(1 << 0u)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START		(1 << 1u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF			(1 << 2u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON			(1 << 3u)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DFS	(1 << 4u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF		(1 << 5u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON		(1 << 6u)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT		(1 << 7u)
+#define SPM_DBG1_NOISE_IRQ				(1 << 8u)
+#define SPM_DBG1_IDX_6360_SRCLKEN2_LOW		(1 << 9u)
+#define SPM_DBG1_IDX_6360_SRCLKEN2_HIGH		(1 << 10u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC		(1 << 11u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M		(1 << 12u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K		(1 << 13u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M		(1 << 14u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF			(1 << 15u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON			(1 << 16u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW			(1 << 17u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH		(1 << 18u)
+#define SPM_DBG1_DEBUG_IDX_MCUPM_WAKE_IRQ		(1 << 19u)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	(1 << 20u)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW			(1 << 21u)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH                    (1 << 22u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT    (1 << 23u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT   (1 << 24u)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT           (1 << 25u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT        (1 << 26u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT       (1 << 27u)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT       (1 << 28u)
+#define SPM_DBG1_DEBUG_IDX_SPM_TIMER_RST_DVFS			(1 << 29u)
+#define SPM_DBG1_DEBUG_IDX_SPM_DISABLE_DDREN_EVENT		(1 << 30u)
+#define MCUPM_RESTORE							(1 << 31u)
+
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC \
+	| SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6877/mtk_lp_plat_apmcu.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef __MTK_LP_PLAT_APMCU_H__
+#define __MTK_LP_PLAT_APMCU_H__
+
+#include <linux/types.h>
+
+#define nr_cluster_ids                  (1)
+#define get_physical_cluster_id(cpu)    (0)
+
+#define LP_PM_SYSRAM_INFO_OFS  0x8
+#define LP_PM_SYSRAM_SIZE      0x500
+
+extern void __iomem *cpu_pm_syssram_base;
+/* 0x11B000 */
+#define MT_CPU_PM_KERNEL_SRAMBASE	(cpu_pm_syssram_base + 0x100)
+#define MT_CPU_PM_KERNEL_SRAM(slot)	(MT_CPU_PM_KERNEL_SRAMBASE + (slot<<2))
+
+
+#define cpu_pm_sync_writel(v, a)				\
+do {								\
+	__raw_writel((v), (void __force __iomem *)((a)));	\
+	mb(); /*make sure register access in order */		\
+} while (0)
+
+#define MT_CPU_PM_KERNEL_SRAM_WR(slot, val) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			cpu_pm_sync_writel(val,\
+				MT_CPU_PM_KERNEL_SRAM(slot)); uval; })
+
+
+#define MT_CPU_PM_KERNEL_SRAM_RD(slot) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			uval = __raw_readl(MT_CPU_PM_KERNEL_SRAM(slot));\
+		uval; })
+
+void mtk_lp_plat_set_mcusys_off(int cpu);
+void mtk_lp_plat_clr_mcusys_off(int cpu);
+
+void mtk_lp_plat_set_cluster_off(int cpu);
+void mtk_lp_plat_clr_cluster_off(int cpu);
+
+bool mtk_lp_plat_is_mcusys_off(void);
+bool mtk_lp_plat_is_cluster_off(int cpu);
+
+int mtk_lp_plat_apmcu_init(void);
+int mtk_lp_plat_apmcu_early_init(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6877/mtk_lp_plat_apmcu_mbox.h

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_LP_PLAT_APMCU_MBOX_H__
+#define __MTK_LP_PLAT_APMCU_MBOX_H__
+
+enum {
+	MBOX_SSPM,
+	MBOX_MCUPM,
+
+	NF_MBOX,
+};
+
+/* SSPM Mbox */
+#define APMCU_SSPM_MBOX_ID           3
+#define APMCU_SSPM_MBOX_SPM_CMD_SIZE 8
+
+#define APMCU_SSPM_MBOX_SPM_CMD      0
+#define APMCU_SSPM_MBOX_SPM_ARGS1    1
+#define APMCU_SSPM_MBOX_SPM_ARGS2    2
+#define APMCU_SSPM_MBOX_SPM_ARGS3    3
+#define APMCU_SSPM_MBOX_SPM_ARGS4    4
+#define APMCU_SSPM_MBOX_SPM_ARGS5    5
+#define APMCU_SSPM_MBOX_SPM_ARGS6    6
+#define APMCU_SSPM_MBOX_SPM_ARGS7    7
+#define APMCU_SSPM_MBOX_AP_READY     17
+
+void mtk_set_sspm_lp_cmd(void *buf);
+void mtk_clr_sspm_lp_cmd(void);
+
+
+/* MCUPM Mbox */
+
+#define APMCU_MCUPM_MBOX_ID             3
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY       0
+#define APMCU_MCUPM_MBOX_RESERVED_1     1
+#define APMCU_MCUPM_MBOX_RESERVED_2     2
+#define APMCU_MCUPM_MBOX_RESERVED_3     3
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN    4
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE  5
+#define APMCU_MCUPM_MBOX_BUCK_MODE      6
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE    7
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA       8
+#define APMCU_MCUPM_MBOX_RESERVED_9     9
+#define APMCU_MCUPM_MBOX_RESERVED_10    10
+#define APMCU_MCUPM_MBOX_RESERVED_11    11
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU     12
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN (4) */
+#define MCUPM_MCUSYS_CTRL               (1 << 0)
+#define MCUPM_BUCK_CTRL                 (1 << 1)
+#define MCUPM_ARMPLL_CTRL               (1 << 2)
+#define MCUPM_CM_CTRL                   (1 << 3)
+#define MCUPM_PWR_CTRL_MASK             ((1 << 4) - 1)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_L3_CACHE_MODE (5) */
+#define MCUPM_L3_OFF_MODE               0 /* default */
+#define MCUPM_L3_DORMANT_MODE           1
+#define NF_MCUPM_L3_MODE                2U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE (6) */
+#define MCUPM_BUCK_NORMAL_MODE          0 /* default */
+#define MCUPM_BUCK_LP_MODE              1
+#define MCUPM_BUCK_OFF_MODE             2
+#define NF_MCUPM_BUCK_MODE              3U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE (7) */
+#define MCUPM_ARMPLL_ON                 0 /* default */
+#define MCUPM_ARMPLL_GATING             1
+#define MCUPM_ARMPLL_OFF                2
+#define NF_MCUPM_ARMPLL_MODE            3U
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA (9) */
+#define MCUPM_TASK_UNINIT               0
+#define MCUPM_TASK_INIT                 1
+#define MCUPM_TASK_INIT_FINISH          2
+#define MCUPM_TASK_WAIT                 3
+#define MCUPM_TASK_RUN                  4
+#define MCUPM_TASK_PAUSE                5
+
+bool mtk_mcupm_cm_is_notified(void);
+
+void mtk_set_mcupm_pll_mode(unsigned int mode);
+int mtk_get_mcupm_pll_mode(void);
+
+void mtk_set_mcupm_buck_mode(unsigned int mode);
+int mtk_get_mcupm_buck_mode(void);
+
+void mtk_set_preferred_cpu_wakeup(int cpu);
+int mtk_get_preferred_cpu_wakeup(void);
+
+bool mtk_mcupm_is_ready(void);
+
+void mtk_wait_mbox_init_done(void);
+void mtk_notify_subsys_ap_ready(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6877/mtk_lp_plat_reg.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_PLAT_CPC_REG_H__
+#define __MTK_PLAT_CPC_REG_H__
+
+/**************************************
+ * CPC related register
+ * base address = 0x0C53A000
+ **************************************/
+#define CPC_FLOW_CTRL_CFG              (0x814)
+#define CPC_MCUSYS_LAST_CORE_REQ       (0x818)
+#define CPC_CPUSYS_LAST_CORE_RESP      (0x81C)
+#define CPC_MCUSYS_LAST_CORE_RESP      (0x824)
+#define CPC_PWR_ON_MASK                (0x828)
+#define CPC_SPMC_PWR_STATUS            (0x840)
+#define CPC_CPUSYS_CPU_ON_SW_HINT_CLR  (0x8AC)
+
+#define SPMC_DBG_SETTING               (0xB00)
+
+#define CPC_TRACE_DATA_SEL             (0xB14)
+
+#define CPC_CPU0_LATENCY               (0xB40)
+#define CPC_CPU1_LATENCY               (0xB44)
+#define CPC_CPU2_LATENCY               (0xB48)
+#define CPC_CPU3_LATENCY               (0xB4C)
+#define CPC_CPU4_LATENCY               (0xB50)
+#define CPC_CPU5_LATENCY               (0xB54)
+#define CPC_CPU6_LATENCY               (0xB58)
+#define CPC_CPU7_LATENCY               (0xB5C)
+#define CPC_CLUSTER_OFF_LATENCY        (0xB60)
+#define CPC_CLUSTER_ON_LATENCY         (0xB64)
+#define CPC_MCUSYS_LATENCY             (0xB68)
+#define CPC_DORMANT_COUNTER            (0xB70)
+#define CPC_DORMANT_COUNTER_CLR        (0xB74)
+#define CPC_CPU_LATENCY(cpu)           ((CPC_CPU0_LATENCY) + 4 * (cpu))
+
+/**************************************
+ * system sram for apmcu debug
+ * base address = 0x0011B000
+ **************************************/
+#define SYSRAM_CPUSYS_CNT              (0x1E8)
+#define SYSRAM_MCUSYS_CNT              (0x1EC)
+#define SYSRAM_CPC_CPUSYS_CNT_BACKUP   (0x1F0)
+#define SYSRAM_MCUPM_MCUSYS_COUNTER    (0x1F4)
+#define SYSRAM_CPU_ONLINE              (0x1F8)
+
+/* Run time information. The registers may be cleared in db dump flow */
+#define SYSRAM_RECENT_CPU_CNT(i)       (4 * (i) + 0x1B0)
+#define SYSRAM_RECENT_CPUSYS_CNT       (0x1D0)
+#define SYSRAM_RECENT_MCUSYS_CNT       (0x1D4)
+#define SYSRAM_RECENT_CNT_TS_L         (0x1D8)
+#define SYSRAM_RECENT_CNT_TS_H         (0x1DC)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6877/mtk_power_gs_array.h

@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+#ifndef MTK_POWER_GS_ARRAY_H
+#define MTK_POWER_GS_ARRAY_H
+
+extern void mt_power_gs_sp_dump(void);
+extern unsigned int golden_read_reg(unsigned int addr);
+
+/* PMIC 6365 */
+extern const unsigned int *AP_PMIC_REG_6365_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_6365_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_6365_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_6365_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_6365_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_6365_gs_suspend_32kless_len;
+
+/* PMIC 6315_1 */
+extern const unsigned int *AP_PMIC_REG_MT6315_1_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_1_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_1_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_1_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_1_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_1_gs_suspend_32kless_len;
+
+/* PMIC 6315_2 */
+extern const unsigned int *AP_PMIC_REG_MT6315_2_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_2_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_2_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_2_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_2_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_2_gs_suspend_32kless_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_dpidle;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_dpidle_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_suspend;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_suspend_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_sodi;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_sodi_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_dpidle;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_dpidle_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_suspend;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_suspend_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_sodi;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_sodi_len;
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6885/mt6885_cond.h

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MT6885_COND_H__
+#define __MT6885_COND_H__
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]    : idle condition check fail
+ */
+
+#define SPM_COND_BLOCKED_CG_IDX		(0)
+#define SPM_COND_BLOCKED_PLL_IDX	(16)
+#define SPM_COND_BLOCKED_PLL		(1<<30L)
+#define SPM_COND_CHECK_FAIL		(1<<31L)
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS_0 = 0,
+	PLAT_SPM_COND_CG_INFRA_0,
+	PLAT_SPM_COND_CG_INFRA_1,
+	PLAT_SPM_COND_CG_INFRA_2,
+	PLAT_SPM_COND_CG_INFRA_3,
+	PLAT_SPM_COND_CG_MMSYS_0,
+	PLAT_SPM_COND_CG_MMSYS_1,
+	PLAT_SPM_COND_CG_MMSYS_2,
+	PLAT_SPM_COND_MAX,
+};
+
+enum PLAT_SPM_PLL_COND {
+	PLAT_SPM_COND_UNIVPLL = 0,
+	PLAT_SPM_COND_MFGPLL,
+	PLAT_SPM_COND_MSDCPLL,
+	PLAT_SPM_COND_TVPLL,
+	PLAT_SPM_COND_MMPLL,
+	PLAT_SPM_COND_PLL_MAX,
+};
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6885/mt6885_pcm_def.h

@@ -0,0 +1,220 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __pcm_def_h__
+#define __pcm_def_h__
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF                      (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN               (1U << 1)
+#define R0_SC_MEM_CK_OFF                      (1U << 2)
+#define R0_SC_AXI_CK_OFF                      (1U << 3)
+#define R0_SC_DR_SRAM_LOAD                    (1U << 4)
+#define R0_SC_MD26M_CK_OFF                    (1U << 5)
+#define R0_SC_DPY_MODE_SW                     (1U << 6)
+#define R0_SC_DMSUS_OFF                       (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN                  (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE                 (1U << 9)
+#define R0_SC_MPLLOUT_OFF                     (1U << 10)
+#define R0_SC_TX_TRACKING_DIS                 (1U << 11)
+#define R0_SC_DPY_DLL_EN                      (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN                   (1U << 13)
+#define R0_SC_DPY_VREF_EN                     (1U << 14)
+#define R0_SC_PHYPLL_EN                       (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN                 (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE                 (1U << 17)
+#define R0_SC_MPLL_OFF                        (1U << 18)
+#define R0_SC_SHU_RESTORE                     (1U << 19)
+#define R0_SC_CKSQ0_OFF                       (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH         (1U << 21)
+#define R0_SC_DR_SHU_EN                       (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP                  (1U << 23)
+#define R0_SC_MPLL_S_OFF                      (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN             (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN                   (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN                  (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW                  (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW                 (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0                   (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1                   (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ                    (1U << 0)
+#define R7_EMI_CLK_OFF_REQ                    (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ                (1U << 2)
+#define R7_SPM_CK_UPDATE                      (1U << 3)
+#define R7_SPM_CK_SEL0                        (1U << 4)
+#define R7_SPM_CK_SEL1                        (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ             (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL                  (1U << 7)
+#define R7_SC_26M_CK_SEL                      (1U << 8)
+#define R7_PCM_TIMER_SET                      (1U << 9)
+#define R7_PCM_TIMER_CLR                      (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ              (1U << 11)
+#define R7_CSYSPWRUPACK                       (1U << 12)
+#define R7_PCM_IM_SLP_EN                      (1U << 13)
+#define R7_SRCCLKENO0                         (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE                  (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK             (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL              (1U << 17)
+#define R7_SC_AXI_DCM_DIS                     (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM                   (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN                  (1U << 20)
+#define R7_SRCCLKENO1                         (1U << 21)
+#define R7_PCM_WDT_KICK_P                     (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC              (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM                 (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM           (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN                    (1U << 26)
+#define R7_FORCE_F26M_WAKE                    (1U << 27)
+#define R7_FORCE_APSRC_WAKE                   (1U << 28)
+#define R7_FORCE_INFRA_WAKE                   (1U << 29)
+#define R7_FORCE_VRF18_WAKE                   (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK            (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER                         (1U << 0)
+#define R12_TWAM_IRQ_B                        (1U << 1)
+#define R12_KP_IRQ_B                          (1U << 2)
+#define R12_APWDT_EVENT_B                     (1U << 3)
+#define R12_APXGPT1_EVENT_B                   (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B              (1U << 5)
+#define R12_EINT_EVENT_B                      (1U << 6)
+#define R12_CONN_WDT_IRQ_B                    (1U << 7)
+#define R12_CCIF0_EVENT_B                     (1U << 8)
+#define R12_LOWBATTERY_IRQ_B                  (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B                 (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B                  (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B                 (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B                  (1U << 13)
+#define R12_USBX_CDSC_B                       (1U << 14)
+#define R12_USBX_POWERDWN_B                   (1U << 15)
+#define R12_SYS_TIMER_EVENT_B                 (1U << 16)
+#define R12_EINT_EVENT_SECURE_B               (1U << 17)
+#define R12_CCIF1_EVENT_B                     (1U << 18)
+#define R12_UART0_IRQ_B                       (1U << 19)
+#define R12_AFE_IRQ_MCU_B                     (1U << 20)
+#define R12_THERM_CTRL_EVENT_B                (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B                    (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B                (1U << 23)
+#define R12_CSYSPWREQ_B                       (1U << 24)
+#define R12_MD1_WDT_B                         (1U << 25)
+#define R12_CLDMA_EVENT_B                     (1U << 26)
+#define R12_SEJ_EVENT_B                       (1U << 27)
+#define R12_REG_CPU_WAKEUP                    (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B                (1U << 29)
+#define R12_NOT_USED1                         (1U << 30)
+#define R12_NOT_USED2                         (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE                       (1U << 0)
+#define R12EXT_26M_SLEEP                      (1U << 1)
+#define R12EXT_INFRA_WAKE                     (1U << 2)
+#define R12EXT_INFRA_SLEEP                    (1U << 3)
+#define R12EXT_APSRC_WAKE                     (1U << 4)
+#define R12EXT_APSRC_SLEEP                    (1U << 5)
+#define R12EXT_VRF18_WAKE                     (1U << 6)
+#define R12EXT_VRF18_SLEEP                    (1U << 7)
+#define R12EXT_DVFS_WAKE                      (1U << 8)
+#define R12EXT_DDREN_WAKE                     (1U << 9)
+#define R12EXT_DDREN_SLEEP                    (1U << 10)
+#define R12EXT_MCU_PM_WFI                     (1U << 11)
+#define R12EXT_SSPM_IDLE                      (1U << 12)
+#define R12EXT_CONN_SRCCLKENB                 (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE           (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE                (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE              (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE              (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE               (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK          (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK         (1U << 20)
+#define R12EXT_VS1_TRIGGER                    (1U << 21)
+#define R12EXT_VS2_TRIGGER                    (1U << 22)
+#define R12EXT_COROSS_REQ_APU                 (1U << 23)
+#define R12EXT_CROSS_REQ_L3                   (1U << 24)
+#define R12EXT_DDR_PST_ACK                    (1U << 25)
+#define R12EXT_BIT26                          (1U << 26)
+#define R12EXT_BIT27                          (1U << 27)
+#define R12EXT_BIT28                          (1U << 28)
+#define R12EXT_BIT29                          (1U << 29)
+#define R12EXT_BIT30                          (1U << 30)
+#define R12EXT_BIT31                          (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0                        (1U << 0)
+#define R13_SRCCLKENI1                        (1U << 1)
+#define R13_MD_SRCCLKENA_0                    (1U << 2)
+#define R13_MD_APSRC_REQ_0                    (1U << 3)
+#define R13_CONN_DDR_EN                       (1U << 4)
+#define R13_MD_SRCCLKENA_1                    (1U << 5)
+#define R13_SSPM_SRCCLKENA                    (1U << 6)
+#define R13_SSPM_APSRC_REQ                    (1U << 7)
+#define R13_MD1_STATE                         (1U << 8)
+#define R13_BIT9                              (1U << 9)
+#define R13_MM_STATE                          (1U << 10)
+#define R13_SSPM_STATE                        (1U << 11)
+#define R13_MD_DDR_EN_0                       (1U << 12)
+#define R13_CONN_STATE                        (1U << 13)
+#define R13_CONN_SRCCLKENA                    (1U << 14)
+#define R13_CONN_APSRC_REQ                    (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL                (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL          (1U << 17)
+#define R13_SCP_STATE                         (1U << 18)
+#define R13_CSYSPWRUPREQ                      (1U << 19)
+#define R13_PWRAP_SLEEP_ACK                   (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL            (1U << 21)
+#define R13_AUDIO_DSP_STATE                   (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL             (1U << 23)
+#define R13_CONN_SRCCLKENB                    (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL           (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0              (1U << 26)
+#define R13_DVFS_STATE                        (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL       (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL        (1U << 29)
+#define R13_MD_VRF18_REQ_0                    (1U << 30)
+#define R13_DDR_EN_STATE                      (1U << 31)
+
+
+enum SPM_WAKE_SRC_LIST {
+	WAKE_SRC_STA1_PCM_TIMER = (1U << 0),
+	WAKE_SRC_STA1_RESERVED_DEBUG_B = (1U << 1),
+	WAKE_SRC_STA1_KP_IRQ_B = (1U << 2),
+	WAKE_SRC_STA1_APWDT_EVENT_B = (1U << 3),
+	WAKE_SRC_STA1_APXGPT1_EVENT_B = (1U << 4),
+	WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B = (1U << 5),
+	WAKE_SRC_STA1_EINT_EVENT_B = (1U << 6),
+	WAKE_SRC_STA1_CONN_WDT_IRQ_B = (1U << 7),
+	WAKE_SRC_STA1_CCIF0_EVENT_B = (1U << 8),
+	WAKE_SRC_STA1_LOWBATTERY_IRQ_B = (1U << 9),
+	WAKE_SRC_STA1_SC_SSPM2SPM_WAKEUP_B = (1U << 10),
+	WAKE_SRC_STA1_SC_SCP2SPM_WAKEUP_B = (1U << 11),
+	WAKE_SRC_STA1_SC_ADSP2SPM_WAKEUP_B = (1U << 12),
+	WAKE_SRC_STA1_PCM_WDT_WAKEUP_B = (1U << 13),
+	WAKE_SRC_STA1_USB_CDSC_B = (1U << 14),
+	WAKE_SRC_STA1_USB_POWERDWN_B = (1U << 15),
+	WAKE_SRC_STA1_SYS_TIMER_EVENT_B = (1U << 16),
+	WAKE_SRC_STA1_EINT_EVENT_SECURE_B = (1U << 17),
+	WAKE_SRC_STA1_CCIF1_EVENT_B = (1U << 18),
+	WAKE_SRC_STA1_UART0_IRQ_B = (1U << 19),
+	WAKE_SRC_STA1_AFE_IRQ_MCU_B = (1U << 20),
+	WAKE_SRC_STA1_THERM_CTRL_EVENT_B = (1U << 21),
+	WAKE_SRC_STA1_SYS_CIRQ_IRQ_B = (1U << 22),
+	WAKE_SRC_STA1_MD2AP_PEER_EVENT_B = (1U << 23),
+	WAKE_SRC_STA1_CSYSPWREQ_B = (1U << 24),
+	WAKE_SRC_STA1_MD1_WDT_B = (1U << 25),
+	WAKE_SRC_STA1_AP2AP_PEER_WAKEUPEVENT_B = (1U << 26),
+	WAKE_SRC_STA1_SEJ_EVENT_B = (1U << 27),
+	WAKE_SRC_STA1_SPM_CPU_WAKEUPEVENT_B = (1U << 28),
+	WAKE_SRC_STA1_APUSYS = (1U << 29),
+	WAKE_SRC_R12_NOT_USED1 = (1U << 30),
+	WAKE_SRC_R12_NOT_USED2 = (1U << 31),
+};
+
+extern const char *wakesrc_str[32];
+
+/* define WAKE_SRC_CONN2AP for conn use */
+#define WAKE_SRC_CONN2AP WAKE_SRC_STA1_CONN2AP_SPM_WAKEUP_B
+
+#endif /* __pcm_def_h__ */

drivers/misc/mediatek/lpm/modules/include/mt6885/mt6885_pwr_ctrl.h

@@ -0,0 +1,394 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __PWR_CTRL_H__
+#define __PWR_CTRL_H__
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP              0x3FF  /* bit0 ~ bit9 */
+#define WAKE_MISC_DVFSRC_IRQ	         (1U << 16)
+#define WAKE_MISC_REG_CPU_WAKEUP         (1U << 17)
+#define WAKE_MISC_PCM_TIMER_EVENT        (1U << 18)
+#define WAKE_MISC_PMIC_OUT_B		     ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B             (1U << 21)
+#define WAKE_MISC_PMSR_IRQ_B_SET0        (1U << 22)
+#define WAKE_MISC_PMSR_IRQ_B_SET1        (1U << 23)
+#define WAKE_MISC_PMSR_IRQ_B_SET2        (1U << 24)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0   (1U << 25)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1	 (1U << 26)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2	 (1U << 27)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3	 (1U << 28)
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL (1U << 29)
+#define WAKE_MISC_PMIC_IRQ_ACK			 (1U << 30)
+#define WAKE_MISC_PMIC_SCP_IRQ			 (1U << 31)
+
+struct pwr_ctrl {
+
+	/* for SPM */
+	uint32_t pcm_flags;
+	uint32_t pcm_flags_cust;
+	uint32_t pcm_flags_cust_set;
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	uint32_t pcm_flags1_cust;
+	uint32_t pcm_flags1_cust_set;
+	uint32_t pcm_flags1_cust_clr;
+	uint32_t timer_val;
+	uint32_t timer_val_cust;
+	uint32_t timer_val_ramp_en;
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	uint32_t wake_src_cust;
+	uint32_t wakelock_timer_val;
+	uint8_t wdt_disable;
+	/* Auto-gen Start */
+
+	/* SPM_CLK_CON */
+	uint8_t reg_srcclken0_ctl;
+	uint8_t reg_srcclken1_ctl;
+	uint8_t reg_spm_lock_infra_dcm;
+	uint8_t reg_srcclken_mask;
+	uint8_t reg_md1_c32rm_en;
+	uint8_t reg_md2_c32rm_en;
+	uint8_t reg_clksq0_sel_ctrl;
+	uint8_t reg_clksq1_sel_ctrl;
+	uint8_t reg_srcclken0_en;
+	uint8_t reg_srcclken1_en;
+	uint32_t reg_sysclk0_src_mask_b;
+	uint32_t reg_sysclk1_src_mask_b;
+
+	/* SPM_AP_STANDBY_CON */
+	uint8_t reg_wfi_op;
+	uint8_t reg_wfi_type;
+	uint8_t reg_mp0_cputop_idle_mask;
+	uint8_t reg_mp1_cputop_idle_mask;
+	uint8_t reg_mcusys_idle_mask;
+	uint8_t reg_md_apsrc_1_sel;
+	uint8_t reg_md_apsrc_0_sel;
+	uint8_t reg_conn_apsrc_sel;
+
+	/* SPM_SRC_REQ */
+	uint8_t reg_spm_apsrc_req;
+	uint8_t reg_spm_f26m_req;
+	uint8_t reg_spm_infra_req;
+	uint8_t reg_spm_vrf18_req;
+	uint8_t reg_spm_ddr_en_req;
+	uint8_t reg_spm_dvfs_req;
+	uint8_t reg_spm_sw_mailbox_req;
+	uint8_t reg_spm_sspm_mailbox_req;
+	uint8_t reg_spm_adsp_mailbox_req;
+	uint8_t reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	uint8_t reg_md_srcclkena_0_mask_b;
+	uint8_t reg_md_srcclkena2infra_req_0_mask_b;
+	uint8_t reg_md_apsrc2infra_req_0_mask_b;
+	uint8_t reg_md_apsrc_req_0_mask_b;
+	uint8_t reg_md_vrf18_req_0_mask_b;
+	uint8_t reg_md_ddr_en_0_mask_b;
+	uint8_t reg_md_srcclkena_1_mask_b;
+	uint8_t reg_md_srcclkena2infra_req_1_mask_b;
+	uint8_t reg_md_apsrc2infra_req_1_mask_b;
+	uint8_t reg_md_apsrc_req_1_mask_b;
+	uint8_t reg_md_vrf18_req_1_mask_b;
+	uint8_t reg_md_ddr_en_1_mask_b;
+	uint8_t reg_conn_srcclkena_mask_b;
+	uint8_t reg_conn_srcclkenb_mask_b;
+	uint8_t reg_conn_infra_req_mask_b;
+	uint8_t reg_conn_apsrc_req_mask_b;
+	uint8_t reg_conn_vrf18_req_mask_b;
+	uint8_t reg_conn_ddr_en_mask_b;
+	uint8_t reg_conn_vfe28_mask_b;
+	uint8_t reg_srcclkeni0_srcclkena_mask_b;
+	uint8_t reg_srcclkeni0_infra_req_mask_b;
+	uint8_t reg_srcclkeni1_srcclkena_mask_b;
+	uint8_t reg_srcclkeni1_infra_req_mask_b;
+	uint8_t reg_srcclkeni2_srcclkena_mask_b;
+	uint8_t reg_srcclkeni2_infra_req_mask_b;
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	uint8_t reg_infrasys_ddr_en_mask_b;
+	uint8_t reg_md32_srcclkena_mask_b;
+	uint8_t reg_md32_infra_req_mask_b;
+	uint8_t reg_md32_apsrc_req_mask_b;
+	uint8_t reg_md32_vrf18_req_mask_b;
+	uint8_t reg_md32_ddr_en_mask_b;
+
+	/* SPM_SRC2_MASK */
+	uint8_t reg_scp_srcclkena_mask_b;
+	uint8_t reg_scp_infra_req_mask_b;
+	uint8_t reg_scp_apsrc_req_mask_b;
+	uint8_t reg_scp_vrf18_req_mask_b;
+	uint8_t reg_scp_ddr_en_mask_b;
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	uint8_t reg_audio_dsp_ddr_en_mask_b;
+	uint8_t reg_ufs_srcclkena_mask_b;
+	uint8_t reg_ufs_infra_req_mask_b;
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	uint8_t reg_ufs_vrf18_req_mask_b;
+	uint8_t reg_ufs_ddr_en_mask_b;
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	uint8_t reg_disp0_ddr_en_mask_b;
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	uint8_t reg_disp1_ddr_en_mask_b;
+	uint8_t reg_gce_infra_req_mask_b;
+	uint8_t reg_gce_apsrc_req_mask_b;
+	uint8_t reg_gce_vrf18_req_mask_b;
+	uint8_t reg_gce_ddr_en_mask_b;
+	uint8_t reg_apu_srcclkena_mask_b;
+	uint8_t reg_apu_infra_req_mask_b;
+	uint8_t reg_apu_apsrc_req_mask_b;
+	uint8_t reg_apu_vrf18_req_mask_b;
+	uint8_t reg_apu_ddr_en_mask_b;
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	uint8_t reg_cg_check_ddr_en_mask_b;
+
+	/* SPM_SRC3_MASK */
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+	uint8_t reg_sw2spm_int0_mask_b;
+	uint8_t reg_sw2spm_int1_mask_b;
+	uint8_t reg_sw2spm_int2_mask_b;
+	uint8_t reg_sw2spm_int3_mask_b;
+	uint8_t reg_sc_adsp2spm_wakeup_mask_b;
+	uint8_t reg_sc_sspm2spm_wakeup_mask_b;
+	uint8_t reg_sc_scp2spm_wakeup_mask_b;
+	uint8_t reg_csyspwrreq_mask;
+	uint8_t reg_spm_srcclkena_reserved_mask_b;
+	uint8_t reg_spm_infra_req_reserved_mask_b;
+	uint8_t reg_spm_apsrc_req_reserved_mask_b;
+	uint8_t reg_spm_vrf18_req_reserved_mask_b;
+	uint8_t reg_spm_ddr_en_reserved_mask_b;
+	uint8_t reg_mcupm_srcclkena_mask_b;
+	uint8_t reg_mcupm_infra_req_mask_b;
+	uint8_t reg_mcupm_apsrc_req_mask_b;
+	uint8_t reg_mcupm_vrf18_req_mask_b;
+	uint8_t reg_mcupm_ddr_en_mask_b;
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	uint8_t reg_msdc0_infra_req_mask_b;
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	uint8_t reg_msdc0_ddr_en_mask_b;
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	uint8_t reg_msdc1_infra_req_mask_b;
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	uint8_t reg_msdc1_ddr_en_mask_b;
+
+	/* SPM_SRC4_MASK */
+	uint32_t ccif_event_mask_b;
+	uint8_t reg_bak_psri_srcclkena_mask_b;
+	uint8_t reg_bak_psri_infra_req_mask_b;
+	uint8_t reg_bak_psri_apsrc_req_mask_b;
+	uint8_t reg_bak_psri_vrf18_req_mask_b;
+	uint8_t reg_bak_psri_ddr_en_mask_b;
+	uint8_t reg_dramc0_md32_infra_req_mask_b;
+	uint8_t reg_dramc0_md32_vrf18_req_mask_b;
+	uint8_t reg_dramc1_md32_infra_req_mask_b;
+	uint8_t reg_dramc1_md32_vrf18_req_mask_b;
+	uint8_t reg_conn_srcclkenb2pwrap_mask_b;
+	uint8_t reg_dramc0_md32_wakeup_mask;
+	uint8_t reg_dramc1_md32_wakeup_mask;
+
+	/* SPM_SRC5_MASK */
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	uint32_t reg_mcusys_merge_ddr_en_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	uint32_t reg_ext_wakeup_event_mask;
+
+	/* Auto-gen End */
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+
+	/* SPM_CLK_CON */
+	PW_REG_SRCCLKEN0_CTL,
+	PW_REG_SRCCLKEN1_CTL,
+	PW_REG_SPM_LOCK_INFRA_DCM,
+	PW_REG_SRCCLKEN_MASK,
+	PW_REG_MD1_C32RM_EN,
+	PW_REG_MD2_C32RM_EN,
+	PW_REG_CLKSQ0_SEL_CTRL,
+	PW_REG_CLKSQ1_SEL_CTRL,
+	PW_REG_SRCCLKEN0_EN,
+	PW_REG_SRCCLKEN1_EN,
+	PW_REG_SYSCLK0_SRC_MASK_B,
+	PW_REG_SYSCLK1_SRC_MASK_B,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDR_EN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+
+	/* SPM_SRC_MASK */
+	PW_REG_MD_SRCCLKENA_0_MASK_B,
+	PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
+	PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
+	PW_REG_MD_APSRC_REQ_0_MASK_B,
+	PW_REG_MD_VRF18_REQ_0_MASK_B,
+	PW_REG_MD_DDR_EN_0_MASK_B,
+	PW_REG_MD_SRCCLKENA_1_MASK_B,
+	PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
+	PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
+	PW_REG_MD_APSRC_REQ_1_MASK_B,
+	PW_REG_MD_VRF18_REQ_1_MASK_B,
+	PW_REG_MD_DDR_EN_1_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_CONN_DDR_EN_MASK_B,
+	PW_REG_CONN_VFE28_MASK_B,
+	PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
+	PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
+	PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDR_EN_MASK_B,
+	PW_REG_MD32_SRCCLKENA_MASK_B,
+	PW_REG_MD32_INFRA_REQ_MASK_B,
+	PW_REG_MD32_APSRC_REQ_MASK_B,
+	PW_REG_MD32_VRF18_REQ_MASK_B,
+	PW_REG_MD32_DDR_EN_MASK_B,
+
+	/* SPM_SRC2_MASK */
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDR_EN_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDR_EN_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDR_EN_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDR_EN_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GCE_DDR_EN_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_APU_DDR_EN_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDR_EN_MASK_B,
+
+	/* SPM_SRC3_MASK */
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_SW2SPM_INT0_MASK_B,
+	PW_REG_SW2SPM_INT1_MASK_B,
+	PW_REG_SW2SPM_INT2_MASK_B,
+	PW_REG_SW2SPM_INT3_MASK_B,
+	PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRREQ_MASK,
+	PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
+	PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
+	PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
+	PW_REG_MCUPM_SRCCLKENA_MASK_B,
+	PW_REG_MCUPM_INFRA_REQ_MASK_B,
+	PW_REG_MCUPM_APSRC_REQ_MASK_B,
+	PW_REG_MCUPM_VRF18_REQ_MASK_B,
+	PW_REG_MCUPM_DDR_EN_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDR_EN_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDR_EN_MASK_B,
+
+	/* SPM_SRC4_MASK */
+	PW_CCIF_EVENT_MASK_B,
+	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+	PW_REG_BAK_PSRI_DDR_EN_MASK_B,
+	PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
+	PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+	PW_REG_DRAMC0_MD32_WAKEUP_MASK,
+	PW_REG_DRAMC1_MD32_WAKEUP_MASK,
+
+	/* SPM_SRC5_MASK */
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+	PW_MAX_COUNT,
+};
+
+
+#endif /* __PWR_CTRL_H__ */

drivers/misc/mediatek/lpm/modules/include/mt6885/mt6885_spm_comm.h

@@ -0,0 +1,238 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MT6885_SPM_COMM_H__
+#define __MT6885_SPM_COMM_H__
+
+struct mt6885_spm_wake_status {
+	u32 r12;			/* SPM_BK_WAKE_EVENT */
+	u32 r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	u32 raw_sta;		/* SPM_WAKEUP_STA */
+	u32 raw_ext_sta;	/* SPM_WAKEUP_EXT_STA */
+	u32 md32pcm_wakeup_sta;/* MD32CPM_WAKEUP_STA */
+	u32 md32pcm_event_sta;/* MD32PCM_EVENT_STA */
+	u32 wake_misc;		/* SPM_BK_WAKE_MISC */
+	u32 timer_out;		/* SPM_BK_PCM_TIMER */
+	u32 r13;			/* PCM_REG13_DATA */
+	u32 idle_sta;		/* SUBSYS_IDLE_STA */
+	u32 req_sta0;		/* SRC_REQ_STA_0 */
+	u32 req_sta1;		/* SRC_REQ_STA_1 */
+	u32 req_sta2;		/* SRC_REQ_STA_2 */
+	u32 req_sta3;		/* SRC_REQ_STA_3 */
+	u32 req_sta4;		/* SRC_REQ_STA_4 */
+	u32 cg_check_sta;	/* SPM_CG_CHECK_STA */
+	u32 debug_flag;		/* PCM_WDT_LATCH_SPARE_0 */
+	u32 debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	u32 b_sw_flag0;		/* SPM_SW_RSV_7 */
+	u32 b_sw_flag1;		/* SPM_SW_RSV_8 */
+	u32 isr;			/* SPM_IRQ_STA */
+	u32 sw_flag0;		/* SPM_SW_FLAG_0 */
+	u32 sw_flag1;		/* SPM_SW_FLAG_1 */
+	u32 clk_settle;		/* SPM_CLK_SETTLE */
+	u32 src_req;	/* SPM_SRC_REQ */
+	u32 log_index;
+	u32 is_abort;
+};
+
+struct spm_wakesrc_irq_list {
+	unsigned int wakesrc;
+	const char *name;
+	int order;
+	unsigned int irq_no;
+};
+
+enum MTK_LPM_SUSPEND_TYPE {
+	MTK_LPM_SUSPEND_SYSTEM,
+	MTK_LPM_SUSPEND_S2IDLE,
+};
+
+/* MD sleep status */
+
+struct md_sleep_status {
+	u64 sleep_wall_clk;
+	u64 sleep_cnt;
+	u64 sleep_cnt_reserve;
+	u64 sleep_time; // 32k
+	u64 sleep_time_reserve;
+	u64 md_sleep_time; // uS
+	u64 gsm_sleep_time; // uS
+	u64 wcdma_sleep_time; //uS
+	u64 lte_sleep_time; // uS
+	u64 nr_sleep_time; // uS
+};
+
+
+#define MTK_LP_PREPARE_FAIL		(1<<4L)
+
+/* Determine for operand bit */
+
+#define MTK_DUMP_LP_GOLDEN	(1 << 0L)
+#define MTK_DUMP_GPIO		(1 << 1L)
+#define PCM_32K_TICKS_PER_SEC	(32768)
+#define PCM_TICK_TO_SEC(TICK)	(TICK / PCM_32K_TICKS_PER_SEC)
+extern void mtk_suspend_gpio_dbg(void);
+extern void mtk_suspend_clk_dbg(void);
+extern u32 mt_irq_get_pending(unsigned int irq);
+extern u64 spm_26M_off_count;
+extern u64 spm_26M_off_duration;
+extern u64 ap_pd_count;
+extern u64 ap_slp_duration;
+int mtk_lpm_suspend_type_get(void);
+
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ * From Legacy sleep_def.h
+ */
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN		(1 << 0u)
+#define SPM_FLAG_DISABLE_INFRA_PDN		(1 << 1u)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN		(1 << 2u)
+#define SPM_FLAG_DISABLE_VCORE_DVS		(1 << 3u)
+#define SPM_FLAG_DISABLE_VCORE_DFS		(1 << 4u)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO	(1 << 5u)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF		(1 << 6u)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF		(1 << 7u)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH		(1 << 8u)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND		(1 << 9u)
+#define SPM_FLAG_RUN_COMMON_SCENARIO		(1 << 10u)
+#define SPM_FLAG_RESERVED_BIT11			(1 << 11u)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP	(1 << 12u)
+#define SPM_FLAG_USE_SRCCLKENO2			(1 << 13u)
+#define SPM_FLAG_ENABLE_6315_CTRL		(1 << 14u)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND		(1 << 15u)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP		(1 << 16u)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP	(1 << 17u)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP	(1 << 18u)
+#define SPM_FLAG_RESERVED_BIT19			(1 << 19u)
+#define SPM_FLAG_RESERVED_BIT20			(1 << 20u)
+#define SPM_FLAG_RESERVED_BIT21			(1 << 21u)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP	(1 << 22u)
+#define SPM_FLAG_RESERVED_BIT23			(1 << 23u)
+#define SPM_FLAG_RESERVED_BIT24			(1 << 24u)
+#define SPM_FLAG_RESERVED_BIT25			(1 << 25u)
+#define SPM_FLAG_RESERVED_BIT26			(1 << 26u)
+#define SPM_FLAG_VTCXO_STATE			(1 << 27u)
+#define SPM_FLAG_INFRA_STATE			(1 << 28u)
+#define SPM_FLAG_APSRC_STATE			(1 << 29u)
+#define SPM_FLAG_VRF18_STATE			(1 << 30u)
+#define SPM_FLAG_DDREN_STATE			(1 << 31u)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M      (1 << 0u)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF          (1 << 1u)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH    (1 << 2u)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF          (1 << 3u)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON            (1 << 4u)
+#define SPM_FLAG1_RESERVED_BIT5               (1 << 5u)
+#define SPM_FLAG1_ENABLE_REKICK               (1 << 6u)
+#define SPM_FLAG1_RESERVED_BIT7               (1 << 7u)
+#define SPM_FLAG1_RESERVED_BIT8               (1 << 8u)
+#define SPM_FLAG1_RESERVED_BIT9               (1 << 9u)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW         (1 << 10u)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH      (1 << 11u)
+#define SPM_FLAG1_RESERVED_BIT12              (1 << 12u)
+#define SPM_FLAG1_RESERVED_BIT13              (1 << 13u)
+#define SPM_FLAG1_RESERVED_BIT14              (1 << 14u)
+#define SPM_FLAG1_RESERVED_BIT15              (1 << 15u)
+#define SPM_FLAG1_RESERVED_BIT16              (1 << 16u)
+#define SPM_FLAG1_RESERVED_BIT17              (1 << 17u)
+#define SPM_FLAG1_RESERVED_BIT18              (1 << 18u)
+#define SPM_FLAG1_RESERVED_BIT19              (1 << 19u)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP   (1 << 20u)
+#define SPM_FLAG1_RESERVED_BIT21              (1 << 21u)
+#define SPM_FLAG1_ENABLE_VS1_VOTER            (1 << 22u)
+#define SPM_FLAG1_ENABLE_VS2_VOTER            (1 << 23u)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL   (1 << 24u)
+#define SPM_FLAG1_RESERVED_BIT25              (1 << 25u)
+#define SPM_FLAG1_RESERVED_BIT26              (1 << 26u)
+#define SPM_FLAG1_RESERVED_BIT27              (1 << 27u)
+#define SPM_FLAG1_RESERVED_BIT28              (1 << 28u)
+#define SPM_FLAG1_RESERVED_BIT29              (1 << 29u)
+#define SPM_FLAG1_RESERVED_BIT30              (1 << 30u)
+#define SPM_FLAG1_RESERVED_BIT31              (1 << 31u)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE			(1 << 0u)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP			(1 << 1u)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE			(1 << 2u)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP			(1 << 3u)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE			(1 << 4u)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP			(1 << 5u)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE			(1 << 6u)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP			(1 << 7u)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE			(1 << 8u)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP			(1 << 9u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC	(1 << 10u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE		(1 << 11u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE		(1 << 12u)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN	(1 << 13u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE		(1 << 14u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP			(1 << 15u)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON			(1 << 16u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP		(1 << 17u)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON			(1 << 18u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP			(1 << 19u)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON			(1 << 20u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP		(1 << 21u)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON		(1 << 22u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V		(1 << 23u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V		(1 << 24u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V		(1 << 25u)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V		(1 << 26u)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW		(1 << 27u)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE			(1 << 28u)
+#define SPM_DBG_DEBUG_IDX_VRF18_STATE			(1 << 29u)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE			(1 << 30u)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE			(1 << 31u)
+
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP		(1 << 0u)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START		(1 << 1u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF			(1 << 2u)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON			(1 << 3u)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS	(1 << 4u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF		(1 << 5u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON		(1 << 6u)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT		(1 << 7u)
+#define SPM_DBG1_RESERVED_BIT8				(1 << 8u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF		(1 << 9u)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON		(1 << 10u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC		(1 << 11u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M		(1 << 12u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K		(1 << 13u)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M		(1 << 14u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF			(1 << 15u)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON			(1 << 16u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW			(1 << 17u)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH		(1 << 18u)
+#define SPM_DBG1_RESERVED_BIT19				(1 << 19u)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	(1 << 20u)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW			(1 << 21u)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH                    (1 << 22u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT    (1 << 23u)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT   (1 << 24u)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT           (1 << 25u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT        (1 << 26u)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT       (1 << 27u)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT       (1 << 28u)
+#define SPM_DBG1_RESERVED_BIT29				(1 << 29u)
+#define SPM_DBG1_RESERVED_BIT30				(1 << 30u)
+#define SPM_DBG1_RESERVED_BIT31				(1 << 31u)
+
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC \
+	| SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT \
+	| SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6885/mtk_lp_plat_apmcu.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef __MTK_LP_PLAT_APMCU_H__
+#define __MTK_LP_PLAT_APMCU_H__
+
+#include <linux/types.h>
+
+#define nr_cluster_ids                  (1)
+#define get_physical_cluster_id(cpu)    (0)
+
+#define LP_PM_SYSRAM_INFO_OFS  0x8
+#define LP_PM_SYSRAM_SIZE      0x500
+
+extern void __iomem *cpu_pm_syssram_base;
+/* 0x11B000 */
+#define MT_CPU_PM_KERNEL_SRAMBASE	(cpu_pm_syssram_base + 0x100)
+#define MT_CPU_PM_KERNEL_SRAM(slot)	(MT_CPU_PM_KERNEL_SRAMBASE + (slot<<2))
+
+
+#define cpu_pm_sync_writel(v, a)				\
+do {								\
+	__raw_writel((v), (void __force __iomem *)((a)));	\
+	mb(); /*make sure register access in order */		\
+} while (0)
+
+#define MT_CPU_PM_KERNEL_SRAM_WR(slot, val) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			cpu_pm_sync_writel(val,\
+				MT_CPU_PM_KERNEL_SRAM(slot)); uval; })
+
+
+#define MT_CPU_PM_KERNEL_SRAM_RD(slot) ({\
+		unsigned int uval = 0;\
+		if (cpu_pm_syssram_base)\
+			uval = __raw_readl(MT_CPU_PM_KERNEL_SRAM(slot));\
+		uval; })
+
+void mtk_lp_plat_set_mcusys_off(int cpu);
+void mtk_lp_plat_clr_mcusys_off(int cpu);
+
+void mtk_lp_plat_set_cluster_off(int cpu);
+void mtk_lp_plat_clr_cluster_off(int cpu);
+
+bool mtk_lp_plat_is_mcusys_off(void);
+bool mtk_lp_plat_is_cluster_off(int cpu);
+
+int mtk_lp_plat_apmcu_init(void);
+int mtk_lp_plat_apmcu_early_init(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6885/mtk_lp_plat_apmcu_mbox.h

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_LP_PLAT_APMCU_MBOX_H__
+#define __MTK_LP_PLAT_APMCU_MBOX_H__
+
+enum {
+	MBOX_SSPM,
+	MBOX_MCUPM,
+
+	NF_MBOX,
+};
+
+/* SSPM Mbox */
+#define APMCU_SSPM_MBOX_ID           3
+#define APMCU_SSPM_MBOX_SPM_CMD_SIZE 8
+
+#define APMCU_SSPM_MBOX_SPM_CMD      0
+#define APMCU_SSPM_MBOX_SPM_ARGS1    1
+#define APMCU_SSPM_MBOX_SPM_ARGS2    2
+#define APMCU_SSPM_MBOX_SPM_ARGS3    3
+#define APMCU_SSPM_MBOX_SPM_ARGS4    4
+#define APMCU_SSPM_MBOX_SPM_ARGS5    5
+#define APMCU_SSPM_MBOX_SPM_ARGS6    6
+#define APMCU_SSPM_MBOX_SPM_ARGS7    7
+#define APMCU_SSPM_MBOX_AP_READY     17
+
+void mtk_set_sspm_lp_cmd(void *buf);
+void mtk_clr_sspm_lp_cmd(void);
+
+
+/* MCUPM Mbox */
+
+#define APMCU_MCUPM_MBOX_ID             3
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY       0
+#define APMCU_MCUPM_MBOX_RESERVED_1     1
+#define APMCU_MCUPM_MBOX_RESERVED_2     2
+#define APMCU_MCUPM_MBOX_RESERVED_3     3
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN    4
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE  5
+#define APMCU_MCUPM_MBOX_BUCK_MODE      6
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE    7
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA       8
+#define APMCU_MCUPM_MBOX_RESERVED_9     9
+#define APMCU_MCUPM_MBOX_RESERVED_10    10
+#define APMCU_MCUPM_MBOX_RESERVED_11    11
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU     12
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN (4) */
+#define MCUPM_MCUSYS_CTRL               (1 << 0)
+#define MCUPM_BUCK_CTRL                 (1 << 1)
+#define MCUPM_ARMPLL_CTRL               (1 << 2)
+#define MCUPM_CM_CTRL                   (1 << 3)
+#define MCUPM_PWR_CTRL_MASK             ((1 << 4) - 1)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_L3_CACHE_MODE (5) */
+#define MCUPM_L3_OFF_MODE               0 /* default */
+#define MCUPM_L3_DORMANT_MODE           1
+#define NF_MCUPM_L3_MODE                2U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE (6) */
+#define MCUPM_BUCK_NORMAL_MODE          0 /* default */
+#define MCUPM_BUCK_LP_MODE              1
+#define MCUPM_BUCK_OFF_MODE             2
+#define NF_MCUPM_BUCK_MODE              3U
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE (7) */
+#define MCUPM_ARMPLL_ON                 0 /* default */
+#define MCUPM_ARMPLL_GATING             1
+#define MCUPM_ARMPLL_OFF                2
+#define NF_MCUPM_ARMPLL_MODE            3U
+
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA (9) */
+#define MCUPM_TASK_UNINIT               0
+#define MCUPM_TASK_INIT                 1
+#define MCUPM_TASK_INIT_FINISH          2
+#define MCUPM_TASK_WAIT                 3
+#define MCUPM_TASK_RUN                  4
+#define MCUPM_TASK_PAUSE                5
+
+bool mtk_mcupm_cm_is_notified(void);
+
+void mtk_set_mcupm_pll_mode(unsigned int mode);
+int mtk_get_mcupm_pll_mode(void);
+
+void mtk_set_mcupm_buck_mode(unsigned int mode);
+int mtk_get_mcupm_buck_mode(void);
+
+void mtk_set_preferred_cpu_wakeup(int cpu);
+int mtk_get_preferred_cpu_wakeup(void);
+
+bool mtk_mcupm_is_ready(void);
+
+void mtk_wait_mbox_init_done(void);
+void mtk_notify_subsys_ap_ready(void);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6885/mtk_lp_plat_reg.h

@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_PLAT_CPC_REG_H__
+#define __MTK_PLAT_CPC_REG_H__
+
+/**************************************
+ * CPC related register
+ * base address = 0x0C53A000
+ **************************************/
+#define CPC_FLOW_CTRL_CFG              (0x814)
+#define CPC_MCUSYS_LAST_CORE_REQ       (0x818)
+#define CPC_CPUSYS_LAST_CORE_RESP      (0x81C)
+#define CPC_MCUSYS_LAST_CORE_RESP      (0x824)
+#define CPC_PWR_ON_MASK                (0x828)
+#define CPC_SPMC_PWR_STATUS            (0x840)
+#define CPC_CPUSYS_CPU_ON_SW_HINT_CLR  (0x8AC)
+
+#define SPMC_DBG_SETTING               (0xB00)
+
+#define CPC_TRACE_DATA_SEL             (0xB14)
+
+#define CPC_CPU0_LATENCY               (0xB40)
+#define CPC_CPU1_LATENCY               (0xB44)
+#define CPC_CPU2_LATENCY               (0xB48)
+#define CPC_CPU3_LATENCY               (0xB4C)
+#define CPC_CPU4_LATENCY               (0xB50)
+#define CPC_CPU5_LATENCY               (0xB54)
+#define CPC_CPU6_LATENCY               (0xB58)
+#define CPC_CPU7_LATENCY               (0xB5C)
+#define CPC_CLUSTER_OFF_LATENCY        (0xB60)
+#define CPC_CLUSTER_ON_LATENCY         (0xB64)
+#define CPC_MCUSYS_LATENCY             (0xB68)
+#define CPC_DORMANT_COUNTER            (0xB70)
+#define CPC_DORMANT_COUNTER_CLR        (0xB74)
+#define CPC_CPU_LATENCY(cpu)           ((CPC_CPU0_LATENCY) + 4 * (cpu))
+
+/**************************************
+ * system sram for apmcu debug
+ * base address = 0x0011B000
+ **************************************/
+#define SYSRAM_CPUSYS_CNT              (0x1E8)
+#define SYSRAM_MCUSYS_CNT              (0x1EC)
+#define SYSRAM_CPC_CPUSYS_CNT_BACKUP   (0x1F0)
+#define SYSRAM_MCUPM_MCUSYS_COUNTER    (0x1F4)
+#define SYSRAM_CPU_ONLINE              (0x1F8)
+
+/* Run time information. The registers may be cleared in db dump flow */
+#define SYSRAM_RECENT_CPU_CNT(i)       (4 * (i) + 0x1B0)
+#define SYSRAM_RECENT_CPUSYS_CNT       (0x1D0)
+#define SYSRAM_RECENT_MCUSYS_CNT       (0x1D4)
+#define SYSRAM_RECENT_CNT_TS_L         (0x1D8)
+#define SYSRAM_RECENT_CNT_TS_H         (0x1DC)
+
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mt6885/mtk_power_gs_array.h

@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+/* This file is generated by GenLP_setting.pl v1.5.7 */
+
+#ifndef MTK_POWER_GS_ARRAY_H
+#define MTK_POWER_GS_ARRAY_H
+
+extern void mt_power_gs_sp_dump(void);
+extern unsigned int golden_read_reg(unsigned int addr);
+
+/* PMIC 6359P */
+extern const unsigned int *AP_PMIC_REG_6359P_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_6359P_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_6359P_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_6359P_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_6359P_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_6359P_gs_suspend_32kless_len;
+
+/* PMIC 6315-1 */
+extern const unsigned int *AP_PMIC_REG_MT6315_1_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_1_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_1_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_1_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_1_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_1_gs_suspend_32kless_len;
+
+/* PMIC 6315-2 */
+extern const unsigned int *AP_PMIC_REG_MT6315_2_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_2_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_2_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_2_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_2_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_2_gs_suspend_32kless_len;
+
+/* PMIC 6315-3 */
+extern const unsigned int *AP_PMIC_REG_MT6315_3_gs_deepidle___lp_mp3_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_3_gs_deepidle___lp_mp3_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_3_gs_sodi3p0_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_3_gs_sodi3p0_32kless_len;
+
+extern const unsigned int *AP_PMIC_REG_MT6315_3_gs_suspend_32kless;
+extern unsigned int AP_PMIC_REG_MT6315_3_gs_suspend_32kless_len;
+
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_dpidle;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_dpidle_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_suspend;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_suspend_len;
+
+extern const unsigned int *AP_CG_Golden_Setting_tcl_gs_sodi;
+extern unsigned int AP_CG_Golden_Setting_tcl_gs_sodi_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_dpidle;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_dpidle_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_suspend;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_suspend_len;
+
+extern const unsigned int *AP_DCM_Golden_Setting_tcl_gs_sodi;
+extern unsigned int AP_DCM_Golden_Setting_tcl_gs_sodi_len;
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mtk_dbg_common_v1.h

@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_DBG_COMMON_H__
+#define __MTK_DBG_COMMON_H__
+
+/* For sysfs get the last wake status */
+enum mt_spm_wake_status_enum {
+	WAKE_STA_R12,
+	WAKE_STA_R12_EXT,
+	WAKE_STA_RAW_STA,
+	WAKE_STA_RAW_EXT_STA,
+	WAKE_STA_WAKE_MISC,
+	WAKE_STA_TIMER_OUT,
+	WAKE_STA_R13,
+	WAKE_STA_IDLE_STA,
+	WAKE_STA_REQ_STA,
+	WAKE_STA_DEBUG_FLAG,
+	WAKE_STA_DEBUG_FLAG1,
+	WAKE_STA_ISR,
+
+	WAKE_STA_MAX_COUNT,
+};
+
+enum {
+	WR_NONE = 0,
+	WR_UART_BUSY = 1,
+	WR_ABORT = 2,
+	WR_PCM_TIMER = 3,
+	WR_WAKE_SRC = 4,
+	WR_DVFSRC = 5,
+	WR_PMSR = 6,
+	WR_TWAM = 7,
+	WR_SPM_ACK_CHK = 8,
+	WR_UNKNOWN = 9,
+};
+
+
+/* enum for smc resource request arg */
+enum MT_SPM_RES_TYPE {
+	MT_SPM_RES_XO_FPM,
+	MT_SPM_RES_CK_26M,
+	MT_SPM_RES_INFRA,
+	MT_SPM_RES_SYSPLL,
+	MT_SPM_RES_DRAM_S0,
+	MT_SPM_RES_DRAM_S1,
+	MT_SPM_RES_MAX,
+};
+
+enum dbg_ctrl_enum {
+	DBG_CTRL_COUNT,
+	DBG_CTRL_DURATION,
+	DBG_CTRL_MAX,
+};
+
+struct dbg_ctrl {
+	u32 count;
+	u32 duration;
+};
+
+int mtk_dbg_common_fs_init(void);
+
+void mtk_dbg_common_fs_exit(void);
+
+
+#endif /* __MTK_DBG_COMMON_H__ */

drivers/misc/mediatek/lpm/modules/include/mtk_ipi_sspm_v1.h

@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_IPI_SSPM_V1__
+#define __MTK_IPI_SSPM_V1__
+
+/* cmd flag for sspm sleep task */
+enum {
+	SSPM_SPM_SUSPEND,
+	SSPM_SPM_RESUME,
+	SSPM_SPM_DPIDLE_ENTER,
+	SSPM_SPM_DPIDLE_LEAVE,
+	SSPM_SPM_ENTER_SODI,
+	SSPM_SPM_LEAVE_SODI,
+	SSPM_SPM_ENTER_SODI3,
+	SSPM_SPM_LEAVE_SODI3,
+	SSPM_SPM_SUSPEND_PREPARE,
+	SSPM_SPM_POST_SUSPEND,
+	SSPM_SPM_DPIDLE_PREPARE,
+	SSPM_SPM_POST_DPIDLE,
+	SSPM_SPM_SODI_PREPARE,
+	SSPM_SPM_POST_SODI,
+	SSPM_SPM_SODI3_PREPARE,
+	SSPM_SPM_POST_SODI3,
+	SSPM_SPM_VCORE_PWARP_CMD,
+	SSPM_SPM_PWR_CTRL_SUSPEND,
+	SSPM_SPM_PWR_CTRL_DPIDLE,
+	SSPM_SPM_PWR_CTRL_SODI,
+	SSPM_SPM_PWR_CTRL_SODI3,
+	SSPM_SPM_PWR_CTRL_VCOREFS,
+	SSPM_SPM_TWAM_ENABLE,
+	SSPM_SPM_PWR_CTRL_IDLE_DRAM,
+	SSPM_SPM_PWR_CTRL_IDLE_SYSPLL,
+	SSPM_SPM_PWR_CTRL_IDLE_BUS26M,
+};
+enum {
+	PLAT_PWR_OPT_SLEEP_DPIDLE  = (1 << 0),
+	PLAT_PWR_OPT_UNIVPLL_STAT  = (1 << 1),
+	PLAT_PWR_OPT_GPS_STAT      = (1 << 2),
+	PLAT_PWR_OPT_VCORE_LP_MODE = (1 << 3),
+	PLAT_PWR_OPT_XO_UFS_OFF    = (1 << 4),
+	PLAT_PWR_OPT_CLKBUF_ENTER_BBLPM = (1 << 5),
+	NF_PWR_OPT
+};
+struct plat_spm_data {
+	unsigned int cmd;
+	union {
+		struct {
+			unsigned int sys_timestamp_l;
+			unsigned int sys_timestamp_h;
+			unsigned int sys_src_clk_l;
+			unsigned int sys_src_clk_h;
+			unsigned int spm_opt;
+		} suspend;
+		struct {
+			unsigned int vcore_level0;
+			unsigned int vcore_level1;
+			unsigned int vcore_level2;
+			unsigned int vcore_level3;
+		} vcorefs;
+		struct {
+			unsigned int args1;
+			unsigned int args2;
+			unsigned int args3;
+			unsigned int args4;
+			unsigned int args5;
+			unsigned int args6;
+			unsigned int args7;
+		} args;
+	} u;
+};
+#define SSPM_SPM_DATA_LEN   (8)
+
+enum {
+	SSPM_NOTIFY_ENTER,
+	SSPM_NOTIFY_LEAVE,
+	SSPM_NOTIFY_ENTER_ASYNC,
+	SSPM_NOTIFY_LEAVE_ASYNC,
+};
+
+#endif
+

drivers/misc/mediatek/lpm/modules/include/mtk_lpm_timer.h

@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_LPM_TIMER__
+#define __MTK_LPM_TIMER__
+
+#include <linux/ktime.h>
+#include <linux/timer.h>
+#include <linux/time.h>
+#include <linux/jiffies.h>
+
+enum MTK_LPM_TIMER_TYPE {
+	MTK_LPM_TIMER_ONECE,
+	MTK_LPM_TIMER_REPEAT
+};
+
+struct mt_lpm_timer {
+	int type;
+	unsigned long interval;
+	unsigned long cur;
+	int (*timeout)(unsigned long long dur, void *priv);
+	void *priv;
+	struct timer_list tm;
+};
+
+int mtk_lpm_timer_is_running(struct mt_lpm_timer *timer);
+
+int mtk_lpm_timer_init(struct mt_lpm_timer *timer, int type);
+
+int mtk_lpm_timer_start(struct mt_lpm_timer *timer);
+
+void mtk_lpm_timer_stop(struct mt_lpm_timer *timer);
+
+int mtk_lpm_timer_interval_update(struct mt_lpm_timer *timer,
+					 unsigned long long ms);
+
+unsigned long mtk_lpm_timer_interval(struct mt_lpm_timer *timer);
+
+#endif

drivers/misc/mediatek/lpm/modules/include/mtk_resource_constraint_v1.h

@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_RESOURCE_CONSTRAINT_V1_H__
+#define __MTK_RESOURCE_CONSTRAINT_V1_H__
+
+/* Please refer platform mt_spm.h at atf code for constraint id definition */
+enum MT_SPM_RM_RC_TYPE {
+	MT_RM_CONSTRAINT_ID_BUS26M,
+	MT_RM_CONSTRAINT_ID_SYSPLL,
+	MT_RM_CONSTRAINT_ID_DRAM,
+	MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
+	MT_RM_CONSTRAINT_ID_ALL,
+};
+
+#define MT_SPM_RC_INVALID		(0x0)
+#define MT_SPM_RC_VALID_SW		(1<<0L)
+#define MT_SPM_RC_VALID_FW		(1<<1L)
+#define MT_SPM_RC_VALID_RESIDNECY	(1<<2L)
+#define MT_SPM_RC_VALID_COND_CHECK	(1<<3L)
+#define MT_SPM_RC_VALID_COND_LATCH	(1<<4L)
+#define MT_SPM_RC_VALID_UFS_H8		(1<<5L)
+#define MT_SPM_RC_VALID_FLIGHTMODE	(1<<6L)
+
+
+/* MT_RM_CONSTRAINT_SW_VALID | MT_RM_CONSTRAINT_FW_VALID */
+#define MT_RM_CONSTRAINT_VALID          (0x11)
+
+/* Please refer mt_lp_rm.h at atf code */
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK		(1<<0L)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_EVENT	(1<<1L)
+#define MT_RM_CONSTRAINT_ALLOW_SYSPLL_EVENT	(1<<2L)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_EVENT	(1<<3L)
+#define MT_RM_CONSTRAINT_ALLOW_26M_EVENT	(1<<4L)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP		(1<<5L)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN	(1<<6L)
+#define MT_RM_CONSTRAINT_ALLOW_26M_OFF		(1<<7L)
+
+/*
+ * 1. 26m clk	[OFF]
+ * 2. infra pwr	[ON]
+ * 3. mainpll	[OFF]
+ * 4. vcore low power mode
+ */
+#define VCORE_LP_CLK_26M_OFF (\
+	MT_RM_CONSTRAINT_ALLOW_VCORE_LP\
+	| MT_RM_CONSTRAINT_ALLOW_26M_OFF)
+
+/*
+ * 1. 26m clk	[ON]
+ * 2. infra pwr	[ON]
+ * 3. mainpll	[OFF]
+ * 4. vcore low power mode
+ */
+#define VCORE_LP_CLK_26M_ON (\
+	MT_RM_CONSTRAINT_ALLOW_VCORE_LP\
+	| MT_RM_CONSTRAINT_ALLOW_26M_EVENT)
+
+/*
+ * 1. 26m clk	[OFF]
+ * 2. mainpll	[OFF]
+ * 3. infra pwr	[OFF]
+ * 4. vcore low power mode
+ */
+#define VCORE_LP_CLK_26M_INFRA_PDN (\
+	MT_RM_CONSTRAINT_ALLOW_VCORE_LP\
+	| MT_RM_CONSTRAINT_ALLOW_INFRA_PDN\
+	| MT_RM_CONSTRAINT_ALLOW_26M_OFF)
+
+
+/* mainpll	[OFF] */
+#define MAINPLL_OFF (\
+	MT_RM_CONSTRAINT_ALLOW_SYSPLL_EVENT)
+
+
+#define DRAM_OFF (\
+	MT_RM_CONSTRAINT_ALLOW_DRAM_EVENT)
+
+
+#define CPU_BUCK_OFF (\
+	MT_RM_CONSTRAINT_ALLOW_CPU_BUCK)
+
+
+#define MT_RM_STATUS_CHECK(status, flag)\
+				((status & flag) == flag)
+
+
+#endif